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[/] [ethmac10g/] [tags/] [V10/] [rtl/] [verilog/] [rx_engine/] [rxCRC.v] - Blame information for rev 39

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//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// MODULE NAME: rxCRC                                                                                                 ////
////                                                                                                                                                                    ////
//// DESCRIPTION: CRC Checker, by using magic word c704dd7b.      ////
////                                                              ////
////                                                                                                                                                                    ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                                              ////
////                                                                                                                                                                    ////
//// AUTHOR(S):                                                                                                                                 ////
//// Zheng Cao                                                               ////
////                                                                                                    ////
//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////
////                                                                                                                                                                    ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                                                   ////
////                                                                                                                                                                    ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxCRC(rxclk, reset, receiving, receiving_d1, CRC_DATA, get_terminator,
 get_terminator_d1, wait_crc_check,crc_check_invalid, crc_check_valid, terminator_location,get_error_code);
    input rxclk;
    input reset;
         input get_terminator;
    input [63:0] CRC_DATA;
         input receiving;
         input receiving_d1;
         input [2:0] terminator_location;
         input wait_crc_check;
 
         output crc_check_invalid;
         output crc_check_valid;
         output get_terminator_d1;
         input get_error_code;
 
         parameter TP = 1;
 
         /////////////////////////////////////////////////////////////////////////////////////////////
         // Input registers
         /////////////////////////////////////////////////////////////////////////////////////////////
 
         reg get_terminator_d1, get_terminator_d2,get_terminator_d3;
         always@(posedge rxclk or posedge reset) begin
              if(reset)begin
                          get_terminator_d1 <=#TP 0;
                          get_terminator_d2 <=#TP 0;
                          get_terminator_d3 <=#TP 0;
                        end
                        else begin
                          get_terminator_d1 <=#TP get_terminator;
                          get_terminator_d2 <=#TP get_terminator_d1;
                          get_terminator_d3 <=#TP get_terminator_d2;
                        end
         end
 
         reg[2:0] bytes_cnt;
         reg crc_8_en;//enable 8bit CRC
         always@(posedge rxclk or posedge reset) begin
              if (reset)
                           bytes_cnt <=#TP 0;
                        else if (get_terminator)
                           bytes_cnt <=#TP terminator_location;
                        else if (crc_8_en)
                           bytes_cnt <=#TP bytes_cnt-1;
         end
 
         reg[63:0] terminator_data;
         always@(posedge rxclk or posedge reset) begin
              if(reset)
                           terminator_data <=#TP 0;
                        else if (get_terminator_d2)
                                terminator_data <=#TP CRC_DATA;
                        else
                           terminator_data <=#TP terminator_data<<8;
         end
 
         /////////////////////////////////////////////////////////////////////////////////////////////
         // 64bits CRC 
         // start: crc_valid = 8'hff and receiving_frame = 1
         // end  : crc_valid != 8'hff or receiving_frame = 0
         // if bits_more is 0, then CRC check will happen when end happens.
    // else 8bits CRC should begin
         /////////////////////////////////////////////////////////////////////////////////////////////
 
    wire [31:0] crc_from_64;
 
         reg crc_64_en; // 64bit CRC Enable
         always@(posedge rxclk or posedge reset) begin
               if(reset)
                           crc_64_en <= #TP 1'b0;
                         else if(get_error_code) //if error, stop crc checking
                           crc_64_en <= #TP 1'b0;
                         else if(receiving_d1 & receiving)
                           crc_64_en <= #TP 1'b1;
                         else
                           crc_64_en <= #TP 1'b0;
         end
 
         CRC32_D64 crc64(.DATA_IN(CRC_DATA), .CLK(rxclk), .RESET(reset), .START(crc_64_en), .CRC_OUT(crc_from_64), .init(get_terminator_d3|get_error_code));
 
         /////////////////////////////////////////////////////////////////////////////////////////////
         // 8bits CRC
         /////////////////////////////////////////////////////////////////////////////////////////////
 
         reg[7:0] CRC_DATA_TMP;
    always@(posedge rxclk or posedge reset) begin
              if(reset)
                          CRC_DATA_TMP <=#TP 0;
                        else
           CRC_DATA_TMP <=#TP terminator_data[63:56];
    end
 
         always@(posedge rxclk or posedge reset) begin
              if(reset)
                          crc_8_en <=#TP 0;
                        else if (get_terminator_d3)
           crc_8_en <=#TP 1'b1;
         else if(bytes_cnt==1)
           crc_8_en <=#TP 1'b0;
         end
 
         reg do_crc_check;
         always@(posedge rxclk or posedge reset) begin
              if (reset)
                           do_crc_check <=#TP 0;
                        else if(terminator_location == 0)
                do_crc_check <=#TP get_terminator_d2;
                        else
                           do_crc_check <=#TP wait_crc_check & (bytes_cnt==1);
    end
 
         wire[31:0] crc_from_8;
         CRC32_D8  crc8(.DATA_IN(CRC_DATA_TMP), .CLK(rxclk), .RESET(reset), .START(crc_8_en), .LOAD(~crc_8_en), .CRC_IN(crc_from_64), .CRC_OUT(crc_from_8));
 
    ////////////////////////////////////////////////////////////////////////////////////////////
    // CRC check
         ////////////////////////////////////////////////////////////////////////////////////////////
         wire crc_check_valid, crc_check_invalid;
 
         assign crc_check_valid  = wait_crc_check & do_crc_check & (crc_from_8==32'hc704dd7b);
         assign crc_check_invalid = wait_crc_check & do_crc_check  & (crc_from_8!=32'hc704dd7b);
 
endmodule

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MODULE NAME: rxCRC ////`
4			`//// ////`
5			`//// DESCRIPTION: CRC Checker, by using magic word c704dd7b. ////`
6			`//// ////`
7			`//// ////`
8			`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
9			`//// http://www.opencores.org/projects/ethmac10g/ ////`
10			`//// ////`
11			`//// AUTHOR(S): ////`
12			`//// Zheng Cao ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS REVISION HISTORY:`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
45			`//`
46			`//`
47			`//`
48			`//////////////////////////////////////////////////////////////////////`
49
50			`include "timescale.v"
51			`include "xgiga_define.v"
52
53			`module rxCRC(rxclk, reset, receiving, receiving_d1, CRC_DATA, get_terminator,`
54			`get_terminator_d1, wait_crc_check,crc_check_invalid, crc_check_valid, terminator_location,get_error_code);`
55			`input rxclk;`
56			`input reset;`
57			`input get_terminator;`
58			`input [63:0] CRC_DATA;`
59			`input receiving;`
60			`input receiving_d1;`
61			`input [2:0] terminator_location;`
62			`input wait_crc_check;`
63
64			`output crc_check_invalid;`
65			`output crc_check_valid;`
66			`output get_terminator_d1;`
67			`input get_error_code;`
68
69			`parameter TP = 1;`
70
71			`/////////////////////////////////////////////////////////////////////////////////////////////`
72			`// Input registers`
73			`/////////////////////////////////////////////////////////////////////////////////////////////`
74
75			`reg get_terminator_d1, get_terminator_d2,get_terminator_d3;`
76			`always@(posedge rxclk or posedge reset) begin`
77			`if(reset)begin`
78			`get_terminator_d1 <=#TP 0;`
79			`get_terminator_d2 <=#TP 0;`
80			`get_terminator_d3 <=#TP 0;`
81			`end`
82			`else begin`
83			`get_terminator_d1 <=#TP get_terminator;`
84			`get_terminator_d2 <=#TP get_terminator_d1;`
85			`get_terminator_d3 <=#TP get_terminator_d2;`
86			`end`
87			`end`
88
89			`reg[2:0] bytes_cnt;`
90			`reg crc_8_en;//enable 8bit CRC`
91			`always@(posedge rxclk or posedge reset) begin`
92			`if (reset)`
93			`bytes_cnt <=#TP 0;`
94			`else if (get_terminator)`
95			`bytes_cnt <=#TP terminator_location;`
96			`else if (crc_8_en)`
97			`bytes_cnt <=#TP bytes_cnt-1;`
98			`end`
99
100			`reg[63:0] terminator_data;`
101			`always@(posedge rxclk or posedge reset) begin`
102			`if(reset)`
103			`terminator_data <=#TP 0;`
104			`else if (get_terminator_d2)`
105			`terminator_data <=#TP CRC_DATA;`
106			`else`
107			`terminator_data <=#TP terminator_data<<8;`
108			`end`
109
110			`/////////////////////////////////////////////////////////////////////////////////////////////`
111			`// 64bits CRC`
112			`// start: crc_valid = 8'hff and receiving_frame = 1`
113			`// end : crc_valid != 8'hff or receiving_frame = 0`
114			`// if bits_more is 0, then CRC check will happen when end happens.`
115			`// else 8bits CRC should begin`
116			`/////////////////////////////////////////////////////////////////////////////////////////////`
117
118			`wire [31:0] crc_from_64;`
119
120			`reg crc_64_en; // 64bit CRC Enable`
121			`always@(posedge rxclk or posedge reset) begin`
122			`if(reset)`
123			`crc_64_en <= #TP 1'b0;`
124			`else if(get_error_code) //if error, stop crc checking`
125			`crc_64_en <= #TP 1'b0;`
126			`else if(receiving_d1 & receiving)`
127			`crc_64_en <= #TP 1'b1;`
128			`else`
129			`crc_64_en <= #TP 1'b0;`
130			`end`
131
132			`CRC32_D64 crc64(.DATA_IN(CRC_DATA), .CLK(rxclk), .RESET(reset), .START(crc_64_en), .CRC_OUT(crc_from_64), .init(get_terminator_d3\|get_error_code));`
133
134			`/////////////////////////////////////////////////////////////////////////////////////////////`
135			`// 8bits CRC`
136			`/////////////////////////////////////////////////////////////////////////////////////////////`
137
138			`reg[7:0] CRC_DATA_TMP;`
139			`always@(posedge rxclk or posedge reset) begin`
140			`if(reset)`
141			`CRC_DATA_TMP <=#TP 0;`
142			`else`
143			`CRC_DATA_TMP <=#TP terminator_data[63:56];`
144			`end`
145
146			`always@(posedge rxclk or posedge reset) begin`
147			`if(reset)`
148			`crc_8_en <=#TP 0;`
149			`else if (get_terminator_d3)`
150			`crc_8_en <=#TP 1'b1;`
151			`else if(bytes_cnt==1)`
152			`crc_8_en <=#TP 1'b0;`
153			`end`
154
155			`reg do_crc_check;`
156			`always@(posedge rxclk or posedge reset) begin`
157			`if (reset)`
158			`do_crc_check <=#TP 0;`
159			`else if(terminator_location == 0)`
160			`do_crc_check <=#TP get_terminator_d2;`
161			`else`
162			`do_crc_check <=#TP wait_crc_check & (bytes_cnt==1);`
163			`end`
164
165			`wire[31:0] crc_from_8;`
166			`CRC32_D8 crc8(.DATA_IN(CRC_DATA_TMP), .CLK(rxclk), .RESET(reset), .START(crc_8_en), .LOAD(~crc_8_en), .CRC_IN(crc_from_64), .CRC_OUT(crc_from_8));`
167
168			`////////////////////////////////////////////////////////////////////////////////////////////`
169			`// CRC check`
170			`////////////////////////////////////////////////////////////////////////////////////////////`
171			`wire crc_check_valid, crc_check_invalid;`
172
173			`assign crc_check_valid = wait_crc_check & do_crc_check & (crc_from_8==32'hc704dd7b);`
174			`assign crc_check_invalid = wait_crc_check & do_crc_check & (crc_from_8!=32'hc704dd7b);`
175
176			`endmodule`

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[/] [ethmac10g/] [tags/] [V10/] [rtl/] [verilog/] [rx_engine/] [rxCRC.v] - Blame information for rev 39