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[/] [ethmac10g/] [tags/] [V10/] [rtl/] [verilog/] [rx_engine/] [rxDataPath.v] - Blame information for rev 72

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//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// MODULE NAME: Data Path of Receive Module                                                   ////
////                                                                                                                                                                    ////
//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit       ////
////     Ethernet MAC. Used to recognize every field of a         ////
////     frame, including SOF, EOF, Length, Destination Addr            ////
////     , Source Addr and Data field.                            ////
////                                                                                                                                                                    ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                                              ////
////                                                                                                                                                                    ////
//// AUTHOR(S):                                                                                                                                 ////
//// Zheng Cao                                                               ////
////                                                                                                    ////
//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////
////                                                                                                                                                                    ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                                                   ////
////                                                                                                                                                                    ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,
                  get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,
                                                rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);
//                                    fcTxPauseData);
    input rxclk;
    input reset;
    input [63:0] rxd64;
    input [7:0] rxc8;
         input inband_fcs;
         input receiving;
         input start_da;
         input start_lt;
         input wait_crc_check;
         input get_terminator_d1;
         input bad_frame_get;
         input good_frame_get;
 
         output get_sfd;
         output get_terminator; //get T indicator
         output get_error_code; //get Error indicator
    output tagged_frame;
         output pause_frame;
         output[47:0] da_addr;
         output[2:0] terminator_location;
    output[63:0] CRC_DATA;
         output[7:0] rx_data_valid;
         output[63:0] rx_data;
         output check_reset;
         output rx_good_frame;
         output rx_bad_frame;
//       output [31:0]fcTxPauseData;
 
         parameter TP = 1;
         parameter IDLE = 0, READ = 1, WAIT_TMP = 2, WAIT = 3;
 
         //////////////////////////////////////////////
         // Pipe Line Stage
         //////////////////////////////////////////////
         reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
         reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;
         reg receiving_d1, receiving_d2;
         reg wait_crc_check_d1;
 
//       assign fcTxPauseData = rxd64_d1[31:0];
         // Data pipeline
         always@(posedge rxclk or posedge reset) begin
               if (reset)       begin
                                 rxd64_d1<=#TP 0;
                                 rxd64_d2<=#TP 0;
                                 rxd64_d3<=#TP 0;
                         CRC_DATA<=0;
 
                         end
                         else begin
                                 rxd64_d1<=#TP rxd64;
                                 rxd64_d2<=#TP rxd64_d1;
                                 rxd64_d3<=#TP rxd64_d2;
                                 CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],
                        rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],
                        rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],
                        rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],
                        rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],
                        rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],
                        rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],
                        rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};
                        end
         end
         //control pipeline
         always@(posedge rxclk or posedge reset)begin
              if (reset)        begin
                                 rxc8_d1<=#TP 0;
                                 rxc8_d2<=#TP 0;
                                 rxc8_d3<=#TP 0;
                         end
                         else begin
                                 rxc8_d1<=#TP rxc8;
                                 rxc8_d2<=#TP rxc8_d1;
                                 rxc8_d3<=#TP rxc8_d2;
                         end
         end
 
         always @(posedge rxclk or posedge reset)begin
               if (reset) begin
                            receiving_d1 <=#TP 0;
                                 receiving_d2 <=#TP 0;
                                 wait_crc_check_d1 <=#TP 0;
                         end
                         else   begin
                            receiving_d1 <=#TP receiving;
                                 receiving_d2 <=#TP receiving_d1;
                                 wait_crc_check_d1 <=#TP wait_crc_check;
                         end
         end
 
         ////////////////////////////////////////////
         // Frame analysis
         ////////////////////////////////////////////
         reg get_sfd; //get sfd indicator
         reg get_terminator; //get T indicator
         reg get_error_code; //get Error indicator
         reg[7:0] get_e_chk;
         reg[7:0] rxc_end_data; //seperate DATA with FCS
         reg [2:0]terminator_location; //for n*8bits(n<8), get n
         reg[47:0] da_addr; //get Desetination Address
         reg tagged_frame;  //Tagged frame indicator(type interpret)
         reg pause_frame;   //Pause frame indicator(type interpret)
 
         //1. SFD 
         always@(posedge rxclk or posedge reset) begin
               if (reset)
                            get_sfd <=#TP 0;
                         else
                            get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
         end
 
         //2. EFD
         reg this_cycle;
         // -----------------------------------------------
         //|  0  |  1  |  2  |  3  |  4  |  5  |  6  |  7  | 
         // -----------------------------------------------
         //|<-------- EFD -------->|<-------- EFD -------->|
         //|<-- this_cycle = '1' ->|<-- this_cycle = '0' ->|
 
         always@(posedge rxclk or posedge reset) begin
               if (reset)       begin
                            get_terminator <=#TP 0;
                                 terminator_location <=#TP 0;
                            this_cycle <=#TP 1'b0;
                            rxc_end_data <=#TP 0;
                         end
                         else begin
                            if (rxc8[0] & (rxd64[7:0]  ==`TERMINATE)) begin
                                     get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 0;
                                          this_cycle <=#TP 1'b1;
                                          rxc_end_data <=#TP 8'b00001111;
                            end
                            else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
                                     get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 1;
                                          this_cycle <=#TP 1'b1;
                                          rxc_end_data <=#TP 8'b00011111;
                                 end
                                 else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
                 get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 2;
                 this_cycle <=#TP 1'b1;
                                          rxc_end_data <=#TP 8'b00111111;
                                 end
                                 else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
                 get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 3;
                 this_cycle <=#TP 1'b1;
                                          rxc_end_data <=#TP 8'b01111111;
                                 end
             else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
                                     get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 4;
                 this_cycle <=#TP 1'b1;
                                          rxc_end_data <=#TP 8'b11111111;
                                 end
                                 else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
                 get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 5;
                                          this_cycle <=#TP 1'b0;
                                          rxc_end_data <=#TP 8'b00000001;
                                 end
                                 else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
                 get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 6;
                                          this_cycle <=#TP 1'b0;
                                          rxc_end_data <=#TP 8'b00000011;
                                 end
                                 else if (rxc8[7] & (rxd64[63:56]==`TERMINATE)) begin
                 get_terminator <=#TP 1'b1;
                                          terminator_location <=#TP 7;
                                          this_cycle <=#TP 1'b0;
                                          rxc_end_data <=#TP 8'b00000111;
                                 end
                                 else   begin
                                     get_terminator <=#TP 1'b0;
                                          terminator_location <=#TP terminator_location;
                                          this_cycle <=#TP this_cycle;
                                          rxc_end_data <=#TP rxc_end_data;
                                 end
                         end
         end
 
         //3. Error Character
    always@(posedge rxclk or posedge reset) begin
               if (reset)
                            get_e_chk <=#TP 0;
                         else begin
                                 get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0]  ==`ERROR);
                            get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
             get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
             get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
             get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
             get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
             get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
             get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
                         end
         end
 
         always@(posedge rxclk or posedge reset) begin
               if (reset)
                            get_error_code <=#TP 0;
          else
                            get_error_code <=#TP receiving & (| get_e_chk);
         end
 
         //////////////////////////////////////
         // Get Destination Address
         //////////////////////////////////////
 
         always@(posedge rxclk or posedge reset)begin
       if (reset)
               da_addr <=#TP 0;
         else if (start_da)
               da_addr <=#TP rxd64_d1[47:0];
                 else
                    da_addr <=#TP da_addr;
    end
 
         //////////////////////////////////////
         // Get Length/Type Field
         //////////////////////////////////////
 
//       reg[15:0] lt_data; 
//       always@(posedge rxclk or posedge reset)begin
//       if (reset) 
//             lt_data <=#TP 0;
//       else if (start_lt) 
//             lt_data <=#TP rxd64_d1[47:32];
//               else
//                  lt_data <=#TP lt_data;
//    end
 
    //tagged frame indicator
         always@(posedge rxclk or posedge reset) begin
            if (reset)
                    tagged_frame <=#TP 1'b0;
       else     if (start_lt)
                    tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
                 else
                    tagged_frame <=#TP tagged_frame;
         end
         //pause frame indicator
         always@(posedge rxclk or posedge reset) begin
            if (reset)
                    pause_frame <=#TP 1'b0;
       else     if (start_lt)
                    pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
                 else
                    pause_frame <=#TP 1'b0;
         end
 
    /////////////////////////////////////////////
    // Generate proper rxc to FIFO                                              
    /////////////////////////////////////////////
 
         reg [7:0]rxc_final;
         wire [7:0]rxc_fifo; //rxc send to fifo
 
    always@(posedge rxclk or posedge reset) begin
               if (reset)
                            rxc_final <=#TP 0;
                         else if (get_terminator & this_cycle)
             rxc_final <=#TP rxc_end_data;
                         else if (get_terminator_d1 & ~this_cycle)
                            rxc_final <=#TP rxc_end_data;
          else if (receiving)
             rxc_final <=`ALLONES8;
                         else
                            rxc_final <=0;
    end
 
         assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;
 
    ////////////////////////////////////////////////////////////////
    // FIFO management, to generate rx_good_frame/rx_bad_frame
    // after a frame has been totally received.
    ////////////////////////////////////////////////////////////////
         wire rxfifo_full;
         wire rxfifo_empty;
         wire fifo_wr_en;
    wire [63:0] rx_data_tmp;
         wire [7:0] rx_data_valid_tmp;
 
         reg one_frame_end;
         always@(posedge rxclk or posedge reset) begin
                if(reset)
                            one_frame_end <= 1'b0;
                          else if(rx_data_valid_tmp!=8'hff)
                            one_frame_end <= 1'b1;
                          else
             one_frame_end <= 1'b0;
         end
 
         reg fifo_rd_en;
         reg[1:0] fifo_state;
         reg rx_good_frame;
         reg rx_bad_frame;
         reg check_reset;
         always@(posedge rxclk or posedge reset) begin
               if(reset) begin
                           fifo_rd_en <= 1'b0;
                           fifo_state <= IDLE;
                                rx_good_frame <= 1'b0;
                                rx_bad_frame <= 1'b0;
                                check_reset <= 1'b0;
                         end
                         else
            case (fifo_state)
              IDLE: begin
                                      rx_good_frame <= 1'b0;
                                                rx_bad_frame <= 1'b0;
                                                check_reset <= 1'b0;
                  fifo_state <= IDLE;
                                                fifo_rd_en <= 1'b0;
                  if(~rxfifo_empty) begin
                    fifo_rd_en <= 1'b1;
                    fifo_state <= READ;
                                                end
              end
              READ: begin
                                      check_reset <= 1'b0;
                  fifo_rd_en <= 1'b1;
                                                rx_good_frame <= 1'b0;
                                                rx_bad_frame <= 1'b0;
                                                fifo_state <= READ;
                  if(rx_data_valid_tmp!=8'hff)
                    fifo_state <= WAIT_TMP;
                                  end
                                  WAIT_TMP: begin
                                      if(rx_data_valid_tmp!=8'hff)
                    fifo_state <= WAIT;
              end
                                  WAIT: begin
                  rx_good_frame <= 1'b0;
                  rx_bad_frame <= 1'b0;
                  fifo_state <= WAIT;
                  check_reset <= 1'b0;
                  fifo_rd_en <= 1'b0;
                  if(bad_frame_get | good_frame_get)begin
                                                  rx_good_frame <= good_frame_get;
                                                  rx_bad_frame <= bad_frame_get;
                    fifo_state <= IDLE;
                                                  check_reset <= 1'b1;
                                                end
              end
            endcase
    end
 
         assign fifo_wr_en = receiving_d2;
 
         rxdatafifo rxdatain(.clk(rxclk),
                          .sinit(reset),
                          .din(rxd64_d3),
                                        .wr_en(fifo_wr_en),
                        .rd_en(fifo_rd_en),
                          .dout(rx_data_tmp),
                          .full(rxfifo_full),
                          .empty(rxfifo_empty));
 
         rxcntrlfifo rxcntrlin(.clk(rxclk),
                          .sinit(reset),
                          .din(rxc_fifo),
                                        .wr_en(fifo_wr_en),
                        .rd_en(fifo_rd_en),
                          .dout(rx_data_valid_tmp),
                          .full(),
                          .empty());
 
         reg fifo_rd_en_d1;
         always@(posedge rxclk) begin
              fifo_rd_en_d1 <=#TP fifo_rd_en;
         end
 
         reg [63:0] rx_data;
         always@(posedge rxclk or posedge reset) begin
              if (reset)
            rx_data <= 0;
         else
            rx_data <=#TP rx_data_tmp;
    end
 
         reg [7:0] rx_data_valid;
         always@(posedge rxclk or posedge reset) begin
              if (reset)
                          rx_data_valid <=#TP 0;
                        else
           rx_data_valid <=#TP rx_data_valid_tmp;
    end
 
endmodule

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[/] [ethmac10g/] [tags/] [V10/] [rtl/] [verilog/] [rx_engine/] [rxDataPath.v] - Blame information for rev 72

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MODULE NAME: Data Path of Receive Module ////`
4			`//// ////`
5			`//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit ////`
6			`//// Ethernet MAC. Used to recognize every field of a ////`
7			`//// frame, including SOF, EOF, Length, Destination Addr ////`
8			`//// , Source Addr and Data field. ////`
9			`//// ////`
10			`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
11			`//// http://www.opencores.org/projects/ethmac10g/ ////`
12			`//// ////`
13			`//// AUTHOR(S): ////`
14			`//// Zheng Cao ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS REVISION HISTORY:`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
47			`//`
48			`//`
49			`//`
50			`//////////////////////////////////////////////////////////////////////`
51
52			`include "timescale.v"
53			`include "xgiga_define.v"
54
55			`module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,`
56			`get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,`
57			`rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);`
58			`// fcTxPauseData);`
59			`input rxclk;`
60			`input reset;`
61			`input [63:0] rxd64;`
62			`input [7:0] rxc8;`
63			`input inband_fcs;`
64			`input receiving;`
65			`input start_da;`
66			`input start_lt;`
67			`input wait_crc_check;`
68			`input get_terminator_d1;`
69			`input bad_frame_get;`
70			`input good_frame_get;`
71
72			`output get_sfd;`
73			`output get_terminator; //get T indicator`
74			`output get_error_code; //get Error indicator`
75			`output tagged_frame;`
76			`output pause_frame;`
77			`output[47:0] da_addr;`
78			`output[2:0] terminator_location;`
79			`output[63:0] CRC_DATA;`
80			`output[7:0] rx_data_valid;`
81			`output[63:0] rx_data;`
82			`output check_reset;`
83			`output rx_good_frame;`
84			`output rx_bad_frame;`
85			`// output [31:0]fcTxPauseData;`
86
87			`parameter TP = 1;`
88			`parameter IDLE = 0, READ = 1, WAIT_TMP = 2, WAIT = 3;`
89
90			`//////////////////////////////////////////////`
91			`// Pipe Line Stage`
92			`//////////////////////////////////////////////`
93			`reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;`
94			`reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;`
95			`reg receiving_d1, receiving_d2;`
96			`reg wait_crc_check_d1;`
97
98			`// assign fcTxPauseData = rxd64_d1[31:0];`
99			`// Data pipeline`
100			`always@(posedge rxclk or posedge reset) begin`
101			`if (reset) begin`
102			`rxd64_d1<=#TP 0;`
103			`rxd64_d2<=#TP 0;`
104			`rxd64_d3<=#TP 0;`
105			`CRC_DATA<=0;`
106
107			`end`
108			`else begin`
109			`rxd64_d1<=#TP rxd64;`
110			`rxd64_d2<=#TP rxd64_d1;`
111			`rxd64_d3<=#TP rxd64_d2;`
112			`CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],`
113			`rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],`
114			`rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],`
115			`rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],`
116			`rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],`
117			`rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],`
118			`rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],`
119			`rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};`
120			`end`
121			`end`
122			`//control pipeline`
123			`always@(posedge rxclk or posedge reset)begin`
124			`if (reset) begin`
125			`rxc8_d1<=#TP 0;`
126			`rxc8_d2<=#TP 0;`
127			`rxc8_d3<=#TP 0;`
128			`end`
129			`else begin`
130			`rxc8_d1<=#TP rxc8;`
131			`rxc8_d2<=#TP rxc8_d1;`
132			`rxc8_d3<=#TP rxc8_d2;`
133			`end`
134			`end`
135
136			`always @(posedge rxclk or posedge reset)begin`
137			`if (reset) begin`
138			`receiving_d1 <=#TP 0;`
139			`receiving_d2 <=#TP 0;`
140			`wait_crc_check_d1 <=#TP 0;`
141			`end`
142			`else begin`
143			`receiving_d1 <=#TP receiving;`
144			`receiving_d2 <=#TP receiving_d1;`
145			`wait_crc_check_d1 <=#TP wait_crc_check;`
146			`end`
147			`end`
148
149			`////////////////////////////////////////////`
150			`// Frame analysis`
151			`////////////////////////////////////////////`
152			`reg get_sfd; //get sfd indicator`
153			`reg get_terminator; //get T indicator`
154			`reg get_error_code; //get Error indicator`
155			`reg[7:0] get_e_chk;`
156			`reg[7:0] rxc_end_data; //seperate DATA with FCS`
157			`reg [2:0]terminator_location; //for n*8bits(n<8), get n`
158			`reg[47:0] da_addr; //get Desetination Address`
159			`reg tagged_frame; //Tagged frame indicator(type interpret)`
160			`reg pause_frame; //Pause frame indicator(type interpret)`
161
162			`//1. SFD`
163			`always@(posedge rxclk or posedge reset) begin`
164			`if (reset)`
165			`get_sfd <=#TP 0;`
166			`else`
167			get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
168			`end`
169
170			`//2. EFD`
171			`reg this_cycle;`
172			`// -----------------------------------------------`
173			`//\| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \|`
174			`// -----------------------------------------------`
175			`//\|<-------- EFD -------->\|<-------- EFD -------->\|`
176			`//\|<-- this_cycle = '1' ->\|<-- this_cycle = '0' ->\|`
177
178			`always@(posedge rxclk or posedge reset) begin`
179			`if (reset) begin`
180			`get_terminator <=#TP 0;`
181			`terminator_location <=#TP 0;`
182			`this_cycle <=#TP 1'b0;`
183			`rxc_end_data <=#TP 0;`
184			`end`
185			`else begin`
186			if (rxc8[0] & (rxd64[7:0] ==`TERMINATE)) begin
187			`get_terminator <=#TP 1'b1;`
188			`terminator_location <=#TP 0;`
189			`this_cycle <=#TP 1'b1;`
190			`rxc_end_data <=#TP 8'b00001111;`
191			`end`
192			else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
193			`get_terminator <=#TP 1'b1;`
194			`terminator_location <=#TP 1;`
195			`this_cycle <=#TP 1'b1;`
196			`rxc_end_data <=#TP 8'b00011111;`
197			`end`
198			else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
199			`get_terminator <=#TP 1'b1;`
200			`terminator_location <=#TP 2;`
201			`this_cycle <=#TP 1'b1;`
202			`rxc_end_data <=#TP 8'b00111111;`
203			`end`
204			else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
205			`get_terminator <=#TP 1'b1;`
206			`terminator_location <=#TP 3;`
207			`this_cycle <=#TP 1'b1;`
208			`rxc_end_data <=#TP 8'b01111111;`
209			`end`
210			else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
211			`get_terminator <=#TP 1'b1;`
212			`terminator_location <=#TP 4;`
213			`this_cycle <=#TP 1'b1;`
214			`rxc_end_data <=#TP 8'b11111111;`
215			`end`
216			else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
217			`get_terminator <=#TP 1'b1;`
218			`terminator_location <=#TP 5;`
219			`this_cycle <=#TP 1'b0;`
220			`rxc_end_data <=#TP 8'b00000001;`
221			`end`
222			else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
223			`get_terminator <=#TP 1'b1;`
224			`terminator_location <=#TP 6;`
225			`this_cycle <=#TP 1'b0;`
226			`rxc_end_data <=#TP 8'b00000011;`
227			`end`
228			else if (rxc8[7] & (rxd64[63:56]==`TERMINATE)) begin
229			`get_terminator <=#TP 1'b1;`
230			`terminator_location <=#TP 7;`
231			`this_cycle <=#TP 1'b0;`
232			`rxc_end_data <=#TP 8'b00000111;`
233			`end`
234			`else begin`
235			`get_terminator <=#TP 1'b0;`
236			`terminator_location <=#TP terminator_location;`
237			`this_cycle <=#TP this_cycle;`
238			`rxc_end_data <=#TP rxc_end_data;`
239			`end`
240			`end`
241			`end`
242
243			`//3. Error Character`
244			`always@(posedge rxclk or posedge reset) begin`
245			`if (reset)`
246			`get_e_chk <=#TP 0;`
247			`else begin`
248			get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0] ==`ERROR);
249			get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
250			get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
251			get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
252			get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
253			get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
254			get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
255			get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
256			`end`
257			`end`
258
259			`always@(posedge rxclk or posedge reset) begin`
260			`if (reset)`
261			`get_error_code <=#TP 0;`
262			`else`
263			`get_error_code <=#TP receiving & (\| get_e_chk);`
264			`end`
265
266			`//////////////////////////////////////`
267			`// Get Destination Address`
268			`//////////////////////////////////////`
269
270			`always@(posedge rxclk or posedge reset)begin`
271			`if (reset)`
272			`da_addr <=#TP 0;`
273			`else if (start_da)`
274			`da_addr <=#TP rxd64_d1[47:0];`
275			`else`
276			`da_addr <=#TP da_addr;`
277			`end`
278
279			`//////////////////////////////////////`
280			`// Get Length/Type Field`
281			`//////////////////////////////////////`
282
283			`// reg[15:0] lt_data;`
284			`// always@(posedge rxclk or posedge reset)begin`
285			`// if (reset)`
286			`// lt_data <=#TP 0;`
287			`// else if (start_lt)`
288			`// lt_data <=#TP rxd64_d1[47:32];`
289			`// else`
290			`// lt_data <=#TP lt_data;`
291			`// end`
292
293			`//tagged frame indicator`
294			`always@(posedge rxclk or posedge reset) begin`
295			`if (reset)`
296			`tagged_frame <=#TP 1'b0;`
297			`else if (start_lt)`
298			tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
299			`else`
300			`tagged_frame <=#TP tagged_frame;`
301			`end`
302			`//pause frame indicator`
303			`always@(posedge rxclk or posedge reset) begin`
304			`if (reset)`
305			`pause_frame <=#TP 1'b0;`
306			`else if (start_lt)`
307			pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
308			`else`
309			`pause_frame <=#TP 1'b0;`
310			`end`
311
312			`/////////////////////////////////////////////`
313			`// Generate proper rxc to FIFO`
314			`/////////////////////////////////////////////`
315
316			`reg [7:0]rxc_final;`
317			`wire [7:0]rxc_fifo; //rxc send to fifo`
318
319			`always@(posedge rxclk or posedge reset) begin`
320			`if (reset)`
321			`rxc_final <=#TP 0;`
322			`else if (get_terminator & this_cycle)`
323			`rxc_final <=#TP rxc_end_data;`
324			`else if (get_terminator_d1 & ~this_cycle)`
325			`rxc_final <=#TP rxc_end_data;`
326			`else if (receiving)`
327			rxc_final <=`ALLONES8;
328			`else`
329			`rxc_final <=0;`
330			`end`
331
332			`assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;`
333
334			`////////////////////////////////////////////////////////////////`
335			`// FIFO management, to generate rx_good_frame/rx_bad_frame`
336			`// after a frame has been totally received.`
337			`////////////////////////////////////////////////////////////////`
338			`wire rxfifo_full;`
339			`wire rxfifo_empty;`
340			`wire fifo_wr_en;`
341			`wire [63:0] rx_data_tmp;`
342			`wire [7:0] rx_data_valid_tmp;`
343
344			`reg one_frame_end;`
345			`always@(posedge rxclk or posedge reset) begin`
346			`if(reset)`
347			`one_frame_end <= 1'b0;`
348			`else if(rx_data_valid_tmp!=8'hff)`
349			`one_frame_end <= 1'b1;`
350			`else`
351			`one_frame_end <= 1'b0;`
352			`end`
353
354			`reg fifo_rd_en;`
355			`reg[1:0] fifo_state;`
356			`reg rx_good_frame;`
357			`reg rx_bad_frame;`
358			`reg check_reset;`
359			`always@(posedge rxclk or posedge reset) begin`
360			`if(reset) begin`
361			`fifo_rd_en <= 1'b0;`
362			`fifo_state <= IDLE;`
363			`rx_good_frame <= 1'b0;`
364			`rx_bad_frame <= 1'b0;`
365			`check_reset <= 1'b0;`
366			`end`
367			`else`
368			`case (fifo_state)`
369			`IDLE: begin`
370			`rx_good_frame <= 1'b0;`
371			`rx_bad_frame <= 1'b0;`
372			`check_reset <= 1'b0;`
373			`fifo_state <= IDLE;`
374			`fifo_rd_en <= 1'b0;`
375			`if(~rxfifo_empty) begin`
376			`fifo_rd_en <= 1'b1;`
377			`fifo_state <= READ;`
378			`end`
379			`end`
380			`READ: begin`
381			`check_reset <= 1'b0;`
382			`fifo_rd_en <= 1'b1;`
383			`rx_good_frame <= 1'b0;`
384			`rx_bad_frame <= 1'b0;`
385			`fifo_state <= READ;`
386			`if(rx_data_valid_tmp!=8'hff)`
387			`fifo_state <= WAIT_TMP;`
388			`end`
389			`WAIT_TMP: begin`
390			`if(rx_data_valid_tmp!=8'hff)`
391			`fifo_state <= WAIT;`
392			`end`
393			`WAIT: begin`
394			`rx_good_frame <= 1'b0;`
395			`rx_bad_frame <= 1'b0;`
396			`fifo_state <= WAIT;`
397			`check_reset <= 1'b0;`
398			`fifo_rd_en <= 1'b0;`
399			`if(bad_frame_get \| good_frame_get)begin`
400			`rx_good_frame <= good_frame_get;`
401			`rx_bad_frame <= bad_frame_get;`
402			`fifo_state <= IDLE;`
403			`check_reset <= 1'b1;`
404			`end`
405			`end`
406			`endcase`
407			`end`
408
409			`assign fifo_wr_en = receiving_d2;`
410
411			`rxdatafifo rxdatain(.clk(rxclk),`
412			`.sinit(reset),`
413			`.din(rxd64_d3),`
414			`.wr_en(fifo_wr_en),`
415			`.rd_en(fifo_rd_en),`
416			`.dout(rx_data_tmp),`
417			`.full(rxfifo_full),`
418			`.empty(rxfifo_empty));`
419
420			`rxcntrlfifo rxcntrlin(.clk(rxclk),`
421			`.sinit(reset),`
422			`.din(rxc_fifo),`
423			`.wr_en(fifo_wr_en),`
424			`.rd_en(fifo_rd_en),`
425			`.dout(rx_data_valid_tmp),`
426			`.full(),`
427			`.empty());`
428
429			`reg fifo_rd_en_d1;`
430			`always@(posedge rxclk) begin`
431			`fifo_rd_en_d1 <=#TP fifo_rd_en;`
432			`end`
433
434			`reg [63:0] rx_data;`
435			`always@(posedge rxclk or posedge reset) begin`
436			`if (reset)`
437			`rx_data <= 0;`
438			`else`
439			`rx_data <=#TP rx_data_tmp;`
440			`end`
441
442			`reg [7:0] rx_data_valid;`
443			`always@(posedge rxclk or posedge reset) begin`
444			`if (reset)`
445			`rx_data_valid <=#TP 0;`
446			`else`
447			`rx_data_valid <=#TP rx_data_valid_tmp;`
448			`end`
449
450			`endmodule`