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//////////////////////////////////////////////////////////////////////
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//// ////
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//// MODULE NAME: rxRSLayer ////
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//// ////
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//// DESCRIPTION: Reconciliation SubLayer of 10 Gigabit Ethernet. ////
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//// ////
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//// ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// ////
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//// AUTHOR(S): ////
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//// Zheng Cao ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS REVISION HISTORY:
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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//
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//
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//
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "xgiga_define.v"
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module rxRSLayer(rxclk, rxclk_180, reset, link_fault, rxd64, rxc8, rxd_in, rxc_in);
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input rxclk;
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input rxclk_180;
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input reset;
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input [31:0] rxd_in;
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input [3:0] rxc_in;
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output [1:0] link_fault;
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output [63:0] rxd64;
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output [7:0] rxc8;
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wire local_fault;
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wire remote_fault;
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wire[1:0] link_fault;
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rxRSIO datapath(.rxclk(rxclk),
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.rxclk_180(rxclk_180),
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.reset(reset),
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.rxd_in(rxd_in),
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.rxc_in(rxc_in),
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.rxd64(rxd64),
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.rxc8(rxc8),
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.local_fault(local_fault),
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.remote_fault(remote_fault)
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);
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rxLinkFaultState statemachine(.rxclk(rxclk_180),
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.reset(reset),
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.local_fault(local_fault),
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.remote_fault(remote_fault),
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.link_fault(link_fault)
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);
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endmodule
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