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fisher5090 |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// MODULE NAME: rxNumCounter ////
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//// ////
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//// DESCRIPTION: To count bytes have been received. ////
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//// ////
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//// ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// ////
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//// AUTHOR(S): ////
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//// Zheng Cao ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS REVISION HISTORY:
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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//
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//
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//
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "xgiga_define.v"
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module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, length_error, crc_check_valid, crc_check_invalid,
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start_da, start_lt, receiving, receiving_d1, good_frame_get, bad_frame_get, get_error_code, wait_crc_check,
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get_terminator,check_reset);
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input rxclk;
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input reset;
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input recv_enable;
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//PRE & SFD
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input get_sfd; // SFD has been received;
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//DA field
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input local_invalid;// The Frame's DA field is not Local MAC;
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//Length/Type field
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input length_error;//
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//FCS field
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input get_terminator;//Indicate end of receiving FCS field;
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input crc_check_valid;//Indicate the frame passed CRC Check;
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input crc_check_invalid;//Indicate the frame failed in CRC Check;
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input get_error_code;
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input check_reset;
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//DA field
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output start_da;// Start to receive Destination Address;
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//Length/Type field
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output start_lt;// Start to receive Length/Type field;
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//Receive process control
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output receiving; //Rx Engine is working, not in IDLE state and Check state.
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output receiving_d1;
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output good_frame_get;// A good frame has been received;
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output bad_frame_get; // A bad frame has been received;
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output wait_crc_check;//
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parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 4;
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parameter rxGetError = 8, rxIFGWait = 16;
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parameter TP =1;
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wire start_da;
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wire start_lt;
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wire receiving;
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reg good_frame_get;
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reg bad_frame_get;
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reg[4:0] rxstate, rxstate_next;
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always@(rxstate, get_sfd, local_invalid, recv_enable,
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get_error_code, length_error, get_terminator, reset)begin
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if (reset) begin
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rxstate_next <=#TP IDLE;
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end
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else begin
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case (rxstate)
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IDLE: begin //5'b00000;
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if (get_sfd && recv_enable)
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rxstate_next <=#TP rxReceiveDA;
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else
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rxstate_next <=#TP IDLE;
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end
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rxReceiveDA: begin //5'b00001
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rxstate_next <=#TP rxReceiveLT;
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end
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rxReceiveLT: begin //5'b00010
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rxstate_next <=#TP rxReceiveData;
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end
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rxReceiveData: begin //5'b00100
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if (local_invalid |length_error| get_error_code)
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rxstate_next <=#TP rxGetError;
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else if (get_terminator)
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rxstate_next <=#TP rxIFGWait;
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else
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rxstate_next <=#TP rxReceiveData;
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end
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rxGetError: begin //5'b01000
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if (get_sfd && recv_enable)
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rxstate_next <=#TP rxReceiveDA;
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else
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rxstate_next <=#TP IDLE;
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end
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rxIFGWait : begin //5'b10000;
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if (get_sfd && recv_enable)
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rxstate_next <=#TP rxReceiveDA;
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else
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rxstate_next <=#TP IDLE;
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end
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endcase
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end
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end
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always@(posedge rxclk or posedge reset) begin
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if (reset)
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rxstate <=#TP IDLE;
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else
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rxstate <=#TP rxstate_next;
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end
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assign start_da = rxstate[0];
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assign start_lt = rxstate[1];
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assign receiving = rxstate[2] | rxstate[1] | rxstate[0]; // in DA,LT,DATA status
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reg receiving_d1;
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always@(posedge rxclk or posedge reset) begin
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if (reset) begin
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receiving_d1<=#TP 0;
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end
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else begin
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receiving_d1<=#TP receiving;
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end
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end
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reg wait_crc_check;
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always@(posedge rxclk or posedge reset) begin
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if (reset)
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wait_crc_check <=#TP 0;
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else if (rxstate[4])
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wait_crc_check <=#TP 1'b1;
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else if (crc_check_valid || crc_check_invalid||length_error)
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wait_crc_check <=#TP 1'b0;
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else
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wait_crc_check <=#TP wait_crc_check;
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end
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always@(posedge rxclk or posedge reset)begin
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if (reset) begin
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bad_frame_get <=#TP 0;
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good_frame_get <=#TP 0;
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end
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else if(rxstate[3] || crc_check_invalid || length_error)begin
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bad_frame_get <=#TP 1'b1;
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good_frame_get <=#TP 1'b0;
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end
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else if (crc_check_valid)begin
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good_frame_get <=#TP 1'b1;
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bad_frame_get <=#TP 1'b0;
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end
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else if (check_reset)begin
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good_frame_get <=#TP 1'b0;
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bad_frame_get <=#TP 1'b0;
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end
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end
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endmodule
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