Subversion Repositories ethmac10g

# BEGIN Project Options

SET flowvendor = Foundation_iSE

SET vhdlsim = True

SET verilogsim = True

SET workingdirectory = F:\10G\ethmac10g

SET speedgrade = -6

SET simulationfiles = Behavioral

SET asysymbol = True

SET addpads = False

# SET outputdirectory = F:\10G\ethmac10g

SET device = xc2vp20

# SET projectname = F:\10G\ethmac10g

SET implementationfiletype = Edif

SET busformat = BusFormatAngleBracketNotRipped

SET foundationsym = False

SET package = fg676

SET createndf = False

SET designentry = VHDL

SET devicefamily = virtex2p

SET formalverification = False

SET removerpms = False

# END Project Options

# BEGIN Select

SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0

# END Select

# BEGIN Parameters

CSET memory_type=Block_Memory

CSET write_acknowledge_flag=false

CSET data_width=8

CSET write_error_flag=false

CSET read_acknowledge_sense=Active_Low

CSET data_count_width=1

CSET fifo_depth=128

CSET component_name=rxcntrlfifo

CSET data_count=false

CSET read_acknowledge_flag=false

CSET read_error_sense=Active_Low

CSET read_error_flag=false

CSET write_acknowledge_sense=Active_Low

CSET write_error_sense=Active_Low

# END Parameters

GENERATE