1 |
4 |
fisher5090 |
`timescale 1ns / 1ps
|
2 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
3 |
|
|
// Company:
|
4 |
|
|
// Engineer:
|
5 |
|
|
//
|
6 |
|
|
// Create Date: 19:45:58 12/13/05
|
7 |
|
|
// Design Name:
|
8 |
|
|
// Module Name: rxFrameDepart
|
9 |
|
|
// Project Name:
|
10 |
|
|
// Target Device:
|
11 |
|
|
// Tool versions:
|
12 |
|
|
// Description:
|
13 |
|
|
//
|
14 |
|
|
// Dependencies:
|
15 |
|
|
//
|
16 |
|
|
// Revision:
|
17 |
|
|
// Revision 0.01 - File Created
|
18 |
|
|
// Additional Comments:
|
19 |
|
|
//
|
20 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
21 |
|
|
|
22 |
|
|
`define START 8'hfb
|
23 |
|
|
`define TERMINATE 8'hfd
|
24 |
|
|
`define SFD 8'b10101011
|
25 |
|
|
`define SEQUENCE 8'h9c
|
26 |
|
|
`define ERROR 8'hfe
|
27 |
|
|
`define ALLONES 8'hff
|
28 |
|
|
`define ALLZEROS 8'h00
|
29 |
|
|
|
30 |
|
|
module rxFrameDepart(rxclk, reset, rxclk_180, rxd64, rxc8, start_da, start_lt, tagged_frame,
|
31 |
|
|
bits_more, small_bits_more, tagged_len, small_frame, end_data_cnt,inband_fcs,
|
32 |
|
|
end_small_cnt, da_addr, lt_data, crc_code, end_fcs, crc_valid, length_error,
|
33 |
|
|
get_sfd, get_efd, get_error_code,receiving, rxc_fifo, receiving_frame);
|
34 |
|
|
input rxclk;
|
35 |
|
|
input reset;
|
36 |
|
|
input rxclk_180;
|
37 |
|
|
input [63:0] rxd64;
|
38 |
|
|
input [7:0] rxc8;
|
39 |
|
|
|
40 |
|
|
input start_da;
|
41 |
|
|
input start_lt;
|
42 |
|
|
input tagged_frame;
|
43 |
|
|
input [2:0] bits_more;
|
44 |
|
|
input [2:0] small_bits_more;
|
45 |
|
|
input small_frame;
|
46 |
|
|
input end_data_cnt;
|
47 |
|
|
input end_small_cnt;
|
48 |
|
|
input inband_fcs;
|
49 |
|
|
input receiving;
|
50 |
|
|
input receiving_frame;
|
51 |
|
|
|
52 |
|
|
output[7:0] rxc_fifo;
|
53 |
|
|
output[47:0] da_addr; //destination address won't be changed until start_da was changed again
|
54 |
|
|
output[15:0] lt_data; //(Length/Type) field won't be changed until start_lt was changed again
|
55 |
|
|
output[15:0] tagged_len;
|
56 |
|
|
output[31:0] crc_code;
|
57 |
|
|
output end_fcs;
|
58 |
|
|
output[7:0] crc_valid;
|
59 |
|
|
output length_error;
|
60 |
|
|
|
61 |
|
|
output get_sfd;
|
62 |
|
|
output get_efd;
|
63 |
|
|
output get_error_code;
|
64 |
|
|
|
65 |
|
|
parameter TP = 1;
|
66 |
|
|
|
67 |
|
|
//////////////////////////////////////////
|
68 |
|
|
// Get Control Characters
|
69 |
|
|
//////////////////////////////////////////
|
70 |
|
|
wire get_sfd;
|
71 |
|
|
wire[7:0] get_t_chk;
|
72 |
|
|
wire get_efd;
|
73 |
|
|
wire get_error_code;
|
74 |
|
|
wire[7:0] get_e_chk;
|
75 |
|
|
|
76 |
|
|
//1. SFD
|
77 |
|
|
assign get_sfd = ~(rxd64[63:56] ^ `START) & ~(rxd64[7:0] ^ `SFD) & ~(rxc8 ^ 8'h80);
|
78 |
|
|
|
79 |
|
|
//2. EFD
|
80 |
|
|
assign get_t_chk[0] = rxc8[0] & (rxd64[7:0] ~^ `TERMINATE );
|
81 |
|
|
assign get_t_chk[1] = rxc8[1] & (rxd64[15:8] ~^ `TERMINATE );
|
82 |
|
|
assign get_t_chk[2] = rxc8[2] & (rxd64[23:16] ~^ `TERMINATE );
|
83 |
|
|
assign get_t_chk[3] = rxc8[3] & (rxd64[31:24] ~^ `TERMINATE );
|
84 |
|
|
assign get_t_chk[4] = rxc8[4] & (rxd64[39:32] ~^ `TERMINATE );
|
85 |
|
|
assign get_t_chk[5] = rxc8[5] & (rxd64[47:40] ~^ `TERMINATE );
|
86 |
|
|
assign get_t_chk[6] = rxc8[6] & (rxd64[55:48] ~^ `TERMINATE );
|
87 |
|
|
assign get_t_chk[7] = rxc8[7] & (rxd64[63:56] ~^ `TERMINATE );
|
88 |
|
|
assign get_efd = | get_t_chk;
|
89 |
|
|
|
90 |
|
|
//3. Error Character
|
91 |
|
|
assign get_e_chk[0] = rxc8[0] & (rxd64[7:0] ^`TERMINATE);
|
92 |
|
|
assign get_e_chk[1] = rxc8[1] & (rxd64[15:8] ^`TERMINATE);
|
93 |
|
|
assign get_e_chk[2] = rxc8[2] & (rxd64[23:16]^`TERMINATE);
|
94 |
|
|
assign get_e_chk[3] = rxc8[3] & (rxd64[31:24]^`TERMINATE);
|
95 |
|
|
assign get_e_chk[4] = rxc8[4] & (rxd64[39:32]^`TERMINATE);
|
96 |
|
|
assign get_e_chk[5] = rxc8[5] & (rxd64[47:40]^`TERMINATE);
|
97 |
|
|
assign get_e_chk[6] = rxc8[6] & (rxd64[55:48]^`TERMINATE);
|
98 |
|
|
assign get_e_chk[7] = rxc8[7] & (rxd64[63:56]^`TERMINATE);
|
99 |
|
|
assign get_error_code = | get_e_chk;
|
100 |
|
|
|
101 |
|
|
//////////////////////////////////////
|
102 |
|
|
// Get Destination Address
|
103 |
|
|
//////////////////////////////////////
|
104 |
|
|
|
105 |
|
|
reg[47:0] da_addr;
|
106 |
|
|
always@(posedge rxclk_180 or posedge reset)begin
|
107 |
|
|
if (reset)
|
108 |
|
|
da_addr <=#TP 0;
|
109 |
|
|
else if (start_da)
|
110 |
|
|
da_addr <=#TP rxd64[63:16];
|
111 |
|
|
else
|
112 |
|
|
da_addr <=#TP da_addr;
|
113 |
|
|
end
|
114 |
|
|
|
115 |
|
|
//////////////////////////////////////
|
116 |
|
|
// Get Length/Type Field
|
117 |
|
|
//////////////////////////////////////
|
118 |
|
|
|
119 |
|
|
reg[15:0] lt_data;
|
120 |
|
|
always@(posedge rxclk_180 or posedge reset)begin
|
121 |
|
|
if (reset)
|
122 |
|
|
lt_data <=#TP 0;
|
123 |
|
|
else if (start_lt)
|
124 |
|
|
lt_data <=#TP rxd64[31:16];
|
125 |
|
|
else if(~receiving_frame)
|
126 |
|
|
lt_data <=#TP 16'h0500;
|
127 |
|
|
else
|
128 |
|
|
lt_data <=#TP lt_data;
|
129 |
|
|
end
|
130 |
|
|
|
131 |
|
|
///////////////////////////////////////
|
132 |
|
|
// Get Tagged Frame Length
|
133 |
|
|
///////////////////////////////////////
|
134 |
|
|
|
135 |
|
|
reg tagged_frame_d1;
|
136 |
|
|
always@(posedge rxclk_180) begin
|
137 |
|
|
tagged_frame_d1<=#TP tagged_frame;
|
138 |
|
|
end
|
139 |
|
|
|
140 |
|
|
reg[15:0] tagged_len;
|
141 |
|
|
always@(posedge rxclk_180 or posedge reset) begin
|
142 |
|
|
if (reset)
|
143 |
|
|
tagged_len <=#TP 0;
|
144 |
|
|
else if(~tagged_frame_d1 & tagged_frame)
|
145 |
|
|
tagged_len <=#TP rxd64[63:48];
|
146 |
|
|
else if(~receiving_frame)
|
147 |
|
|
tagged_len <=#TP 16'h0500;
|
148 |
|
|
else
|
149 |
|
|
tagged_len <=#TP tagged_len;
|
150 |
|
|
end
|
151 |
|
|
|
152 |
|
|
////////////////////////////////////////
|
153 |
|
|
// Get FCS Field and Part of DATA
|
154 |
|
|
////////////////////////////////////////
|
155 |
|
|
|
156 |
|
|
wire [7:0]special;
|
157 |
|
|
|
158 |
|
|
wire[31:0] crc_code;
|
159 |
|
|
wire end_fcs;
|
160 |
|
|
wire[7:0] crc_valid;
|
161 |
|
|
wire length_error;
|
162 |
|
|
wire[7:0] tmp_crc_data[31:0];
|
163 |
|
|
wire[31:0] crc_code_tmp1;
|
164 |
|
|
wire[31:0] crc_code_tmp;
|
165 |
|
|
wire[4:0] shift_tmp;
|
166 |
|
|
wire next_cycle;
|
167 |
|
|
reg end_data_cnt_d1;
|
168 |
|
|
|
169 |
|
|
always@(posedge rxclk or posedge reset) begin
|
170 |
|
|
if (reset)
|
171 |
|
|
end_data_cnt_d1<= #TP 0;
|
172 |
|
|
else
|
173 |
|
|
end_data_cnt_d1<= #TP end_data_cnt;
|
174 |
|
|
end
|
175 |
|
|
|
176 |
|
|
reg[31:0] crc_code_tmp_d1;
|
177 |
|
|
always@(posedge rxclk or posedge reset) begin
|
178 |
|
|
if (reset)
|
179 |
|
|
crc_code_tmp_d1<= #TP 0;
|
180 |
|
|
else
|
181 |
|
|
crc_code_tmp_d1 <=#TP crc_code_tmp;
|
182 |
|
|
end
|
183 |
|
|
|
184 |
|
|
assign shift_tmp = (8-bits_more)<<3;
|
185 |
|
|
assign special = `ALLONES >> bits_more;
|
186 |
|
|
assign crc_code_tmp1 = rxd64[63:32] >> shift_tmp;
|
187 |
|
|
assign next_cycle = bits_more[2]&(bits_more[1] | bits_more[0]);
|
188 |
|
|
assign crc_valid = end_data_cnt? ~special: `ALLONES;
|
189 |
|
|
assign end_fcs = end_data_cnt_d1;
|
190 |
|
|
//timing constraint should be added here to make length_error be valid earlier than end_fcs
|
191 |
|
|
assign length_error = (end_data_cnt &(((bits_more == 0) & ~get_t_chk[3]) |
|
192 |
|
|
((bits_more == 1) & ~get_t_chk[2]) |
|
193 |
|
|
((bits_more == 2) & ~get_t_chk[1]) |
|
194 |
|
|
((bits_more == 3) & ~get_t_chk[0])))|
|
195 |
|
|
(end_data_cnt_d1 &(((bits_more == 4) & ~get_t_chk[7]) |
|
196 |
|
|
((bits_more == 5) & ~get_t_chk[6]) |
|
197 |
|
|
((bits_more == 6) & ~get_t_chk[5]) |
|
198 |
|
|
((bits_more == 7) & ~get_t_chk[4])));
|
199 |
|
|
|
200 |
|
|
assign tmp_crc_data[31] = {rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39],rxd64[47],rxd64[55],rxd64[63]};
|
201 |
|
|
assign tmp_crc_data[30] = {rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38],rxd64[46],rxd64[54],rxd64[62]};
|
202 |
|
|
assign tmp_crc_data[29] = {rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37],rxd64[45],rxd64[53],rxd64[61]};
|
203 |
|
|
assign tmp_crc_data[28] = {rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36],rxd64[44],rxd64[52],rxd64[60]};
|
204 |
|
|
assign tmp_crc_data[27] = {rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35],rxd64[43],rxd64[51],rxd64[59]};
|
205 |
|
|
assign tmp_crc_data[26] = {rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34],rxd64[42],rxd64[50],rxd64[58]};
|
206 |
|
|
assign tmp_crc_data[25] = {rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33],rxd64[41],rxd64[49],rxd64[57]};
|
207 |
|
|
assign tmp_crc_data[24] = {rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32],rxd64[40],rxd64[48],rxd64[56]};
|
208 |
|
|
assign tmp_crc_data[23] = {1'b0,rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39],rxd64[47],rxd64[55]};
|
209 |
|
|
assign tmp_crc_data[22] = {1'b0,rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38],rxd64[46],rxd64[54]};
|
210 |
|
|
assign tmp_crc_data[21] = {1'b0,rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37],rxd64[45],rxd64[53]};
|
211 |
|
|
assign tmp_crc_data[20] = {1'b0,rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36],rxd64[44],rxd64[52]};
|
212 |
|
|
assign tmp_crc_data[19] = {1'b0,rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35],rxd64[43],rxd64[51]};
|
213 |
|
|
assign tmp_crc_data[18] = {1'b0,rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34],rxd64[42],rxd64[50]};
|
214 |
|
|
assign tmp_crc_data[17] = {1'b0,rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33],rxd64[41],rxd64[49]};
|
215 |
|
|
assign tmp_crc_data[16] = {1'b0,rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32],rxd64[40],rxd64[48]};
|
216 |
|
|
assign tmp_crc_data[15] = {1'b0,1'b0,rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39],rxd64[47]};
|
217 |
|
|
assign tmp_crc_data[14] = {1'b0,1'b0,rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38],rxd64[46]};
|
218 |
|
|
assign tmp_crc_data[13] = {1'b0,1'b0,rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37],rxd64[45]};
|
219 |
|
|
assign tmp_crc_data[12] = {1'b0,1'b0,rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36],rxd64[44]};
|
220 |
|
|
assign tmp_crc_data[11] = {1'b0,1'b0,rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35],rxd64[43]};
|
221 |
|
|
assign tmp_crc_data[10] = {1'b0,1'b0,rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34],rxd64[42]};
|
222 |
|
|
assign tmp_crc_data[9] = {1'b0,1'b0,rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33],rxd64[41]};
|
223 |
|
|
assign tmp_crc_data[8] = {1'b0,1'b0,rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32],rxd64[40]};
|
224 |
|
|
assign tmp_crc_data[7] = {1'b0,1'b0,1'b0,rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39]};
|
225 |
|
|
assign tmp_crc_data[6] = {1'b0,1'b0,1'b0,rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38]};
|
226 |
|
|
assign tmp_crc_data[5] = {1'b0,1'b0,1'b0,rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37]};
|
227 |
|
|
assign tmp_crc_data[4] = {1'b0,1'b0,1'b0,rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36]};
|
228 |
|
|
assign tmp_crc_data[3] = {1'b0,1'b0,1'b0,rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35]};
|
229 |
|
|
assign tmp_crc_data[2] = {1'b0,1'b0,1'b0,rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34]};
|
230 |
|
|
assign tmp_crc_data[1] = {1'b0,1'b0,1'b0,rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33]};
|
231 |
|
|
assign tmp_crc_data[0] = {1'b0,1'b0,1'b0,rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32]};
|
232 |
|
|
|
233 |
|
|
M8_1E crc31(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[31]), .O(crc_code_tmp[31]));
|
234 |
|
|
M8_1E crc30(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[30]), .O(crc_code_tmp[30]));
|
235 |
|
|
M8_1E crc29(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[29]), .O(crc_code_tmp[29]));
|
236 |
|
|
M8_1E crc28(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[28]), .O(crc_code_tmp[28]));
|
237 |
|
|
M8_1E crc27(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[27]), .O(crc_code_tmp[27]));
|
238 |
|
|
M8_1E crc26(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[26]), .O(crc_code_tmp[26]));
|
239 |
|
|
M8_1E crc25(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[25]), .O(crc_code_tmp[25]));
|
240 |
|
|
M8_1E crc24(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[24]), .O(crc_code_tmp[24]));
|
241 |
|
|
M8_1E crc23(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[23]), .O(crc_code_tmp[23]));
|
242 |
|
|
M8_1E crc22(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[22]), .O(crc_code_tmp[22]));
|
243 |
|
|
M8_1E crc21(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[21]), .O(crc_code_tmp[21]));
|
244 |
|
|
M8_1E crc20(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[20]), .O(crc_code_tmp[20]));
|
245 |
|
|
M8_1E crc19(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[19]), .O(crc_code_tmp[19]));
|
246 |
|
|
M8_1E crc18(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[18]), .O(crc_code_tmp[18]));
|
247 |
|
|
M8_1E crc17(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[17]), .O(crc_code_tmp[17]));
|
248 |
|
|
M8_1E crc16(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[16]), .O(crc_code_tmp[16]));
|
249 |
|
|
M8_1E crc15(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[15]), .O(crc_code_tmp[15]));
|
250 |
|
|
M8_1E crc14(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[14]), .O(crc_code_tmp[14]));
|
251 |
|
|
M8_1E crc13(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[13]), .O(crc_code_tmp[13]));
|
252 |
|
|
M8_1E crc12(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[12]), .O(crc_code_tmp[12]));
|
253 |
|
|
M8_1E crc11(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[11]), .O(crc_code_tmp[11]));
|
254 |
|
|
M8_1E crc10(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[10]), .O(crc_code_tmp[10]));
|
255 |
|
|
M8_1E crc9(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[9]), .O(crc_code_tmp[9]));
|
256 |
|
|
M8_1E crc8(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[8]), .O(crc_code_tmp[8]));
|
257 |
|
|
M8_1E crc7(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[7]), .O(crc_code_tmp[7]));
|
258 |
|
|
M8_1E crc6(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[6]), .O(crc_code_tmp[6]));
|
259 |
|
|
M8_1E crc5(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[5]), .O(crc_code_tmp[5]));
|
260 |
|
|
M8_1E crc4(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[4]), .O(crc_code_tmp[4]));
|
261 |
|
|
M8_1E crc3(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[3]), .O(crc_code_tmp[3]));
|
262 |
|
|
M8_1E crc2(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[2]), .O(crc_code_tmp[2]));
|
263 |
|
|
M8_1E crc1(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[1]), .O(crc_code_tmp[1]));
|
264 |
|
|
M8_1E crc0(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[0]), .O(crc_code_tmp[0]));
|
265 |
|
|
|
266 |
|
|
assign crc_code =next_cycle ? (crc_code_tmp_d1 | crc_code_tmp1): crc_code_tmp;
|
267 |
|
|
|
268 |
|
|
/////////////////////////////////////////////////////////////////////////////////
|
269 |
|
|
// Generate proper rxc to FIFO //
|
270 |
|
|
/////////////////////////////////////////////////////////////////////////////////
|
271 |
|
|
|
272 |
|
|
// FCS is provided by client, inband_fcs is valid
|
273 |
|
|
// receiving end_data_cnt end_fcs
|
274 |
|
|
// frame: |<------ Data ------>|<-- bits_more -->|<-- FCS -->|<--------
|
275 |
|
|
// rxc : |<------------------- all_one -------------------->|<--------all_zero
|
276 |
|
|
// |<--- 8bits, with 1s & 0s --->|
|
277 |
|
|
|
278 |
|
|
// FCS is provided by logic, inband_fcs is invalid
|
279 |
|
|
// receiving end_data_cnt end_fcs
|
280 |
|
|
// frame: |<------ Data ------>|<-- bits_more -->|<-- FCS -->|
|
281 |
|
|
// rxc : |<-------------- all_one ------------->|<----- all_zero
|
282 |
|
|
// |<-- 8bits, with 1s & 0s --->|
|
283 |
|
|
|
284 |
|
|
// receiving end_small_cnt end_fcs
|
285 |
|
|
// frame: |<------ Data ------>|<-- small_bits_more -->|<-- PAD -->|<-- FCS -->|
|
286 |
|
|
// rxc : |<----------------- all_one ---------------->|<----- all_zero
|
287 |
|
|
// |<-------- 1s --------->|<----- 0s
|
288 |
|
|
wire [7:0]rxc_pad;
|
289 |
|
|
wire [7:0]rxc_end_data;
|
290 |
|
|
wire [7:0]rxc_fcs;
|
291 |
|
|
wire [7:0]rxc_final[2:0];
|
292 |
|
|
wire [7:0]rxc_fifo; //rxc send to fifo
|
293 |
|
|
|
294 |
|
|
assign rxc_pad = ~(`ALLONES >> small_bits_more);
|
295 |
|
|
assign rxc_end_data = ~special;
|
296 |
|
|
assign rxc_fcs =~(bits_more[2]?(`ALLONES >> {1'b0,bits_more[1:0]}) : (`ALLONES >> {1'b1,bits_more[1:0]}));
|
297 |
|
|
|
298 |
|
|
assign rxc_final[0] = receiving? (((end_data_cnt & ~next_cycle) | (end_data_cnt_d1 & next_cycle))? rxc_fcs: `ALLONES): `ALLZEROS;
|
299 |
|
|
assign rxc_final[1] = receiving? (end_data_cnt? rxc_end_data: `ALLONES): `ALLZEROS;
|
300 |
|
|
assign rxc_final[2] = receiving? (end_small_cnt?rxc_pad: `ALLONES): `ALLZEROS;
|
301 |
|
|
assign rxc_fifo = inband_fcs? rxc_final[0]: (small_frame? rxc_final[2]: rxc_final[1]);
|
302 |
|
|
|
303 |
|
|
endmodule
|