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[/] [ethmac10g/] [tags/] [V10/] [rxLinkFaultState.v] - Blame information for rev 72

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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    17:11:43 12/19/05
// Design Name:    
// Module Name:    rxLinkFaultState
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module rxLinkFaultState(rxclk_2x, reset, local_fault, remote_fault, link_fault);
    input rxclk_2x;
    input reset;
    input local_fault;
    input remote_fault;
    output[1:0] link_fault;
 
         parameter TP =1;
         parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;
 
         //------------------------------------------------
         // Link        Fault Signalling Statemachine
         //------------------------------------------------
         wire  fault_type;
         wire  get_one_fault;
         wire  no_new_type;
 
         reg[2:0] linkstate;
         reg[7:0] col_cnt;
         reg[1:0] seq_cnt;
         reg[1:0] seq_type;
         reg[1:0] last_seq_type;
         reg[1:0] link_fault;
         reg      reset_col_cnt;
 
         assign fault_type = {local_fault, remote_fault};
         assign get_one_fault = local_fault | remote_fault;
         assign no_new_type = (seq_type == last_seq_type);
         assign col_cnt_128 = (col_cnt == 127);
 
         always@(posedge rxclk_2x or posedge reset)begin
             if (reset) begin
                           seq_type <=#TP 0;
                                seq_cnt <=#TP 0;
                                last_seq_type <=#TP 0;
                                reset_col_cnt<= #TP 1;
                                link_fault <=#TP 2'b00;
                                linkstate<= #TP IDLE;
                  end
                  else begin
                           seq_type <= #TP fault_type;
                           last_seq_type <=#TP seq_type;
                           case (linkstate)
                              IDLE: begin
                                             linkstate <=#TP IDLE;
                                             reset_col_cnt <= #TP 1;
                                                  seq_cnt <= #TP 0;
                                                  link_fault <= #TP 2'b00;
                                             if (get_one_fault)
                                                                linkstate<=#TP LinkFaultDetect;
                                        end
 
                   LinkFaultDetect: begin
                                             linkstate <=#TP LinkFaultDetect;
                                                  reset_col_cnt <=#TP 1;
                                             if (get_one_fault & no_new_type)
                                                     if (seq_cnt < 3)
                                                        seq_cnt <=#TP seq_cnt + 1;
                                                          else linkstate <=#TP GetFault;
                                                  else if(~get_one_fault)
                                                       if(col_cnt_128) begin
                                                                    linkstate <=#TP IDLE;
                                                                         reset_col_cnt <=#TP 1;
                                                                 end
                                                                 else reset_col_cnt <=#TP 0;
                                                  else if(get_one_fault & ~no_new_type)
                                                        linkstate <=#TP NewFaultType;
                                        end
 
                NewFaultType: begin
                                  seq_cnt <=#TP 0;
                                                  linkstate <=#TP LinkFaultDetect;
                                                  reset_col_cnt<=#TP 1;
                end
 
                                        GetFault: begin
                                                  linkstate <=#TP GetFault;
                                                  reset_col_cnt <=#TP 1;
                    if (get_one_fault & no_new_type)
                                                                link_fault <=#TP seq_type;
                                        else if (~get_one_fault)        begin
                                                         reset_col_cnt<=#TP 0;
                                                                        if(col_cnt_128)
                                                                linkstate <=#TP IDLE;
                                                  end
                    else if (get_one_fault &    ~no_new_type)
                                                      linkstate <=#TP NewFaultType;
                                        end
                           endcase
            end
         end
 
         always@(posedge rxclk_2x or posedge reset) begin
                    if (reset)
                            col_cnt <=#TP 0;
          else if (reset_col_cnt)
                            col_cnt <=#TP 0;
          else
                            col_cnt <=#TP col_cnt + 1;
    end
 
endmodule

Line No.	Rev	Author	Line
1	4	fisher5090	`timescale 1ns / 1ps
2			`////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 17:11:43 12/19/05`
7			`// Design Name:`
8			`// Module Name: rxLinkFaultState`
9			`// Project Name:`
10			`// Target Device:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`////////////////////////////////////////////////////////////////////////////////`
21			`module rxLinkFaultState(rxclk_2x, reset, local_fault, remote_fault, link_fault);`
22			`input rxclk_2x;`
23			`input reset;`
24			`input local_fault;`
25			`input remote_fault;`
26			`output[1:0] link_fault;`
27
28			`parameter TP =1;`
29			`parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;`
30
31			`//------------------------------------------------`
32			`// Link Fault Signalling Statemachine`
33			`//------------------------------------------------`
34			`wire fault_type;`
35			`wire get_one_fault;`
36			`wire no_new_type;`
37
38			`reg[2:0] linkstate;`
39			`reg[7:0] col_cnt;`
40			`reg[1:0] seq_cnt;`
41			`reg[1:0] seq_type;`
42			`reg[1:0] last_seq_type;`
43			`reg[1:0] link_fault;`
44			`reg reset_col_cnt;`
45
46			`assign fault_type = {local_fault, remote_fault};`
47			`assign get_one_fault = local_fault \| remote_fault;`
48			`assign no_new_type = (seq_type == last_seq_type);`
49			`assign col_cnt_128 = (col_cnt == 127);`
50
51			`always@(posedge rxclk_2x or posedge reset)begin`
52			`if (reset) begin`
53			`seq_type <=#TP 0;`
54			`seq_cnt <=#TP 0;`
55			`last_seq_type <=#TP 0;`
56			`reset_col_cnt<= #TP 1;`
57			`link_fault <=#TP 2'b00;`
58			`linkstate<= #TP IDLE;`
59			`end`
60			`else begin`
61			`seq_type <= #TP fault_type;`
62			`last_seq_type <=#TP seq_type;`
63			`case (linkstate)`
64			`IDLE: begin`
65			`linkstate <=#TP IDLE;`
66			`reset_col_cnt <= #TP 1;`
67			`seq_cnt <= #TP 0;`
68			`link_fault <= #TP 2'b00;`
69			`if (get_one_fault)`
70			`linkstate<=#TP LinkFaultDetect;`
71			`end`
72
73			`LinkFaultDetect: begin`
74			`linkstate <=#TP LinkFaultDetect;`
75			`reset_col_cnt <=#TP 1;`
76			`if (get_one_fault & no_new_type)`
77			`if (seq_cnt < 3)`
78			`seq_cnt <=#TP seq_cnt + 1;`
79			`else linkstate <=#TP GetFault;`
80			`else if(~get_one_fault)`
81			`if(col_cnt_128) begin`
82			`linkstate <=#TP IDLE;`
83			`reset_col_cnt <=#TP 1;`
84			`end`
85			`else reset_col_cnt <=#TP 0;`
86			`else if(get_one_fault & ~no_new_type)`
87			`linkstate <=#TP NewFaultType;`
88			`end`
89
90			`NewFaultType: begin`
91			`seq_cnt <=#TP 0;`
92			`linkstate <=#TP LinkFaultDetect;`
93			`reset_col_cnt<=#TP 1;`
94			`end`
95
96			`GetFault: begin`
97			`linkstate <=#TP GetFault;`
98			`reset_col_cnt <=#TP 1;`
99			`if (get_one_fault & no_new_type)`
100			`link_fault <=#TP seq_type;`
101			`else if (~get_one_fault) begin`
102			`reset_col_cnt<=#TP 0;`
103			`if(col_cnt_128)`
104			`linkstate <=#TP IDLE;`
105			`end`
106			`else if (get_one_fault & ~no_new_type)`
107			`linkstate <=#TP NewFaultType;`
108			`end`
109			`endcase`
110			`end`
111			`end`
112
113			`always@(posedge rxclk_2x or posedge reset) begin`
114			`if (reset)`
115			`col_cnt <=#TP 0;`
116			`else if (reset_col_cnt)`
117			`col_cnt <=#TP 0;`
118			`else`
119			`col_cnt <=#TP col_cnt + 1;`
120			`end`
121
122			`endmodule`

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[/] [ethmac10g/] [tags/] [V10/] [rxLinkFaultState.v] - Blame information for rev 72