OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [tags/] [V10/] [rxRSIO.v] - Blame information for rev 40

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 fisher5090 
`timescale 1ns / 1ps
2 
////////////////////////////////////////////////////////////////////////////////
3 
// Company:
4 
// Engineer:
5 
//
6 
// Create Date:    09:22:59 12/22/05
7 
// Design Name:
8 
// Module Name:    rxRSIO
9 
// Project Name:
10 
// Target Device:
11 
// Tool versions:
12 
// Description:
13 
//
14 
// Dependencies:
15 
//
16 
// Revision:
17 
// Revision 0.01 - File Created
18 
// Additional Comments:
19 
//
20 
////////////////////////////////////////////////////////////////////////////////
21 
`define START  8'hdf
22 
`define PREAMBLE 8'h55
23 
`define SEQUENCE 8'h59
24 
 
25 
module rxRSIO(rxclk_2x, reset, rxd, rxc, rxd64, rxc8, local_fault, remote_fault);
26 
    input rxclk_2x;
27 
         input reset;
28 
    input [0:31] rxd;
29 
    input [0:3] rxc;
30 
    output [63:0] rxd64;
31 
    output [7:0] rxc8;
32 
         output local_fault;
33 
         output remote_fault;
34 
 
35 
         parameter TP =1;
36 
 
37 
         wire local_fault, remote_fault;
38 
         wire get_align, get_seq;
39 
 
40 
         assign get_align = ((rxd[0:7]==`START) & rxc[0]) & ((rxd[8:15]==`PREAMBLE) & ~rxc[1]);
41 
    assign get_seq = (rxd[0:7] == `SEQUENCE) & (rxd[8:29] == 0) & (rxc[0:3]== 4'h8) & rxd[31];
42 
    assign local_fault = get_seq & ~rxd[30];
43 
    assign remote_fault = get_seq & rxd[30];
44 
 
45 
         reg ddr_read_en;
46 
         always@(posedge rxclk_2x or posedge reset) begin
47 
               if (reset)
48 
                            ddr_read_en<=#TP 0;
49 
                         else if (get_align)
50 
                            ddr_read_en <=#TP 0;
51 
                         else
52 
                            ddr_read_en<=#TP ~ddr_read_en;
53 
         end
54 
 
55 
//rxd ddr io registers
56 
FDCE rxd64_0 (.Q(rxd64[0]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[7]));    defparam rxd64_0.INIT = 1'b0;
57 
FDCE rxd64_1 (.Q(rxd64[1]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[6]));     defparam rxd64_1.INIT = 1'b0;
58 
FDCE rxd64_2 (.Q(rxd64[2]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[5]));          defparam rxd64_2.INIT = 1'b0;
59 
FDCE rxd64_3 (.Q(rxd64[3]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[4]));          defparam rxd64_3.INIT = 1'b0;
60 
FDCE rxd64_4 (.Q(rxd64[4]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[3]));          defparam rxd64_4.INIT = 1'b0;
61 
FDCE rxd64_5 (.Q(rxd64[5]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[2]));          defparam rxd64_5.INIT = 1'b0;
62 
FDCE rxd64_6 (.Q(rxd64[6]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[1]));          defparam rxd64_6.INIT = 1'b0;
63 
FDCE rxd64_7 (.Q(rxd64[7]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[0]));           defparam rxd64_7.INIT = 1'b0;
64 
FDCE rxd64_8 (.Q(rxd64[8]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[15])); defparam rxd64_8.INIT = 1'b0;
65 
FDCE rxd64_9 (.Q(rxd64[9]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[14])); defparam rxd64_9.INIT = 1'b0;
66 
FDCE rxd64_10 (.Q(rxd64[10]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[13]));       defparam rxd64_10.INIT = 1'b0;
67 
FDCE rxd64_11 (.Q(rxd64[11]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[12]));       defparam rxd64_11.INIT = 1'b0;
68 
FDCE rxd64_12 (.Q(rxd64[12]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[11]));       defparam rxd64_12.INIT = 1'b0;
69 
FDCE rxd64_13 (.Q(rxd64[13]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[10]));       defparam rxd64_13.INIT = 1'b0;
70 
FDCE rxd64_14 (.Q(rxd64[14]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[9]));        defparam rxd64_14.INIT = 1'b0;
71 
FDCE rxd64_15 (.Q(rxd64[15]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[8]));        defparam rxd64_15.INIT = 1'b0;
72 
FDCE rxd64_16 (.Q(rxd64[16]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[23]));       defparam rxd64_16.INIT = 1'b0;
73 
FDCE rxd64_17 (.Q(rxd64[17]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[22]));       defparam rxd64_17.INIT = 1'b0;
74 
FDCE rxd64_18 (.Q(rxd64[18]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[21]));       defparam rxd64_18.INIT = 1'b0;
75 
FDCE rxd64_19 (.Q(rxd64[19]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[20]));       defparam rxd64_19.INIT = 1'b0;
76 
FDCE rxd64_20 (.Q(rxd64[20]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[19]));       defparam rxd64_20.INIT = 1'b0;
77 
FDCE rxd64_21 (.Q(rxd64[21]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[18]));       defparam rxd64_21.INIT = 1'b0;
78 
FDCE rxd64_22 (.Q(rxd64[22]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[17]));       defparam rxd64_22.INIT = 1'b0;
79 
FDCE rxd64_23 (.Q(rxd64[23]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[16]));       defparam rxd64_23.INIT = 1'b0;
80 
FDCE rxd64_24 (.Q(rxd64[24]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[31]));       defparam rxd64_24.INIT = 1'b0;
81 
FDCE rxd64_25 (.Q(rxd64[25]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[30]));       defparam rxd64_25.INIT = 1'b0;
82 
FDCE rxd64_26 (.Q(rxd64[26]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[29]));       defparam rxd64_26.INIT = 1'b0;
83 
FDCE rxd64_27 (.Q(rxd64[27]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[28]));       defparam rxd64_27.INIT = 1'b0;
84 
FDCE rxd64_28 (.Q(rxd64[28]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[27]));       defparam rxd64_28.INIT = 1'b0;
85 
FDCE rxd64_29 (.Q(rxd64[29]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[26]));       defparam rxd64_29.INIT = 1'b0;
86 
FDCE rxd64_30 (.Q(rxd64[30]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[25]));       defparam rxd64_30.INIT = 1'b0;
87 
FDCE rxd64_31 (.Q(rxd64[31]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[24]));       defparam rxd64_31.INIT = 1'b0;
88 
FDCE rxd64_32 (.Q(rxd64[32]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[7])); defparam rxd64_32.INIT = 1'b0;
89 
FDCE rxd64_33 (.Q(rxd64[33]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[6])); defparam rxd64_33.INIT = 1'b0;
90 
FDCE rxd64_34 (.Q(rxd64[34]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[5])); defparam rxd64_34.INIT = 1'b0;
91 
FDCE rxd64_35 (.Q(rxd64[35]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[4])); defparam rxd64_35.INIT = 1'b0;
92 
FDCE rxd64_36 (.Q(rxd64[36]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[3])); defparam rxd64_36.INIT = 1'b0;
93 
FDCE rxd64_37 (.Q(rxd64[37]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[2])); defparam rxd64_37.INIT = 1'b0;
94 
FDCE rxd64_38 (.Q(rxd64[38]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[1])); defparam rxd64_38.INIT = 1'b0;
95 
FDCE rxd64_39 (.Q(rxd64[39]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[0]));  defparam rxd64_39.INIT = 1'b0;
96 
FDCE rxd64_40 (.Q(rxd64[40]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[15]));        defparam rxd64_40.INIT = 1'b0;
97 
FDCE rxd64_41 (.Q(rxd64[41]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[14]));        defparam rxd64_41.INIT = 1'b0;
98 
FDCE rxd64_42 (.Q(rxd64[42]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[13]));        defparam rxd64_42.INIT = 1'b0;
99 
FDCE rxd64_43 (.Q(rxd64[43]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[12]));        defparam rxd64_43.INIT = 1'b0;
100 
FDCE rxd64_44 (.Q(rxd64[44]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[11]));        defparam rxd64_44.INIT = 1'b0;
101 
FDCE rxd64_45 (.Q(rxd64[45]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[10]));        defparam rxd64_45.INIT = 1'b0;
102 
FDCE rxd64_46 (.Q(rxd64[46]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[9])); defparam rxd64_46.INIT = 1'b0;
103 
FDCE rxd64_47 (.Q(rxd64[47]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[8])); defparam rxd64_47.INIT = 1'b0;
104 
FDCE rxd64_48 (.Q(rxd64[48]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[23]));        defparam rxd64_48.INIT = 1'b0;
105 
FDCE rxd64_49 (.Q(rxd64[49]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[22]));        defparam rxd64_49.INIT = 1'b0;
106 
FDCE rxd64_50 (.Q(rxd64[50]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[21]));        defparam rxd64_50.INIT = 1'b0;
107 
FDCE rxd64_51 (.Q(rxd64[51]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[20]));        defparam rxd64_51.INIT = 1'b0;
108 
FDCE rxd64_52 (.Q(rxd64[52]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[19]));        defparam rxd64_52.INIT = 1'b0;
109 
FDCE rxd64_53 (.Q(rxd64[53]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[18]));        defparam rxd64_53.INIT = 1'b0;
110 
FDCE rxd64_54 (.Q(rxd64[54]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[17]));        defparam rxd64_54.INIT = 1'b0;
111 
FDCE rxd64_55 (.Q(rxd64[55]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[16]));        defparam rxd64_55.INIT = 1'b0;
112 
FDCE rxd64_56 (.Q(rxd64[56]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[31]));        defparam rxd64_56.INIT = 1'b0;
113 
FDCE rxd64_57 (.Q(rxd64[57]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[30]));        defparam rxd64_57.INIT = 1'b0;
114 
FDCE rxd64_58 (.Q(rxd64[58]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[29]));        defparam rxd64_58.INIT = 1'b0;
115 
FDCE rxd64_59 (.Q(rxd64[59]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[28]));        defparam rxd64_59.INIT = 1'b0;
116 
FDCE rxd64_60 (.Q(rxd64[60]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[27]));        defparam rxd64_60.INIT = 1'b0;
117 
FDCE rxd64_61 (.Q(rxd64[61]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[26]));        defparam rxd64_61.INIT = 1'b0;
118 
FDCE rxd64_62 (.Q(rxd64[62]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[25]));        defparam rxd64_62.INIT = 1'b0;
119 
FDCE rxd64_63 (.Q(rxd64[63]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[24]));        defparam rxd64_63.INIT = 1'b0;
120 
 
121 
//rxc ddr io registers
122 
FDCE rxc8_0 (.Q(rxc8[0]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[3]));      defparam rxc8_0.INIT = 1'b0;
123 
FDCE rxc8_1 (.Q(rxc8[1]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[2]));     defparam rxc8_1.INIT = 1'b0;
124 
FDCE rxc8_2 (.Q(rxc8[2]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[1]));     defparam rxc8_2.INIT = 1'b0;
125 
FDCE rxc8_3 (.Q(rxc8[3]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[0]));      defparam rxc8_3.INIT = 1'b0;
126 
FDCE rxc8_4 (.Q(rxc8[4]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[3]));              defparam rxc8_4.INIT = 1'b0;
127 
FDCE rxc8_5 (.Q(rxc8[5]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[2]));              defparam rxc8_5.INIT = 1'b0;
128 
FDCE rxc8_6 (.Q(rxc8[6]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[1]));              defparam rxc8_6.INIT = 1'b0;
129 
FDCE rxc8_7 (.Q(rxc8[7]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[0]));               defparam rxc8_7.INIT = 1'b0;
130 
 
131 
 
132 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.