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[/] [ethmac10g/] [tags/] [V10/] [rxcntrlfifo.v] - Blame information for rev 74

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/*******************************************************************************
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*     This file is owned and controlled by Xilinx and must be used             *
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*     solely for design, simulation, implementation and creation of            *
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*     design files limited to Xilinx devices or technologies. Use              *
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*     with non-Xilinx devices or technologies is expressly prohibited          *
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*     and immediately terminates your license.                                 *
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*                                                                              *
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*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
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*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
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*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
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*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
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*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
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*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
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*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
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*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
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*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
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*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
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*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
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*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
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*     FOR A PARTICULAR PURPOSE.                                                *
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*                                                                              *
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*     Xilinx products are not intended for use in life support                 *
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*     appliances, devices, or systems. Use in such applications are            *
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*     expressly prohibited.                                                    *
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*                                                                              *
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*     (c) Copyright 1995-2005 Xilinx, Inc.                                     *
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*     All rights reserved.                                                     *
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*******************************************************************************/
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// The synopsys directives "translate_off/translate_on" specified below are
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// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file rxcntrlfifo.v when simulating
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// the core, rxcntrlfifo. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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module rxcntrlfifo(
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        clk,
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        sinit,
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        din,
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        wr_en,
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        rd_en,
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        dout,
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        full,
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        empty);
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input clk;
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input sinit;
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input [7 : 0] din;
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input wr_en;
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input rd_en;
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output [7 : 0] dout;
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output full;
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output empty;
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// synopsys translate_off
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      SYNC_FIFO_V5_0 #(
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                1,      // c_dcount_width
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                0,       // c_enable_rlocs
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                0,       // c_has_dcount
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                0,       // c_has_rd_ack
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                0,       // c_has_rd_err
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                0,       // c_has_wr_ack
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                0,       // c_has_wr_err
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                1,      // c_memory_type
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                0,       // c_ports_differ
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                1,      // c_rd_ack_low
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                1,      // c_rd_err_low
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                8,      // c_read_data_width
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                2048,   // c_read_depth
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                8,      // c_write_data_width
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                2048,   // c_write_depth
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                1,      // c_wr_ack_low
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                1)      // c_wr_err_low
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        inst (
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                .CLK(clk),
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                .SINIT(sinit),
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                .DIN(din),
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                .WR_EN(wr_en),
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                .RD_EN(rd_en),
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                .DOUT(dout),
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                .FULL(full),
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                .EMPTY(empty),
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                .RD_ACK(),
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                .WR_ACK(),
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                .RD_ERR(),
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                .WR_ERR(),
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                .DATA_COUNT());
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// synopsys translate_on
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// FPGA Express black box declaration
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// synopsys attribute fpga_dont_touch "true"
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// synthesis attribute fpga_dont_touch of rxcntrlfifo is "true"
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// XST black box declaration
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// box_type "black_box"
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// synthesis attribute box_type of rxcntrlfifo is "black_box"
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endmodule
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