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/*-------------------------------------------------------------------------------
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fisher5090 |
-- $Revision: 1.5 $ $Date: 2008-04-10 00:44:36 $
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fisher5090 |
-- Title : Demo testbench
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-- Project : 10 Gigabit Ethernet MAC
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-------------------------------------------------------------------------------
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-- File : demo_tb.v
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-------------------------------------------------------------------------------
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-- Description: This testbench will exercise the ports of the MAC core to
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-- demonstrate the functionality.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2001 Xilinx Inc.
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-------------------------------------------------------------------------------
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--
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-- This testbench performs the following operations on the MAC core:
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-- - The clock divide register is set for MIIM operation. */
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/* - The clientXGMII port is wired as a loopback, so that transmitted frames
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-- are then injected into the receiver.
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-- - Four frames are pushed into the receiver. The first is a minimum
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-- length frame, the second is slightly longer, the third has an error
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-- asserted and the fourth is less than minimum length and is padded
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-- up to the minimum.
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-- - These frames are then looped back and sent out by the transmitter.
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-- */
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`timescale 1ps / 1ps
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module frame_typ;
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// This module abstracts the frame data for simpler manipulation
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reg [31:0] data [0:31];
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reg [ 3:0] ctrl [0:31];
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reg [31:0] crc;
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reg underrun;
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`define FRAME_TYP [32*32+32*4+32+1:1]
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reg `FRAME_TYP bits;
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function `FRAME_TYP tobits;
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input dummy;
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begin
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bits = {data[ 0], data[ 1], data[ 2], data[ 3], data[ 4],
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data[ 5], data[ 6], data[ 7], data[ 8], data[ 9],
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data[10], data[11], data[12], data[13], data[14],
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data[15], data[16], data[17], data[18], data[19],
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data[20], data[21], data[22], data[23], data[24],
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data[25], data[26], data[27], data[28], data[29],
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data[30], data[31], ctrl[ 0], ctrl[ 1], ctrl[ 2],
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ctrl[ 3], ctrl[ 4], ctrl[ 5], ctrl[ 6], ctrl[ 7],
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ctrl[ 8], ctrl[ 9], ctrl[10], ctrl[11], ctrl[12],
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ctrl[13], ctrl[14], ctrl[15], ctrl[16], ctrl[17],
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ctrl[18], ctrl[19], ctrl[20], ctrl[21], ctrl[22],
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ctrl[23], ctrl[24], ctrl[25], ctrl[26], ctrl[27],
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ctrl[28], ctrl[29], ctrl[30], ctrl[31], crc, underrun};
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tobits = bits;
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end
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endfunction // tobits
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task frombits;
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input `FRAME_TYP frame;
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begin
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bits = frame;
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{data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], data[ 5],
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data[ 6], data[ 7], data[ 8], data[ 9], data[10], data[11],
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data[12], data[13], data[14], data[15], data[16], data[17],
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data[18], data[19], data[20], data[21], data[22], data[23],
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data[24], data[25], data[26], data[27], data[28], data[29],
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data[30], data[31], ctrl[ 0], ctrl[ 1], ctrl[ 2], ctrl[ 3],
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ctrl[ 4], ctrl[ 5], ctrl[ 6], ctrl[ 7], ctrl[ 8], ctrl[ 9],
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ctrl[10], ctrl[11], ctrl[12], ctrl[13], ctrl[14], ctrl[15],
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ctrl[16], ctrl[17], ctrl[18], ctrl[19], ctrl[20], ctrl[21],
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ctrl[22], ctrl[23], ctrl[24], ctrl[25], ctrl[26], ctrl[27],
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ctrl[28], ctrl[29], ctrl[30], ctrl[31], crc, underrun} = bits;
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end
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endtask // frombits
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endmodule // frame_typ
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// Address of management configuration register
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`define CONFIG_MANAGEMENT 9'b101000000
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// Address of flow control configuration register
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`define CONFIG_FLOW_CTRL 9'b011000000
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// addresses of statistics registers
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`define STATS_TX_OK 9'b000100000
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`define STATS_TX_UNDERRUN 9'b000100011
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`define STATS_RX_OK 9'b000000000
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`define STATS_RX_FCS_ERR 9'b000000001
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`define MIN_FRAME_DATA_BYTES 60
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module testbench;
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// Frame data....
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frame_typ frame0();
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frame_typ frame1();
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frame_typ frame2();
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frame_typ frame3();
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frame_typ tx_stimulus_working_frame();
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frame_typ tx_monitor_working_frame();
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frame_typ rx_stimulus_working_frame();
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frame_typ rx_monitor_working_frame();
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// Store the frame data etc....
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initial
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begin
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// Frame 0...
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frame0.data[0] = 32'h04030201;
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frame0.data[1] = 32'h02020605;
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frame0.data[2] = 32'h06050403;
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frame0.data[3] = 32'h55AA2E00;
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frame0.data[4] = 32'hAA55AA55;
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frame0.data[5] = 32'h55AA55AA;
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frame0.data[6] = 32'hAA55AA55;
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frame0.data[7] = 32'h55AA55AA;
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frame0.data[8] = 32'hAA55AA55;
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frame0.data[9] = 32'h55AA55AA;
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frame0.data[10] = 32'hAA55AA55;
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frame0.data[11] = 32'h55AA55AA;
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frame0.data[12] = 32'hAA55AA55;
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frame0.data[13] = 32'h55AA55AA;
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frame0.data[14] = 32'hAA55AA55;
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frame0.data[15] = 32'h00000000;
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frame0.data[16] = 32'h00000000;
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frame0.data[17] = 32'h00000000;
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| 126 |
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frame0.data[18] = 32'h00000000;
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| 127 |
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frame0.data[19] = 32'h00000000;
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| 128 |
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frame0.data[20] = 32'h00000000;
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frame0.data[21] = 32'h00000000;
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frame0.data[22] = 32'h00000000;
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frame0.data[23] = 32'h00000000;
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frame0.data[24] = 32'h00000000;
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frame0.data[25] = 32'h00000000;
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frame0.data[26] = 32'h00000000;
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frame0.data[27] = 32'h00000000;
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frame0.data[28] = 32'h00000000;
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frame0.data[29] = 32'h00000000;
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frame0.data[30] = 32'h00000000;
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frame0.data[31] = 32'h00000000;
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frame0.ctrl[0] = 4'b1111;
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frame0.ctrl[1] = 4'b1111;
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frame0.ctrl[2] = 4'b1111;
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frame0.ctrl[3] = 4'b1111;
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frame0.ctrl[4] = 4'b1111;
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frame0.ctrl[5] = 4'b1111;
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frame0.ctrl[6] = 4'b1111;
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frame0.ctrl[7] = 4'b1111;
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frame0.ctrl[8] = 4'b1111;
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frame0.ctrl[9] = 4'b1111;
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| 150 |
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frame0.ctrl[10] = 4'b1111;
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| 151 |
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frame0.ctrl[11] = 4'b1111;
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| 152 |
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frame0.ctrl[12] = 4'b1111;
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| 153 |
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frame0.ctrl[13] = 4'b1111;
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frame0.ctrl[14] = 4'b1111;
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frame0.ctrl[15] = 4'b0000;
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| 156 |
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frame0.ctrl[16] = 4'b0000;
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| 157 |
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frame0.ctrl[17] = 4'b0000;
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| 158 |
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frame0.ctrl[18] = 4'b0000;
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| 159 |
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frame0.ctrl[19] = 4'b0000;
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| 160 |
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frame0.ctrl[20] = 4'b0000;
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frame0.ctrl[21] = 4'b0000;
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| 162 |
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frame0.ctrl[22] = 4'b0000;
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frame0.ctrl[23] = 4'b0000;
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frame0.ctrl[24] = 4'b0000;
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frame0.ctrl[25] = 4'b0000;
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frame0.ctrl[26] = 4'b0000;
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| 167 |
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frame0.ctrl[27] = 4'b0000;
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| 168 |
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frame0.ctrl[28] = 4'b0000;
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| 169 |
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frame0.ctrl[29] = 4'b0000;
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| 170 |
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frame0.ctrl[30] = 4'b0000;
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| 171 |
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frame0.ctrl[31] = 4'b0000;
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| 172 |
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| 173 |
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frame0.crc = 32'h0D4820F6;
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| 174 |
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| 175 |
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frame0.underrun = 1'b0;
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| 176 |
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| 177 |
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// Frame 1
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frame1.data[0] = 32'h03040506;
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frame1.data[1] = 32'h05060102;
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| 180 |
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frame1.data[2] = 32'h02020304;
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| 181 |
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frame1.data[3] = 32'hEE110080;
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| 182 |
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frame1.data[4] = 32'h11EE11EE;
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| 183 |
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frame1.data[5] = 32'hEE11EE11;
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| 184 |
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frame1.data[6] = 32'h11EE11EE;
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| 185 |
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frame1.data[7] = 32'hEE11EE11;
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| 186 |
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frame1.data[8] = 32'h11EE11EE;
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| 187 |
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frame1.data[9] = 32'hEE11EE11;
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| 188 |
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frame1.data[10] = 32'h11EE11EE;
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| 189 |
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frame1.data[11] = 32'hEE11EE11;
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| 190 |
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frame1.data[12] = 32'h11EE11EE;
|
| 191 |
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frame1.data[13] = 32'hEE11EE11;
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| 192 |
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frame1.data[14] = 32'h11EE11EE;
|
| 193 |
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frame1.data[15] = 32'hEE11EE11;
|
| 194 |
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frame1.data[16] = 32'h11EE11EE;
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| 195 |
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frame1.data[17] = 32'hEE11EE11;
|
| 196 |
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frame1.data[18] = 32'h11EE11EE;
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| 197 |
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frame1.data[19] = 32'hEE11EE11;
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| 198 |
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frame1.data[20] = 32'h11EE11EE;
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| 199 |
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frame1.data[21] = 32'h0000EE11;
|
| 200 |
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frame1.data[22] = 32'h00000000;
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| 201 |
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frame1.data[23] = 32'h00000000;
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| 202 |
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frame1.data[24] = 32'h00000000;
|
| 203 |
|
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frame1.data[25] = 32'h00000000;
|
| 204 |
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frame1.data[26] = 32'h00000000;
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| 205 |
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frame1.data[27] = 32'h00000000;
|
| 206 |
|
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frame1.data[28] = 32'h00000000;
|
| 207 |
|
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frame1.data[29] = 32'h00000000;
|
| 208 |
|
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frame1.data[30] = 32'h00000000;
|
| 209 |
|
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frame1.data[31] = 32'h00000000;
|
| 210 |
|
|
|
| 211 |
|
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frame1.ctrl[0] = 4'b1111;
|
| 212 |
|
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frame1.ctrl[1] = 4'b1111;
|
| 213 |
|
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frame1.ctrl[2] = 4'b1111;
|
| 214 |
|
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frame1.ctrl[3] = 4'b1111;
|
| 215 |
|
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frame1.ctrl[4] = 4'b1111;
|
| 216 |
|
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frame1.ctrl[5] = 4'b1111;
|
| 217 |
|
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frame1.ctrl[6] = 4'b1111;
|
| 218 |
|
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frame1.ctrl[7] = 4'b1111;
|
| 219 |
|
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frame1.ctrl[8] = 4'b1111;
|
| 220 |
|
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frame1.ctrl[9] = 4'b1111;
|
| 221 |
|
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frame1.ctrl[10] = 4'b1111;
|
| 222 |
|
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frame1.ctrl[11] = 4'b1111;
|
| 223 |
|
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frame1.ctrl[12] = 4'b1111;
|
| 224 |
|
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frame1.ctrl[13] = 4'b1111;
|
| 225 |
|
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frame1.ctrl[14] = 4'b1111;
|
| 226 |
|
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frame1.ctrl[15] = 4'b1111;
|
| 227 |
|
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frame1.ctrl[16] = 4'b1111;
|
| 228 |
|
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frame1.ctrl[17] = 4'b1111;
|
| 229 |
|
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frame1.ctrl[18] = 4'b1111;
|
| 230 |
|
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frame1.ctrl[19] = 4'b1111;
|
| 231 |
71 |
fisher5090 |
frame1.ctrl[20] = 4'b1111;
|
| 232 |
|
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frame1.ctrl[21] = 4'b0011;
|
| 233 |
55 |
fisher5090 |
frame1.ctrl[22] = 4'b0000;
|
| 234 |
|
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frame1.ctrl[23] = 4'b0000;
|
| 235 |
|
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frame1.ctrl[24] = 4'b0000;
|
| 236 |
|
|
frame1.ctrl[25] = 4'b0000;
|
| 237 |
|
|
frame1.ctrl[26] = 4'b0000;
|
| 238 |
|
|
frame1.ctrl[27] = 4'b0000;
|
| 239 |
|
|
frame1.ctrl[28] = 4'b0000;
|
| 240 |
|
|
frame1.ctrl[29] = 4'b0000;
|
| 241 |
|
|
frame1.ctrl[30] = 4'b0000;
|
| 242 |
|
|
frame1.ctrl[31] = 4'b0000;
|
| 243 |
|
|
|
| 244 |
|
|
frame1.crc = 32'hDE13388C;
|
| 245 |
|
|
|
| 246 |
|
|
frame1.underrun = 1'b0;
|
| 247 |
|
|
|
| 248 |
|
|
// Frame 2
|
| 249 |
|
|
frame2.data[0] = 32'h04030201;
|
| 250 |
|
|
frame2.data[1] = 32'h02020605;
|
| 251 |
|
|
frame2.data[2] = 32'h06050403;
|
| 252 |
|
|
frame2.data[3] = 32'h55AA2E80;
|
| 253 |
|
|
frame2.data[4] = 32'hAA55AA55;
|
| 254 |
|
|
frame2.data[5] = 32'h55AA55AA;
|
| 255 |
|
|
frame2.data[6] = 32'hAA55AA55;
|
| 256 |
|
|
frame2.data[7] = 32'h55AA55AA;
|
| 257 |
|
|
frame2.data[8] = 32'hAA55AA55;
|
| 258 |
|
|
frame2.data[9] = 32'h55AA55AA;
|
| 259 |
|
|
frame2.data[10] = 32'hAA55AA55;
|
| 260 |
|
|
frame2.data[11] = 32'h55AA55AA;
|
| 261 |
|
|
frame2.data[12] = 32'hAA55AA55;
|
| 262 |
|
|
frame2.data[13] = 32'h55AA55AA;
|
| 263 |
|
|
frame2.data[14] = 32'hAA55AA55;
|
| 264 |
|
|
frame2.data[15] = 32'h55AA55AA;
|
| 265 |
|
|
frame2.data[16] = 32'hAA55AA55;
|
| 266 |
|
|
frame2.data[17] = 32'h55AA55AA;
|
| 267 |
|
|
frame2.data[18] = 32'hAA55AA55;
|
| 268 |
|
|
frame2.data[19] = 32'h55AA55AA;
|
| 269 |
|
|
frame2.data[20] = 32'h00000000;
|
| 270 |
|
|
frame2.data[21] = 32'h00000000;
|
| 271 |
|
|
frame2.data[22] = 32'h00000000;
|
| 272 |
|
|
frame2.data[23] = 32'h00000000;
|
| 273 |
|
|
frame2.data[24] = 32'h00000000;
|
| 274 |
|
|
frame2.data[25] = 32'h00000000;
|
| 275 |
|
|
frame2.data[26] = 32'h00000000;
|
| 276 |
|
|
frame2.data[27] = 32'h00000000;
|
| 277 |
|
|
frame2.data[28] = 32'h00000000;
|
| 278 |
|
|
frame2.data[29] = 32'h00000000;
|
| 279 |
|
|
frame2.data[30] = 32'h00000000;
|
| 280 |
|
|
frame2.data[31] = 32'h00000000;
|
| 281 |
|
|
|
| 282 |
|
|
frame2.ctrl[0] = 4'b1111;
|
| 283 |
|
|
frame2.ctrl[1] = 4'b1111;
|
| 284 |
|
|
frame2.ctrl[2] = 4'b1111;
|
| 285 |
|
|
frame2.ctrl[3] = 4'b1111;
|
| 286 |
|
|
frame2.ctrl[4] = 4'b1111;
|
| 287 |
|
|
frame2.ctrl[5] = 4'b1111;
|
| 288 |
|
|
frame2.ctrl[6] = 4'b1111;
|
| 289 |
|
|
frame2.ctrl[7] = 4'b1111;
|
| 290 |
|
|
frame2.ctrl[8] = 4'b1111;
|
| 291 |
|
|
frame2.ctrl[9] = 4'b1111;
|
| 292 |
|
|
frame2.ctrl[10] = 4'b1111;
|
| 293 |
|
|
frame2.ctrl[11] = 4'b1111;
|
| 294 |
|
|
frame2.ctrl[12] = 4'b1111;
|
| 295 |
|
|
frame2.ctrl[13] = 4'b1111;
|
| 296 |
|
|
frame2.ctrl[14] = 4'b1111;
|
| 297 |
|
|
frame2.ctrl[15] = 4'b1111;
|
| 298 |
|
|
frame2.ctrl[16] = 4'b1111;
|
| 299 |
|
|
frame2.ctrl[17] = 4'b1111;
|
| 300 |
|
|
frame2.ctrl[18] = 4'b1111;
|
| 301 |
|
|
frame2.ctrl[19] = 4'b1111;
|
| 302 |
71 |
fisher5090 |
frame2.ctrl[20] = 4'b0000;
|
| 303 |
55 |
fisher5090 |
frame2.ctrl[21] = 4'b0000;
|
| 304 |
|
|
frame2.ctrl[22] = 4'b0000;
|
| 305 |
|
|
frame2.ctrl[23] = 4'b0000;
|
| 306 |
|
|
frame2.ctrl[24] = 4'b0000;
|
| 307 |
|
|
frame2.ctrl[25] = 4'b0000;
|
| 308 |
|
|
frame2.ctrl[26] = 4'b0000;
|
| 309 |
|
|
frame2.ctrl[27] = 4'b0000;
|
| 310 |
|
|
frame2.ctrl[28] = 4'b0000;
|
| 311 |
|
|
frame2.ctrl[29] = 4'b0000;
|
| 312 |
|
|
frame2.ctrl[30] = 4'b0000;
|
| 313 |
|
|
frame2.ctrl[31] = 4'b0000;
|
| 314 |
|
|
|
| 315 |
|
|
frame2.crc = 32'h20C6B69D;
|
| 316 |
|
|
|
| 317 |
|
|
frame2.underrun = 1'b1;
|
| 318 |
|
|
|
| 319 |
|
|
// Frame 3
|
| 320 |
|
|
frame3.data[0] = 32'h03040506;
|
| 321 |
|
|
frame3.data[1] = 32'h05060102;
|
| 322 |
|
|
frame3.data[2] = 32'h02020304;
|
| 323 |
|
|
frame3.data[3] = 32'hEE111500;
|
| 324 |
|
|
frame3.data[4] = 32'h11EE11EE;
|
| 325 |
|
|
frame3.data[5] = 32'hEE11EE11;
|
| 326 |
71 |
fisher5090 |
frame3.data[6] = 64'h11EE11EE;
|
| 327 |
55 |
fisher5090 |
frame3.data[7] = 32'hEE11EE11;
|
| 328 |
|
|
frame3.data[8] = 32'h00EE11EE;
|
| 329 |
|
|
frame3.data[9] = 32'h00000000;
|
| 330 |
|
|
frame3.data[10] = 32'h00000000;
|
| 331 |
|
|
frame3.data[11] = 32'h00000000;
|
| 332 |
|
|
frame3.data[12] = 32'h00000000;
|
| 333 |
|
|
frame3.data[13] = 32'h00000000;
|
| 334 |
|
|
frame3.data[14] = 32'h00000000;
|
| 335 |
|
|
frame3.data[15] = 32'h00000000;
|
| 336 |
|
|
frame3.data[16] = 32'h00000000;
|
| 337 |
|
|
frame3.data[17] = 32'h00000000;
|
| 338 |
|
|
frame3.data[18] = 32'h00000000;
|
| 339 |
|
|
frame3.data[19] = 32'h00000000;
|
| 340 |
|
|
frame3.data[20] = 32'h00000000;
|
| 341 |
|
|
frame3.data[21] = 32'h00000000;
|
| 342 |
|
|
frame3.data[22] = 32'h00000000;
|
| 343 |
|
|
frame3.data[23] = 32'h00000000;
|
| 344 |
|
|
frame3.data[24] = 32'h00000000;
|
| 345 |
|
|
frame3.data[25] = 32'h00000000;
|
| 346 |
|
|
frame3.data[26] = 32'h00000000;
|
| 347 |
|
|
frame3.data[27] = 32'h00000000;
|
| 348 |
|
|
frame3.data[28] = 32'h00000000;
|
| 349 |
|
|
frame3.data[29] = 32'h00000000;
|
| 350 |
|
|
frame3.data[30] = 32'h00000000;
|
| 351 |
|
|
frame3.data[31] = 32'h00000000;
|
| 352 |
|
|
|
| 353 |
|
|
frame3.ctrl[0] = 4'b1111;
|
| 354 |
|
|
frame3.ctrl[1] = 4'b1111;
|
| 355 |
|
|
frame3.ctrl[2] = 4'b1111;
|
| 356 |
|
|
frame3.ctrl[3] = 4'b1111;
|
| 357 |
|
|
frame3.ctrl[4] = 4'b1111;
|
| 358 |
|
|
frame3.ctrl[5] = 4'b1111;
|
| 359 |
|
|
frame3.ctrl[6] = 4'b1111;
|
| 360 |
|
|
frame3.ctrl[7] = 4'b1111;
|
| 361 |
|
|
frame3.ctrl[8] = 4'b0111;
|
| 362 |
|
|
frame3.ctrl[9] = 4'b0000;
|
| 363 |
|
|
frame3.ctrl[10] = 4'b0000;
|
| 364 |
|
|
frame3.ctrl[11] = 4'b0000;
|
| 365 |
|
|
frame3.ctrl[12] = 4'b0000;
|
| 366 |
|
|
frame3.ctrl[13] = 4'b0000;
|
| 367 |
|
|
frame3.ctrl[14] = 4'b0000;
|
| 368 |
|
|
frame3.ctrl[15] = 4'b0000;
|
| 369 |
|
|
frame3.ctrl[16] = 4'b0000;
|
| 370 |
|
|
frame3.ctrl[17] = 4'b0000;
|
| 371 |
|
|
frame3.ctrl[18] = 4'b0000;
|
| 372 |
|
|
frame3.ctrl[19] = 4'b0000;
|
| 373 |
|
|
frame3.ctrl[20] = 4'b0000;
|
| 374 |
|
|
frame3.ctrl[21] = 4'b0000;
|
| 375 |
|
|
frame3.ctrl[22] = 4'b0000;
|
| 376 |
|
|
frame3.ctrl[23] = 4'b0000;
|
| 377 |
|
|
frame3.ctrl[24] = 4'b0000;
|
| 378 |
|
|
frame3.ctrl[25] = 4'b0000;
|
| 379 |
|
|
frame3.ctrl[26] = 4'b0000;
|
| 380 |
|
|
frame3.ctrl[27] = 4'b0000;
|
| 381 |
|
|
frame3.ctrl[28] = 4'b0000;
|
| 382 |
|
|
frame3.ctrl[29] = 4'b0000;
|
| 383 |
|
|
frame3.ctrl[30] = 4'b0000;
|
| 384 |
|
|
frame3.ctrl[31] = 4'b0000;
|
| 385 |
|
|
|
| 386 |
|
|
frame3.crc = 32'h6B734A56;
|
| 387 |
|
|
|
| 388 |
|
|
frame3.underrun = 1'b0;
|
| 389 |
|
|
end // initial
|
| 390 |
|
|
|
| 391 |
|
|
// DUT signals
|
| 392 |
|
|
reg reset;
|
| 393 |
|
|
|
| 394 |
|
|
//Client transmitter signals
|
| 395 |
|
|
//client receiver signals
|
| 396 |
|
|
|
| 397 |
|
|
wire [63:0] rx_data;
|
| 398 |
|
|
wire [7:0] rx_data_valid;
|
| 399 |
|
|
wire rx_good_frame;
|
| 400 |
|
|
wire rx_bad_frame;
|
| 401 |
|
|
wire rx_clk;
|
| 402 |
71 |
fisher5090 |
reg rxclk_2x;
|
| 403 |
|
|
wire [28:0] rx_statistics_vector;
|
| 404 |
|
|
wire rx_statistics_valid;
|
| 405 |
55 |
fisher5090 |
reg xgmii_rx_clk;
|
| 406 |
|
|
reg [31:0] xgmii_rxd;
|
| 407 |
|
|
reg [3:0] xgmii_rxc;
|
| 408 |
|
|
|
| 409 |
71 |
fisher5090 |
reg rx_monitor_finished;
|
| 410 |
|
|
wire simulation_finished;
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
55 |
fisher5090 |
/*---------------------------------------------------------------------------
|
| 414 |
|
|
-- wire up Device Under Test
|
| 415 |
|
|
---------------------------------------------------------------------------*/
|
| 416 |
71 |
fisher5090 |
wire [64:0] configuration_vector;
|
| 417 |
|
|
rxReceiveEngine uut (
|
| 418 |
|
|
.xgmii_rxclk(xgmii_rx_clk),
|
| 419 |
|
|
.rxclk_2x(rxclk_2x),
|
| 420 |
55 |
fisher5090 |
.reset_in(reset),
|
| 421 |
|
|
.rxclk_out(rx_clk),
|
| 422 |
60 |
fisher5090 |
.xgmii_rxd(xgmii_rxd),
|
| 423 |
|
|
.xgmii_rxc(xgmii_rxc),
|
| 424 |
71 |
fisher5090 |
.rxStatRegPlus(),
|
| 425 |
55 |
fisher5090 |
.cfgRxRegData_in(configuration_vector),
|
| 426 |
|
|
.rx_data(rx_data),
|
| 427 |
|
|
.rx_data_valid(rx_data_valid),
|
| 428 |
|
|
.rx_good_frame(rx_good_frame),
|
| 429 |
|
|
.rx_bad_frame(rx_bad_frame),
|
| 430 |
71 |
fisher5090 |
.rxCfgofRS(),
|
| 431 |
|
|
.rxTxLinkFault()
|
| 432 |
55 |
fisher5090 |
// .fcTxPauseData(),
|
| 433 |
|
|
// .fcTxPauseValid()
|
| 434 |
|
|
);
|
| 435 |
|
|
|
| 436 |
58 |
fisher5090 |
assign configuration_vector = {1'b0, 64'h058b010203040506}; //fcs in-band invalid
|
| 437 |
|
|
//assign configuration_vector = {1'b0, 64'h058f010203040506}; // fcs in-band valid
|
| 438 |
55 |
fisher5090 |
/*---------------------------------------------------------------------------
|
| 439 |
|
|
-- Clock drivers
|
| 440 |
|
|
---------------------------------------------------------------------------*/
|
| 441 |
|
|
initial
|
| 442 |
|
|
begin
|
| 443 |
71 |
fisher5090 |
xgmii_rx_clk <= 1;
|
| 444 |
55 |
fisher5090 |
#1000;
|
| 445 |
|
|
forever
|
| 446 |
|
|
begin
|
| 447 |
|
|
#3200;
|
| 448 |
71 |
fisher5090 |
xgmii_rx_clk <= 0;
|
| 449 |
|
|
#3200;
|
| 450 |
55 |
fisher5090 |
xgmii_rx_clk <= 1;
|
| 451 |
|
|
end
|
| 452 |
|
|
end // initial begin
|
| 453 |
71 |
fisher5090 |
|
| 454 |
|
|
initial
|
| 455 |
|
|
begin
|
| 456 |
|
|
rxclk_2x <= 1;
|
| 457 |
|
|
#1000;
|
| 458 |
|
|
forever
|
| 459 |
|
|
begin
|
| 460 |
|
|
#1600;
|
| 461 |
|
|
rxclk_2x <= 0;
|
| 462 |
|
|
#1600;
|
| 463 |
|
|
rxclk_2x <= 1;
|
| 464 |
|
|
end
|
| 465 |
|
|
end // initial begin
|
| 466 |
55 |
fisher5090 |
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
/* RX Stimulus process - insert frames into the PHY side of the
|
| 471 |
|
|
* receiver
|
| 472 |
|
|
*/
|
| 473 |
|
|
|
| 474 |
|
|
task rx_stimulus_send_column;
|
| 475 |
|
|
input [31:0] d;
|
| 476 |
|
|
input [ 3:0] c;
|
| 477 |
|
|
begin
|
| 478 |
|
|
@(posedge xgmii_rx_clk or negedge xgmii_rx_clk);
|
| 479 |
|
|
#1600;
|
| 480 |
|
|
xgmii_rxd <= d;
|
| 481 |
|
|
xgmii_rxc <= c;
|
| 482 |
|
|
end
|
| 483 |
|
|
endtask // rx_stimulus_send_column
|
| 484 |
|
|
|
| 485 |
|
|
task rx_stimulus_send_idle;
|
| 486 |
|
|
begin
|
| 487 |
|
|
rx_stimulus_send_column(32'h07070707,4'b1111);
|
| 488 |
|
|
end
|
| 489 |
|
|
endtask // rx_stimulus_send_idle
|
| 490 |
|
|
|
| 491 |
|
|
task rx_stimulus_send_frame;
|
| 492 |
|
|
input `FRAME_TYP frame;
|
| 493 |
|
|
integer column_index, lane_index, byte_count, I, J;
|
| 494 |
|
|
reg [31:0] scratch_column_data, current_column_data;
|
| 495 |
|
|
reg [ 3:0] scratch_column_ctrl, current_column_ctrl;
|
| 496 |
|
|
reg [ 7:0] code_temp;
|
| 497 |
|
|
begin
|
| 498 |
|
|
rx_stimulus_working_frame.frombits(frame);
|
| 499 |
|
|
column_index = 0;
|
| 500 |
|
|
lane_index = 0;
|
| 501 |
|
|
byte_count = 0;
|
| 502 |
|
|
// send preamble
|
| 503 |
|
|
rx_stimulus_send_column(32'h555555FB, 4'b0001);
|
| 504 |
|
|
rx_stimulus_send_column(32'hD5555555, 4'b0000);
|
| 505 |
|
|
// send complete columns
|
| 506 |
|
|
while (rx_stimulus_working_frame.ctrl[column_index] === 4'b1111)
|
| 507 |
|
|
begin
|
| 508 |
|
|
rx_stimulus_send_column(rx_stimulus_working_frame.data[column_index],
|
| 509 |
|
|
4'b0000);
|
| 510 |
|
|
column_index = column_index + 1;
|
| 511 |
|
|
byte_count = byte_count + 4;
|
| 512 |
|
|
end
|
| 513 |
|
|
current_column_data = rx_stimulus_working_frame.data[column_index];
|
| 514 |
|
|
current_column_ctrl = rx_stimulus_working_frame.ctrl[column_index];
|
| 515 |
|
|
while (current_column_ctrl[lane_index])
|
| 516 |
|
|
begin
|
| 517 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 518 |
|
|
scratch_column_data[lane_index*8+J] =
|
| 519 |
|
|
current_column_data[lane_index*8+J];
|
| 520 |
|
|
scratch_column_ctrl[lane_index] = 0;
|
| 521 |
|
|
lane_index = lane_index + 1;
|
| 522 |
|
|
byte_count = byte_count + 1;
|
| 523 |
|
|
end
|
| 524 |
|
|
// send any padding required
|
| 525 |
|
|
while (byte_count < `MIN_FRAME_DATA_BYTES)
|
| 526 |
|
|
begin
|
| 527 |
|
|
if (lane_index == 4)
|
| 528 |
|
|
begin
|
| 529 |
|
|
rx_stimulus_send_column(scratch_column_data,
|
| 530 |
|
|
scratch_column_ctrl);
|
| 531 |
|
|
lane_index = 0;
|
| 532 |
|
|
end
|
| 533 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 534 |
|
|
scratch_column_data[lane_index*8+J] = 0;
|
| 535 |
|
|
scratch_column_ctrl[lane_index] = 0;
|
| 536 |
|
|
lane_index = lane_index + 1;
|
| 537 |
|
|
byte_count = byte_count + 1;
|
| 538 |
|
|
end // while (byte_count < `MIN_FRAME_DATA_BYTES)
|
| 539 |
|
|
// send the CRC
|
| 540 |
|
|
for (I = 3; I >= 0; I = I - 1)
|
| 541 |
|
|
begin
|
| 542 |
|
|
if (lane_index == 4)
|
| 543 |
|
|
begin
|
| 544 |
|
|
rx_stimulus_send_column(scratch_column_data,
|
| 545 |
|
|
scratch_column_ctrl);
|
| 546 |
|
|
lane_index = 0;
|
| 547 |
|
|
end
|
| 548 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 549 |
|
|
scratch_column_data[lane_index*8+J] =
|
| 550 |
|
|
rx_stimulus_working_frame.crc[I*8+J];
|
| 551 |
|
|
scratch_column_ctrl = 0;
|
| 552 |
|
|
lane_index = lane_index + 1;
|
| 553 |
|
|
end // for (I = 3; I >= 0; I = I - 1)
|
| 554 |
|
|
// send the terminate/error column
|
| 555 |
|
|
if (lane_index == 4)
|
| 556 |
|
|
begin
|
| 557 |
|
|
rx_stimulus_send_column(scratch_column_data,
|
| 558 |
|
|
scratch_column_ctrl);
|
| 559 |
|
|
lane_index = 0;
|
| 560 |
|
|
end
|
| 561 |
|
|
// send an /E/ if underrun, /T/ if not
|
| 562 |
|
|
code_temp = rx_stimulus_working_frame.underrun ? 8'hFE : 8'hFD;
|
| 563 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 564 |
|
|
scratch_column_data[lane_index*8+J] = code_temp[J];
|
| 565 |
|
|
scratch_column_ctrl[lane_index] = 1;
|
| 566 |
|
|
|
| 567 |
|
|
lane_index = lane_index + 1;
|
| 568 |
|
|
while (lane_index < 4)
|
| 569 |
|
|
begin
|
| 570 |
|
|
code_temp = 8'h07;
|
| 571 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 572 |
|
|
scratch_column_data[lane_index*8+J] = code_temp[J];
|
| 573 |
|
|
scratch_column_ctrl[lane_index] = 1;
|
| 574 |
|
|
lane_index = lane_index + 1;
|
| 575 |
|
|
end
|
| 576 |
|
|
rx_stimulus_send_column(scratch_column_data,
|
| 577 |
|
|
scratch_column_ctrl);
|
| 578 |
|
|
$display("Receiver: frame inserted into PHY interface");
|
| 579 |
|
|
end
|
| 580 |
|
|
endtask // rx_stimulus_send_frame
|
| 581 |
|
|
|
| 582 |
|
|
initial
|
| 583 |
|
|
begin : p_rx_stimulus
|
| 584 |
|
|
integer I;
|
| 585 |
71 |
fisher5090 |
$display("Timing checks are not valid");
|
| 586 |
55 |
fisher5090 |
while (reset !== 0)
|
| 587 |
|
|
rx_stimulus_send_idle;
|
| 588 |
71 |
fisher5090 |
for (I = 0; I < 100; I = I + 1)
|
| 589 |
55 |
fisher5090 |
rx_stimulus_send_idle;
|
| 590 |
71 |
fisher5090 |
$display("Timing checks are valid");
|
| 591 |
55 |
fisher5090 |
rx_stimulus_send_frame(frame0.tobits(0));
|
| 592 |
|
|
rx_stimulus_send_idle;
|
| 593 |
|
|
rx_stimulus_send_idle;
|
| 594 |
|
|
rx_stimulus_send_frame(frame1.tobits(0));
|
| 595 |
|
|
rx_stimulus_send_idle;
|
| 596 |
|
|
rx_stimulus_send_idle;
|
| 597 |
|
|
rx_stimulus_send_frame(frame2.tobits(0));
|
| 598 |
|
|
rx_stimulus_send_idle;
|
| 599 |
|
|
rx_stimulus_send_idle;
|
| 600 |
|
|
rx_stimulus_send_frame(frame3.tobits(0));
|
| 601 |
|
|
while (1)
|
| 602 |
|
|
rx_stimulus_send_idle;
|
| 603 |
|
|
end // block: p_rx_stimulus
|
| 604 |
|
|
|
| 605 |
71 |
fisher5090 |
|
| 606 |
|
|
/* rx monitor - checks that the receiver extracts the information
|
| 607 |
|
|
* inserted into the PHY interface
|
| 608 |
|
|
*/
|
| 609 |
|
|
task wait_on_rx_clk;
|
| 610 |
|
|
begin
|
| 611 |
|
|
@(posedge rx_clk);
|
| 612 |
|
|
#6399;
|
| 613 |
|
|
end
|
| 614 |
|
|
endtask // wait_on_rx_clk
|
| 615 |
|
|
|
| 616 |
|
|
task rx_monitor_check_frame;
|
| 617 |
|
|
input `FRAME_TYP frame;
|
| 618 |
|
|
integer column_count, I, J;
|
| 619 |
|
|
reg [31:0] current_column_data;
|
| 620 |
|
|
reg good_frame_flagged;
|
| 621 |
|
|
reg bad_frame_flagged;
|
| 622 |
|
|
reg wrong;
|
| 623 |
|
|
begin
|
| 624 |
|
|
rx_monitor_working_frame.frombits(frame);
|
| 625 |
|
|
column_count = 0;
|
| 626 |
|
|
wrong = 0;
|
| 627 |
|
|
// wait for the first real column of data
|
| 628 |
|
|
while (rx_data_valid === 8'b00000000)
|
| 629 |
|
|
wait_on_rx_clk;
|
| 630 |
|
|
// frame has started, get columns of frame
|
| 631 |
|
|
while (rx_data_valid !== 8'b00000000)
|
| 632 |
|
|
begin
|
| 633 |
|
|
// only check contents of good frames
|
| 634 |
|
|
if (!rx_monitor_working_frame.underrun)
|
| 635 |
|
|
begin
|
| 636 |
|
|
if (rx_data_valid !== { rx_monitor_working_frame.ctrl[column_count+1],
|
| 637 |
|
|
rx_monitor_working_frame.ctrl[column_count] })
|
| 638 |
|
|
$display("ERROR: Receiver fail: RX_DATA_VALID incorrect rx_data_valid is %x, expected is %x %x",rx_data_valid,rx_monitor_working_frame.ctrl[column_count+1],rx_monitor_working_frame.ctrl[column_count]);
|
| 639 |
|
|
current_column_data = rx_monitor_working_frame.data[column_count];
|
| 640 |
|
|
for (I = 0; I < 4; I = I + 1)
|
| 641 |
|
|
if (rx_data_valid[I])
|
| 642 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 643 |
|
|
if (rx_data[I*8+J] !== current_column_data[I*8+J])
|
| 644 |
|
|
wrong = 1;
|
| 645 |
|
|
if(wrong == 1)
|
| 646 |
|
|
$display("ERROR: Receiver fail : 1 RX_DATA incorrect rx_data is %x, expected is %x",rx_data[31:0],current_column_data[31:0]);
|
| 647 |
|
|
current_column_data = rx_monitor_working_frame.data[column_count+1];
|
| 648 |
|
|
wrong = 0;
|
| 649 |
|
|
for (I = 4; I < 8; I = I + 1)
|
| 650 |
|
|
if (rx_data_valid[I])
|
| 651 |
|
|
for (J = 0; J < 8; J = J + 1)
|
| 652 |
|
|
if (rx_data[I*8+J] !== current_column_data[(I-4)*8+J])
|
| 653 |
|
|
wrong = 1;
|
| 654 |
|
|
if(wrong == 1)
|
| 655 |
|
|
$display("ERROR: Receiver fail : 2 RX_DATA incorrect rx_data is %x, expected is %x",rx_data[63:32],current_column_data[31:0]);
|
| 656 |
|
|
end // if (!rx_monitor_working_frame.underrun)
|
| 657 |
|
|
|
| 658 |
|
|
good_frame_flagged = rx_good_frame;
|
| 659 |
|
|
bad_frame_flagged = rx_bad_frame;
|
| 660 |
|
|
column_count = column_count + 2;
|
| 661 |
|
|
wait_on_rx_clk;
|
| 662 |
|
|
end // while (RX_DATA_VALID != 8'b00000000)
|
| 663 |
|
|
// check whether the frame has been flagged at the right time
|
| 664 |
|
|
while (!good_frame_flagged && !bad_frame_flagged)
|
| 665 |
|
|
begin
|
| 666 |
|
|
good_frame_flagged = rx_good_frame;
|
| 667 |
|
|
bad_frame_flagged = rx_bad_frame;
|
| 668 |
|
|
if (rx_data_valid !== 8'b00000000)
|
| 669 |
|
|
$display("ERROR: Receiver fail: New frame received before good/bad flag from previous frame");
|
| 670 |
|
|
wait_on_rx_clk;
|
| 671 |
|
|
end
|
| 672 |
|
|
if (rx_monitor_working_frame.underrun)
|
| 673 |
|
|
begin
|
| 674 |
|
|
if (good_frame_flagged)
|
| 675 |
|
|
$display("ERROR: Receive Fail: bad frame flagged as good");
|
| 676 |
|
|
end
|
| 677 |
|
|
else
|
| 678 |
|
|
begin
|
| 679 |
|
|
if (bad_frame_flagged)
|
| 680 |
|
|
$display("ERROR: Receive Fail: good frame flagged as bad");
|
| 681 |
|
|
end
|
| 682 |
|
|
$display("Receiver: Frame extracted from client interface");
|
| 683 |
|
|
end
|
| 684 |
|
|
endtask // rx_monitor_check_frame
|
| 685 |
|
|
|
| 686 |
|
|
/*---------------------------------------------------------------------------
|
| 687 |
|
|
-- RX Monitor process. This process checks the data coming out of the
|
| 688 |
|
|
receiver
|
| 689 |
|
|
-- to make sure that it matches that inserted into the transmitter.
|
| 690 |
|
|
---------------------------------------------------------------------------*/
|
| 691 |
|
|
initial
|
| 692 |
|
|
begin : p_rx_monitor
|
| 693 |
|
|
rx_monitor_finished = 0;
|
| 694 |
|
|
|
| 695 |
|
|
// first, get synced up with the RX clock
|
| 696 |
|
|
@(negedge reset)
|
| 697 |
|
|
wait_on_rx_clk;
|
| 698 |
|
|
|
| 699 |
|
|
rx_monitor_check_frame(frame0.tobits(0));
|
| 700 |
|
|
rx_monitor_check_frame(frame1.tobits(0));
|
| 701 |
|
|
rx_monitor_check_frame(frame2.tobits(0));
|
| 702 |
|
|
rx_monitor_check_frame(frame3.tobits(0));
|
| 703 |
|
|
rx_monitor_finished = 1;
|
| 704 |
|
|
end // block: p_rx_monitor
|
| 705 |
|
|
|
| 706 |
|
|
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
55 |
fisher5090 |
// reset process
|
| 710 |
|
|
initial
|
| 711 |
|
|
begin
|
| 712 |
|
|
$display("Resetting the core...");
|
| 713 |
|
|
reset <= 1;
|
| 714 |
|
|
#200000;
|
| 715 |
|
|
reset <= 0;
|
| 716 |
|
|
end
|
| 717 |
|
|
|
| 718 |
|
|
// Simulation control
|
| 719 |
71 |
fisher5090 |
assign simulation_finished =
|
| 720 |
|
|
rx_monitor_finished
|
| 721 |
|
|
;
|
| 722 |
|
|
|
| 723 |
55 |
fisher5090 |
initial
|
| 724 |
|
|
begin
|
| 725 |
71 |
fisher5090 |
fork: sim_in_progress
|
| 726 |
|
|
@(posedge simulation_finished) disable sim_in_progress;
|
| 727 |
|
|
#10000000 disable sim_in_progress;
|
| 728 |
|
|
join
|
| 729 |
|
|
if (simulation_finished)
|
| 730 |
|
|
$display("** Finish: Simulation Stopped");
|
| 731 |
|
|
else
|
| 732 |
|
|
$display("** Failure: ERROR: Testbench timed out");
|
| 733 |
|
|
$stop;
|
| 734 |
55 |
fisher5090 |
end // initial begin
|
| 735 |
|
|
|
| 736 |
71 |
fisher5090 |
endmodule
|
| 737 |
|
|
|
| 738 |
|
|
|
| 739 |
|
|
|
