OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [bench/] [TransmitTop_tb.v] - Blame information for rev 72

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 fisher5090
`include "TransmitTop.v"
2
module TransmitTop_tb();
3
 
4
//Input from user logic
5
reg [63:0] TX_DATA;
6
reg [63:0] TX_DATA_int;
7
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
8
reg Append_last_bit;
9
reg TX_CLK;
10
reg RESET;
11
reg TX_START; // This signify the first frame of data
12
reg TX_UNDERRUN; // this will cause an error to be injected into the data
13
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
14
 
15
//input to transmit fault signals
16
reg RXTXLINKFAULT;
17
reg LOCALLINKFAULT;
18
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
19
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
20
 
21
//apply pause timing
22
reg [15:0] FC_TX_PAUSEDATA;
23
reg FC_TX_PAUSEVALID;
24
 
25
//apply configuration value
26
reg [31:0] TX_CFG_REG_VALUE;
27
reg TX_CFG_REG_VALID;
28
 
29
//output to stat register
30
wire TX_STATS_VALID;
31
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
32
wire [63:0] TXD;
33
wire [7:0] TXC;
34
wire TX_ACK;
35
reg D_START;
36
 
37
reg START_TX_BITS;
38
 
39
// Initialize all variables
40
initial begin
41
  Append_last_bit = 0;
42
  TX_CLK = 1;       // initial value of clock
43
  RESET <= 0;       // initial value of reset
44
  TX_START <= 0;      // initial value of enable
45
  TX_DATA_VALID <= 8'h00;
46
  D_START = 0;
47
  FC_TX_PAUSEVALID <= 0;
48
  FC_TX_PAUSEDATA <= 0;
49
  FC_TRANS_PAUSEDATA <= 0;
50
  FC_TRANS_PAUSEVAL <= 0;
51
  TX_UNDERRUN = 0;
52
  #5 RESET <= 1;    // Assert the reset
53
  #10 RESET <= 0;    // De-assert the reset 
54
 
55
  #15 TX_START <= 1;
56
      TX_DATA_VALID <= 8'hFF;
57
        D_START <= 1;
58
  #20 TX_START <= 0;
59
  #400  //TX_DATA_VALID <= 8'h00;
60
        //FC_TX_PAUSEVALID <= 1;
61
        //FC_TX_PAUSEDATA <= 30;
62
        //  FC_TRANS_PAUSEDATA <= 30;
63
        //  FC_TRANS_PAUSEVAL <= 1;
64
         TX_DATA_VALID <= 8'h7f;
65
  #10   TX_DATA_VALID <= 8'h00;
66
                D_START = 0;
67
        //FC_TX_PAUSEVALID <= 0;
68
        //FC_TX_PAUSEDATA <= 0;
69
        //  FC_TRANS_PAUSEDATA <= 0;
70
        //  FC_TRANS_PAUSEVAL <= 0;
71
  #20 TX_START <= 1;
72
      TX_DATA_VALID <= 8'hFF;
73
        D_START = 1;
74
  #20 TX_START <= 0;
75
  #400  TX_DATA_VALID <= 8'h00;
76
  #10   TX_DATA_VALID <= 8'h00;
77
                D_START = 0;
78
  #1300 $finish;     // Terminate simulation
79
end
80
 
81
always @(posedge D_START or posedge TX_CLK)
82
begin
83
  if (D_START == 0) begin
84
    TX_DATA = 64'h0000000000000000;
85
  end
86
  //else if (TX_DATA_VALID == 8'h07) begin
87
  //  TX_DATA = 64'h000000000077FFCC;
88
  //end
89
  else if (Append_last_bit == 1) begin
90
//    TX_DATA = 64'h202020202077FFCC;
91
    TX_DATA = 64'h000000000077FFCC;
92
  end
93
  else if (START_TX_BITS == 1) begin
94
    TX_DATA = TX_DATA + 1;
95
  end
96
  else begin
97
    TX_DATA = 64'h0000000000000001;
98
  end
99
end
100
 
101
 
102
 
103
always @(TX_DATA)
104
begin
105
  if (TX_DATA == 2) begin
106
     TX_DATA_int[31:0] <= TX_DATA[31:0];
107
     TX_DATA_int[47:32] <= 300;
108
     TX_DATA_int[63:48] <= TX_DATA[63:48];
109
  end
110
  else begin
111
     TX_DATA_int <= TX_DATA;
112
  end
113
 
114
end
115
 
116
 
117
always @(TX_ACK | TX_START)
118
begin
119
  if (TX_ACK) begin
120
    START_TX_BITS = 1;
121
  end
122
  else if (TX_START) begin
123
    START_TX_BITS = 0;
124
  end
125
end
126
 
127
 
128
// Clock generator
129
always begin
130
  #5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
131
end
132
 
133
// Connect DUT to test bench
134
TRANSMIT_TOP U_top_module (
135
TX_DATA_int,
136
TX_DATA_VALID,
137
TX_CLK,
138
RESET,
139
TX_START,
140
TX_ACK,
141
TX_UNDERRUN,
142
TX_IFG_DELAY,
143
RXTXLINKFAULT,
144
LOCALLINKFAULT,
145
TX_STATS_VALID,
146
TXSTATREGPLUS,
147
TXD,
148
TXC,
149
FC_TRANS_PAUSEDATA,
150
FC_TRANS_PAUSEVAL,
151
FC_TX_PAUSEDATA,
152
FC_TX_PAUSEVALID,
153
TX_CFG_REG_VALUE,
154
TX_CFG_REG_VALID
155
);
156
 
157
 
158
 
159
 
160
endmodule
161
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.