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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [mgmt/] [manage_registers.v] - Blame information for rev 59

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`timescale 1ns / 1ps
2 
//////////////////////////////////////////////////////////////////////
3 
////                                                                                                                                                                    ////
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//// MODULE NAME: manage_registers                                                                                      ////
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////                                                                                                                                                                    ////
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//// DESCRIPTION: implement read & write logic for configuration  ////
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////              and statistics registers                        ////
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////                                                                                                                                                                    ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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////  http://www.opencores.org/projects/ethmac10g/                                              ////
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////                                                                                                                                                                    ////
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//// AUTHOR(S):                                                                                                                                 ////
13 
//// Zheng Cao                                                               ////
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////                                                                                                    ////
15 
//////////////////////////////////////////////////////////////////////
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////                                                                                                                                                                    ////
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//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////
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////                                                                                                                                                                    ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                                                   ////
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////                                                                                                                                                                    ////
40 
//////////////////////////////////////////////////////////////////////
41 
//
42 
// CVS REVISION HISTORY:
43 
//
44 
// $Log: not supported by cvs2svn $
45 
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
46 
//
47 
//
48 
//
49 
//////////////////////////////////////////////////////////////////////
50 
module manage_registers(mgmt_clk, rxclk, txclk, reset, mgmt_opcode, mgmt_addr, mgmt_wr_data, mgmt_rd_data, mgmt_miim_sel, mgmt_req,
51 
mgmt_miim_rdy, rxStatRegPlus, txStatRegPlus, cfgRxRegData, cfgTxRegData, mdio_opcode, mdio_data_out, mdio_data_in, mdio_in_valid,
52 
mgmt_config, mdio_out_valid);
53 
input mgmt_clk; //management clock
54 
input rxclk; //receive clock
55 
input txclk; //transmit clock
56 
input reset; //system reset
57 
input[1:0] mgmt_opcode; //management opcode(read/write/mdio)
58 
input[9:0] mgmt_addr; //management address, including addresses of configuration, statistics and MDIO registers
59 
input[31:0] mgmt_wr_data; //Data to be writen to Configuration/MDIO registers
60 
output[31:0] mgmt_rd_data; //Data read from Configuration/Statistics/MDIO registers
61 
input mgmt_miim_sel; //select internal register or MDIO registers
62 
input mgmt_req; //Valid when operate statistics/MDIO registers, one clock valid____|-|____
63 
output mgmt_miim_rdy; //Indicate the Management Module is in IDLE Status
64 
input[18:0] rxStatRegPlus; //From Receive Module, one bit is related to one receive statistics register
65 
input[14:0] txStatRegPlus; //From Transmit Module, one bit is related to one transmit statistics register
66 
output[52:0] cfgRxRegData; //To Receive Module, config receive module
67 
output[9:0] cfgTxRegData; //To Transmit Module, config transmit module
68 
output[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode
69 
output mdio_out_valid; //Indicate mdio_data_out is valid
70 
output[41:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}
71 
input[31:0] mdio_data_in; //Data read from MDIO
72 
input mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid
73 
output[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency
74 
 
75 
parameter IDLE =0, MDIO_OPERATE =1, STAT_OPERATE =2, CONFIG_OPERATE =3;
76 
parameter TP = 1;
77 
 
78 
/////////////////////////////////////////////
79 
// Statistics Register Definition
80 
/////////////////////////////////////////////
81 
 
82 
//--Receive Related
83 
reg[63:0] frame_received_good;
84 
reg[63:0] fcs_error;
85 
reg[63:0] broadcast_received_good;
86 
reg[63:0] multicast_received_good;
87 
reg[63:0] frame_64_good;
88 
reg[63:0] frame_65_127_good;
89 
reg[63:0] frame_128_255_good;
90 
reg[63:0] frame_256_511_good;
91 
reg[63:0] frame_512_1023_good;
92 
reg[63:0] frame_1024_max_good;
93 
reg[63:0] control_frame_good;
94 
reg[63:0] lt_out_range;
95 
reg[63:0] tagged_frame_good;
96 
reg[63:0] pause_frame_good;
97 
reg[63:0] unsupported_control_frame;
98 
reg[63:0] oversize_frame_good;
99 
reg[63:0] undersize_frame;
100 
reg[63:0] fragment_frame;
101 
reg[63:0] total_bytes_recved;
102 
 
103 
//--Transmit Related
104 
reg[63:0] total_bytes_transed;
105 
reg[63:0] good_frame_transed;
106 
reg[63:0] broadcast_frame_transed;
107 
reg[63:0] multicast_frame_transed;
108 
reg[63:0] underrun_error;
109 
reg[63:0] control_frame_transed;
110 
reg[63:0] frame_64_transed;
111 
reg[63:0] frame_65_127_transed;
112 
reg[63:0] frame_128_255_transed;
113 
reg[63:0] frame_256_511_transed;
114 
reg[63:0] frame_512_1023_transed;
115 
reg[63:0] frame_1024_max_transed;
116 
reg[63:0] tagged_frame_transed;
117 
reg[63:0] pause_frame_transed;
118 
reg[63:0] oversize_frame_transed;
119 
 
120 
/////////////////////////////////////////////
121 
// Configuration Registers Definition
122 
/////////////////////////////////////////////
123 
 
124 
reg[31:0] recv_config0;
125 
reg[31:0] recv_config1;
126 
reg[31:0] trans_config;
127 
reg[31:0] flow_control_config;
128 
reg[31:0] rs_config;
129 
reg[31:0] mgmt_config;
130 
 
131 
/////////////////////////////////////////////
132 
// Input registers
133 
/////////////////////////////////////////////
134 
 
135 
reg[8:0] mgmt_addr_d1;
136 
always@(posedge mgmt_clk or posedge reset)begin
137 
      if(reset)
138 
                  mgmt_addr_d1 <=#TP 0;
139 
                else
140 
                  mgmt_addr_d1 <=#TP mgmt_addr[8:0];
141 
end
142 
 
143 
reg mdio_in_valid_d1;
144 
always@(posedge mgmt_clk or posedge reset) begin
145 
      if(reset)
146 
                  mdio_in_valid_d1 <=#TP 1'b0;
147 
                else
148 
                  mdio_in_valid_d1 <=#TP mdio_in_valid;
149 
end
150 
 
151 
/////////////////////////////////////////////
152 
// State Machine
153 
/////////////////////////////////////////////
154 
reg[1:0] state;
155 
 
156 
reg read_done;
157 
always@(posedge mgmt_clk or posedge reset)begin
158 
    if (reset)
159 
            state <=#TP IDLE;
160 
         else begin
161 
            case (state)
162 
                    IDLE: begin
163 
                             if(mgmt_req & mgmt_miim_sel)
164 
                                    state <=#TP MDIO_OPERATE;
165 
                                  else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])
166 
                                    state <=#TP STAT_OPERATE;
167 
                                  else if(~mgmt_miim_sel & mgmt_addr[9])
168 
                                    state <=#TP CONFIG_OPERATE;
169 
                                  else
170 
                                    state <=#TP IDLE;
171 
                         end
172 
          MDIO_OPERATE: begin
173 
              if(~mdio_in_valid & mdio_in_valid_d1)
174 
                state <=#TP IDLE;
175 
              else
176 
                state <=#TP MDIO_OPERATE;
177 
          end
178 
          STAT_OPERATE: begin
179 
              if(read_done)
180 
                state <=#TP IDLE;
181 
              else
182 
                state <=#TP STAT_OPERATE;
183 
          end
184 
          CONFIG_OPERATE: begin
185 
              if(mgmt_req & mgmt_miim_sel)
186 
                                    state <=#TP MDIO_OPERATE;
187 
                                  else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])
188 
                                    state <=#TP STAT_OPERATE;
189 
                                  else if(~mgmt_miim_sel & mgmt_addr[9])
190 
                                    state <=#TP CONFIG_OPERATE;
191 
                                  else
192 
                                    state <=#TP IDLE;
193 
          end
194 
      endcase
195 
   end
196 
end
197 
 
198 
/////////////////////////////////////////////
199 
// Write Statistics Registers
200 
/////////////////////////////////////////////
201 
 
202 
//--Receive Related
203 
always@(posedge rxclk or posedge reset) begin
204 
      if (reset)
205 
              frame_received_good <=#TP 1;
206 
           else if(rxStatRegPlus[0])
207 
         frame_received_good <=#TP frame_received_good + 1;
208 
end
209 
 
210 
always@(posedge rxclk or posedge reset) begin
211 
      if (reset)
212 
              fcs_error <=#TP 2;
213 
           else if(rxStatRegPlus[1])
214 
         fcs_error <=#TP fcs_error + 1;
215 
end
216 
 
217 
always@(posedge rxclk or posedge reset) begin
218 
      if (reset)
219 
              broadcast_received_good <=#TP 0;
220 
           else if(rxStatRegPlus[2])
221 
         broadcast_received_good <=#TP broadcast_received_good + 1;
222 
end
223 
 
224 
always@(posedge rxclk or posedge reset) begin
225 
      if (reset)
226 
              multicast_received_good <=#TP 0;
227 
           else if(rxStatRegPlus[3])
228 
         multicast_received_good <=#TP multicast_received_good + 1;
229 
end
230 
 
231 
always@(posedge rxclk or posedge reset) begin
232 
      if (reset)
233 
              frame_64_good <=#TP 0;
234 
           else if(rxStatRegPlus[4])
235 
         frame_64_good <=#TP frame_64_good + 1;
236 
end
237 
 
238 
always@(posedge rxclk or posedge reset) begin
239 
      if (reset)
240 
              frame_65_127_good <=#TP 0;
241 
           else if(rxStatRegPlus[5])
242 
         frame_65_127_good <=#TP frame_65_127_good + 1;
243 
end
244 
 
245 
always@(posedge rxclk or posedge reset) begin
246 
      if (reset)
247 
              frame_128_255_good <=#TP 0;
248 
           else if(rxStatRegPlus[6])
249 
         frame_128_255_good <=#TP frame_128_255_good + 1;
250 
end
251 
 
252 
always@(posedge rxclk or posedge reset) begin
253 
      if (reset)
254 
              frame_256_511_good <=#TP 0;
255 
           else if(rxStatRegPlus[7])
256 
         frame_256_511_good <=#TP frame_256_511_good + 1;
257 
end
258 
 
259 
always@(posedge rxclk or posedge reset) begin
260 
      if (reset)
261 
              frame_512_1023_good <=#TP 0;
262 
           else if(rxStatRegPlus[8])
263 
         frame_512_1023_good <=#TP frame_512_1023_good + 1;
264 
end
265 
 
266 
always@(posedge rxclk or posedge reset) begin
267 
      if (reset)
268 
              frame_1024_max_good <=#TP 0;
269 
           else if(rxStatRegPlus[9])
270 
         frame_1024_max_good <=#TP frame_1024_max_good + 1;
271 
end
272 
 
273 
always@(posedge rxclk or posedge reset) begin
274 
      if (reset)
275 
              control_frame_good <=#TP 0;
276 
           else if(rxStatRegPlus[10])
277 
         control_frame_good <=#TP control_frame_good + 1;
278 
end
279 
 
280 
always@(posedge rxclk or posedge reset) begin
281 
      if (reset)
282 
              lt_out_range <=#TP 0;
283 
           else if(rxStatRegPlus[11])
284 
         lt_out_range <=#TP lt_out_range + 1;
285 
end
286 
 
287 
always@(posedge rxclk or posedge reset) begin
288 
      if (reset)
289 
              tagged_frame_good <=#TP 0;
290 
           else if(rxStatRegPlus[12])
291 
         tagged_frame_good <=#TP tagged_frame_good + 1;
292 
end
293 
 
294 
always@(posedge rxclk or posedge reset) begin
295 
      if (reset)
296 
              pause_frame_good <=#TP 0;
297 
           else if(rxStatRegPlus[13])
298 
         pause_frame_good <=#TP pause_frame_good + 1;
299 
end
300 
 
301 
always@(posedge rxclk or posedge reset) begin
302 
      if (reset)
303 
              unsupported_control_frame <=#TP 0;
304 
           else if(rxStatRegPlus[14])
305 
         unsupported_control_frame <=#TP unsupported_control_frame + 1;
306 
end
307 
 
308 
always@(posedge rxclk or posedge reset) begin
309 
      if (reset)
310 
              oversize_frame_good <=#TP 0;
311 
           else if(rxStatRegPlus[15])
312 
         oversize_frame_good <=#TP oversize_frame_good + 1;
313 
end
314 
 
315 
always@(posedge rxclk or posedge reset) begin
316 
      if (reset)
317 
              undersize_frame <=#TP 0;
318 
           else if(rxStatRegPlus[16])
319 
         undersize_frame <=#TP undersize_frame + 1;
320 
end
321 
 
322 
always@(posedge rxclk or posedge reset) begin
323 
      if (reset)
324 
              fragment_frame <=#TP 0;
325 
           else if(rxStatRegPlus[17])
326 
         fragment_frame <=#TP fragment_frame + 1;
327 
end
328 
 
329 
always@(posedge rxclk or posedge reset) begin
330 
      if (reset)
331 
              total_bytes_recved <=#TP 0;
332 
           else if(rxStatRegPlus[18])
333 
         total_bytes_recved <=#TP total_bytes_recved + 1;
334 
end
335 
 
336 
//--Transmit Related
337 
always@(posedge txclk or posedge reset) begin
338 
      if (reset)
339 
              total_bytes_transed <=#TP 0;
340 
           else if(txStatRegPlus[0])
341 
         total_bytes_transed <=#TP total_bytes_transed + 1;
342 
end
343 
 
344 
always@(posedge txclk or posedge reset) begin
345 
      if (reset)
346 
              good_frame_transed <=#TP 0;
347 
           else if(txStatRegPlus[1])
348 
         good_frame_transed <=#TP good_frame_transed + 1;
349 
end
350 
 
351 
always@(posedge txclk or posedge reset) begin
352 
      if (reset)
353 
              broadcast_frame_transed <=#TP 0;
354 
           else if(txStatRegPlus[2])
355 
         broadcast_frame_transed <=#TP broadcast_frame_transed + 1;
356 
end
357 
 
358 
always@(posedge txclk or posedge reset) begin
359 
      if (reset)
360 
              multicast_frame_transed <=#TP 0;
361 
           else if(txStatRegPlus[3])
362 
         multicast_frame_transed <=#TP multicast_frame_transed + 1;
363 
end
364 
 
365 
always@(posedge txclk or posedge reset) begin
366 
      if (reset)
367 
              underrun_error <=#TP 0;
368 
           else if(txStatRegPlus[4])
369 
         underrun_error <=#TP underrun_error + 1;
370 
end
371 
 
372 
always@(posedge txclk or posedge reset) begin
373 
      if (reset)
374 
              control_frame_transed <=#TP 0;
375 
           else if(txStatRegPlus[5])
376 
         control_frame_transed <=#TP control_frame_transed + 1;
377 
end
378 
 
379 
always@(posedge txclk or posedge reset) begin
380 
      if (reset)
381 
              frame_64_transed <=#TP 0;
382 
           else if(txStatRegPlus[6])
383 
         frame_64_transed <=#TP frame_64_transed + 1;
384 
end
385 
 
386 
always@(posedge txclk or posedge reset) begin
387 
      if (reset)
388 
              frame_65_127_transed <=#TP 0;
389 
           else if(txStatRegPlus[7])
390 
         frame_65_127_transed <=#TP frame_65_127_transed + 1;
391 
end
392 
 
393 
always@(posedge txclk or posedge reset) begin
394 
      if (reset)
395 
              frame_128_255_transed <=#TP 0;
396 
           else if(txStatRegPlus[8])
397 
         frame_128_255_transed <=#TP frame_128_255_transed + 1;
398 
end
399 
 
400 
always@(posedge txclk or posedge reset) begin
401 
      if (reset)
402 
              frame_256_511_transed <=#TP 0;
403 
           else if(txStatRegPlus[9])
404 
         frame_256_511_transed <=#TP frame_256_511_transed + 1;
405 
end
406 
 
407 
always@(posedge txclk or posedge reset) begin
408 
      if (reset)
409 
              frame_512_1023_transed <=#TP 0;
410 
           else if(txStatRegPlus[10])
411 
         frame_512_1023_transed <=#TP frame_512_1023_transed + 1;
412 
end
413 
 
414 
always@(posedge txclk or posedge reset) begin
415 
      if (reset)
416 
              frame_1024_max_transed <=#TP 0;
417 
           else if(txStatRegPlus[11])
418 
         frame_1024_max_transed <=#TP frame_1024_max_transed + 1;
419 
end
420 
 
421 
always@(posedge txclk or posedge reset) begin
422 
      if (reset)
423 
              tagged_frame_transed <=#TP 0;
424 
           else if(txStatRegPlus[12])
425 
         tagged_frame_transed <=#TP tagged_frame_transed + 1;
426 
end
427 
 
428 
always@(posedge txclk or posedge reset) begin
429 
      if (reset)
430 
              pause_frame_transed <=#TP 0;
431 
           else if(txStatRegPlus[13])
432 
         pause_frame_transed <=#TP pause_frame_transed + 1;
433 
end
434 
 
435 
always@(posedge txclk or posedge reset) begin
436 
      if (reset)
437 
              oversize_frame_transed <=#TP 0;
438 
           else if(txStatRegPlus[14])
439 
         oversize_frame_transed <=#TP oversize_frame_transed + 1;
440 
end
441 
 
442 
/////////////////////////////////////////////
443 
// Read Statistics Registers
444 
/////////////////////////////////////////////
445 
reg[63:0] stat_rd_data;
446 
always@(posedge mgmt_clk or posedge reset) begin
447 
      if(reset)
448 
                  stat_rd_data <=#TP 0;
449 
      else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])begin
450 
                  case (mgmt_addr[7:0])
451 
                      8'h00: stat_rd_data <= frame_received_good;
452 
                      8'h01: stat_rd_data <= fcs_error;
453 
                      8'h02: stat_rd_data <= broadcast_received_good;
454 
                      8'h03: stat_rd_data <= multicast_received_good;
455 
                      8'h04: stat_rd_data <= frame_64_good;
456 
                      8'h05: stat_rd_data <= frame_65_127_good;
457 
                      8'h06: stat_rd_data <= frame_128_255_good;
458 
                      8'h07: stat_rd_data <= frame_256_511_good;
459 
                      8'h08: stat_rd_data <= frame_512_1023_good;
460 
                      8'h09: stat_rd_data <= frame_1024_max_good;
461 
                      8'h0a: stat_rd_data <= control_frame_good;
462 
                      8'h0b: stat_rd_data <= lt_out_range;
463 
                      8'h0c: stat_rd_data <= tagged_frame_good;
464 
                      8'h0d: stat_rd_data <= pause_frame_good;
465 
                      8'h0e: stat_rd_data <= unsupported_control_frame;
466 
                      8'h0f: stat_rd_data <= oversize_frame_good;
467 
                      8'h10: stat_rd_data <= undersize_frame;
468 
                      8'h11: stat_rd_data <= fragment_frame;
469 
                      8'h12: stat_rd_data <= total_bytes_recved;
470 
                      8'h13: stat_rd_data <= total_bytes_transed;
471 
                      8'h20: stat_rd_data <= good_frame_transed;
472 
                      8'h21: stat_rd_data <= broadcast_frame_transed;
473 
                      8'h22: stat_rd_data <= multicast_frame_transed;
474 
                      8'h23: stat_rd_data <= underrun_error;
475 
                      8'h24: stat_rd_data <= control_frame_transed;
476 
                      8'h25: stat_rd_data <= frame_64_transed;
477 
                      8'h26: stat_rd_data <= frame_65_127_transed;
478 
                      8'h27: stat_rd_data <= frame_128_255_transed;
479 
                      8'h28: stat_rd_data <= frame_256_511_transed;
480 
                      8'h29: stat_rd_data <= frame_512_1023_transed;
481 
                      8'h2a: stat_rd_data <= frame_1024_max_transed;
482 
                      8'h2b: stat_rd_data <= tagged_frame_transed;
483 
                      8'h2c: stat_rd_data <= pause_frame_transed;
484 
                      8'h2d: stat_rd_data <= oversize_frame_transed;
485 
            default: stat_rd_data <= 0;
486 
       endcase
487 
    end
488 
end
489 
 
490 
////////////////////////////////////////////////////////
491 
// Select which data to be writen to mgmt_rd_data
492 
////////////////////////////////////////////////////////
493 
reg[31:0] mgmt_rd_data;
494 
reg mgmt_miim_rdy;
495 
reg data_sel;
496 
always@(posedge mgmt_clk or posedge reset) begin
497 
      if(reset) begin
498 
         mgmt_rd_data <=#TP 0;
499 
                        data_sel <=#TP 0;
500 
                        read_done <=#TP 0;
501 
                        mgmt_miim_rdy <=#TP 0;
502 
                end
503 
                else begin
504 
         case (state)
505 
                            IDLE: begin
506 
                                     mgmt_rd_data <=#TP 0;
507 
                                     data_sel <=#TP 1'b0;
508 
                                read_done <=#TP 0;
509 
                                mgmt_miim_rdy <=#TP 1;
510 
                                 end
511 
             STAT_OPERATE: begin
512 
                                mgmt_miim_rdy <=#TP 0;
513 
                                read_done <=#TP 1'b0;
514 
                 if (~data_sel) begin
515 
                                  mgmt_rd_data <=#TP stat_rd_data[31:0];
516 
                                            data_sel <=#TP 1'b1;
517 
                                          end
518 
                                          else if(data_sel)begin
519 
                                            mgmt_rd_data <=#TP stat_rd_data[63:32];
520 
                                                 data_sel <=#TP 1'b0;
521 
                                  mgmt_miim_rdy <=#TP 1;
522 
                                  read_done <=#TP 1'b1;
523 
                                          end
524 
                                 end
525 
                                 CONFIG_OPERATE: begin
526 
                                     case (mgmt_addr_d1[8:4])
527 
                                                5'h00: mgmt_rd_data <=#TP recv_config0;
528 
                       5'h04: mgmt_rd_data <=#TP recv_config1;
529 
                       5'h08: mgmt_rd_data <=#TP trans_config;
530 
                       5'h0c: mgmt_rd_data <=#TP flow_control_config;
531 
                       5'h10: mgmt_rd_data <=#TP rs_config;
532 
                       5'h14: mgmt_rd_data <=#TP mgmt_config;
533 
                                                          default: mgmt_rd_data <=#TP mgmt_rd_data;
534 
                                          endcase
535 
                                 end
536 
             MDIO_OPERATE: begin
537 
                                     if(~mdio_in_valid & mdio_in_valid_d1) begin
538 
                    mgmt_rd_data <=#TP mdio_data_in;
539 
                                                  mgmt_miim_rdy <=#TP 1'b1;
540 
                                          end
541 
                 else begin
542 
                    mgmt_rd_data <=#TP 0;
543 
                                                  mgmt_miim_rdy <=#TP 1'b0;
544 
                 end
545 
             end
546 
             default: begin
547 
                 mgmt_rd_data <=#TP 0;
548 
                                data_sel <=#TP 0;
549 
                                read_done <=#TP 0;
550 
                           mgmt_miim_rdy <=#TP 1;
551 
             end
552 
          endcase
553 
      end
554 
end
555 
 
556 
/////////////////////////////////////////////
557 
// Write Configuration Registers
558 
/////////////////////////////////////////////
559 
reg[31:0] mgmt_wr_data_d1;
560 
always@(posedge mgmt_clk or posedge reset) begin
561 
      if(reset)
562 
                   mgmt_wr_data_d1 <=#TP 0;
563 
                else
564 
                   mgmt_wr_data_d1 <=#TP mgmt_wr_data;
565 
end
566 
 
567 
always@(posedge mgmt_clk or posedge reset)begin
568 
      if(reset)begin
569 
                  recv_config0 <=#TP 0;
570 
        recv_config1 <=#TP 32'h1000;
571 
        trans_config <=#TP 32'h1000;
572 
        flow_control_config <=#TP 32'h6000;
573 
        rs_config <=#TP 0;
574 
        mgmt_config <=#TP 32'h0010;
575 
                end
576 
      else if(~mgmt_miim_sel & mgmt_addr[9]& ~mgmt_opcode[1]) begin
577 
        case (mgmt_addr[8:0])
578 
          9'h000: recv_config0 <=#TP mgmt_wr_data;
579 
          9'h040: recv_config1 <=#TP mgmt_wr_data;
580 
          9'h080: trans_config <=#TP mgmt_wr_data;
581 
          9'h0c0: flow_control_config <=#TP mgmt_wr_data;
582 
          9'h100: rs_config <=#TP mgmt_wr_data;
583 
          9'h140: mgmt_config <=#TP mgmt_wr_data;
584 
                         default: begin
585 
                           recv_config0 <=#TP recv_config0;
586 
            recv_config1 <=#TP recv_config1;
587 
            trans_config <=#TP trans_config;
588 
            flow_control_config <=#TP flow_control_config;
589 
            rs_config <=#TP rs_config;
590 
            mgmt_config <=#TP mgmt_config;
591 
                         end
592 
        endcase
593 
      end
594 
end
595 
 
596 
/////////////////////////////////////////////
597 
// Read Configuration Registers
598 
/////////////////////////////////////////////
599 
 
600 
assign cfgRxRegData = {recv_config1[31:27], recv_config1[15:0], recv_config0};
601 
assign cfgTxRegData = {rs_config[27], trans_config[31:24],flow_control_config[30]};
602 
 
603 
/////////////////////////////////////////////
604 
// Generate MDIO Operations
605 
/////////////////////////////////////////////
606 
reg[41:0] mdio_data_out;
607 
always@(posedge mgmt_clk or posedge reset) begin
608 
      if(reset)
609 
                   mdio_data_out <=#TP 0;
610 
                else if(mgmt_req & mgmt_miim_sel)
611 
                   mdio_data_out <=#TP {mgmt_addr[9:0], mgmt_wr_data[31:0]};
612 
                else
613 
                   mdio_data_out <=#TP mdio_data_out;
614 
end
615 
 
616 
reg[1:0] mdio_opcode;
617 
always@(posedge mgmt_clk or posedge reset) begin
618 
      if(reset)
619 
                  mdio_opcode <=#TP 0;
620 
                else if(mgmt_req & mgmt_miim_sel)
621 
                  mdio_opcode <=#TP mgmt_opcode;
622 
end
623 
 
624 
reg mdio_out_valid;
625 
 
626 
always@(posedge mgmt_clk or posedge reset) begin
627 
      if(reset)
628 
                        mdio_out_valid <=#TP 0;
629 
                else if(mgmt_req & mgmt_miim_sel)
630 
                   mdio_out_valid <=#TP 1'b1;
631 
                else
632 
                   mdio_out_valid <=#TP 1'b0;
633 
end
634 
 
635 
endmodule

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