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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: manage_registers                                ////
////                                                              ////
//// DESCRIPTION: implement read & write logic for configuration  ////
////              and statistics registers                        ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2006/06/15 12:12:27  fisher5090
// modify mgmt_miim_rdy timing sequence
//
// Revision 1.3  2006/06/15 08:25:42  fisher5090
// comments added
//
// Revision 1.2  2006/06/15 05:09:24  fisher5090
// bad coding style, but works, will be modified later
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
module manage_registers(mgmt_clk, rxclk, txclk, reset, mgmt_opcode, mgmt_addr, mgmt_wr_data, mgmt_rd_data, mgmt_miim_sel, mgmt_req,
mgmt_miim_rdy, rxStatRegPlus, txStatRegPlus, cfgRxRegData, cfgTxRegData, mdio_opcode, mdio_data_out, mdio_data_in, mdio_in_valid,
mgmt_config, mdio_out_valid);
input mgmt_clk; //management clock
input rxclk; //receive clock
input txclk; //transmit clock
input reset; //system reset
input[1:0] mgmt_opcode; //management opcode(read/write/mdio)
input[9:0] mgmt_addr; //management address, including addresses of configuration, statistics and MDIO registers
input[31:0] mgmt_wr_data; //Data to be writen to Configuration/MDIO registers
output[31:0] mgmt_rd_data; //Data read from Configuration/Statistics/MDIO registers
input mgmt_miim_sel; //select internal register or MDIO registers
input mgmt_req; //Valid when operate statistics/MDIO registers, one clock valid____|-|____
output mgmt_miim_rdy; //Indicate the Management Module is in IDLE Status
input[18:0] rxStatRegPlus; //From Receive Module, one bit is related to one receive statistics register
input[14:0] txStatRegPlus; //From Transmit Module, one bit is related to one transmit statistics register
output[52:0] cfgRxRegData; //To Receive Module, config receive module
output[9:0] cfgTxRegData; //To Transmit Module, config transmit module
output[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode
output mdio_out_valid; //Indicate mdio_data_out is valid
output[25:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}
input[15:0] mdio_data_in; //Data read from MDIO
input mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid
output[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency
 
parameter IDLE =0, MDIO_OPERATE =1, STAT_OPERATE =2, CONFIG_OPERATE =3;
parameter TP = 1;
 
/////////////////////////////////////////////
// Statistics Register Definition
/////////////////////////////////////////////
 
//--Receive Related
reg[63:0] frame_received_good;
reg[63:0] fcs_error;
reg[63:0] broadcast_received_good;
reg[63:0] multicast_received_good;
reg[63:0] frame_64_good;
reg[63:0] frame_65_127_good;
reg[63:0] frame_128_255_good;
reg[63:0] frame_256_511_good;
reg[63:0] frame_512_1023_good;
reg[63:0] frame_1024_max_good;
reg[63:0] control_frame_good;
reg[63:0] lt_out_range;
reg[63:0] tagged_frame_good;
reg[63:0] pause_frame_good;
reg[63:0] unsupported_control_frame;
reg[63:0] oversize_frame_good;
reg[63:0] undersize_frame;
reg[63:0] fragment_frame;
reg[63:0] total_bytes_recved;
 
//--Transmit Related
reg[63:0] total_bytes_transed;
reg[63:0] good_frame_transed;
reg[63:0] broadcast_frame_transed;
reg[63:0] multicast_frame_transed;
reg[63:0] underrun_error;
reg[63:0] control_frame_transed;
reg[63:0] frame_64_transed;
reg[63:0] frame_65_127_transed;
reg[63:0] frame_128_255_transed;
reg[63:0] frame_256_511_transed;
reg[63:0] frame_512_1023_transed;
reg[63:0] frame_1024_max_transed;
reg[63:0] tagged_frame_transed;
reg[63:0] pause_frame_transed;
reg[63:0] oversize_frame_transed;
 
/////////////////////////////////////////////
// Configuration Registers Definition
/////////////////////////////////////////////
 
reg[31:0] recv_config0;
reg[31:0] recv_config1;
reg[31:0] trans_config;
reg[31:0] flow_control_config;
reg[31:0] rs_config;
reg[31:0] mgmt_config;
 
/////////////////////////////////////////////
// Input registers
/////////////////////////////////////////////
 
reg[8:0] mgmt_addr_d1;
always@(posedge mgmt_clk or posedge reset)begin
      if(reset)
                  mgmt_addr_d1 <=#TP 0;
                else
                  mgmt_addr_d1 <=#TP mgmt_addr[8:0];
end
 
reg mdio_in_valid_d1;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                  mdio_in_valid_d1 <=#TP 1'b0;
                else
                  mdio_in_valid_d1 <=#TP mdio_in_valid;
end
 
/////////////////////////////////////////////
// State Machine
/////////////////////////////////////////////
reg[1:0] state;
reg read_done;
always@(posedge mgmt_clk or posedge reset)begin
    if (reset)
            state <=#TP IDLE;
         else begin
            case (state)
                    IDLE: begin
                             if(mgmt_req & mgmt_miim_sel) // MDIO Operations
                                    state <=#TP MDIO_OPERATE;
                                  else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9]) // Operations on Statistics registers 
                                    state <=#TP STAT_OPERATE;
                                  else if(~mgmt_miim_sel & mgmt_addr[9]) // Operations on Configuration registers
                                    state <=#TP CONFIG_OPERATE;
                                  else
                                    state <=#TP IDLE;
                         end
          MDIO_OPERATE: begin
              if(~mdio_in_valid & mdio_in_valid_d1) // MDIO read/write done
                state <=#TP IDLE;
              else
                state <=#TP MDIO_OPERATE;
          end
          STAT_OPERATE: begin
              if(read_done) // for statistics registers, only read operation happens 
                state <=#TP IDLE;
              else
                state <=#TP STAT_OPERATE;
          end
          CONFIG_OPERATE: begin
              if(mgmt_req & mgmt_miim_sel) //during operation on configuration registers, 
                                           //other request can be responsed. because such 
                                           //operations only take one cycle time.  
                state <=#TP MDIO_OPERATE
              else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])
                state <=#TP STAT_OPERATE;
              else if(~mgmt_miim_sel & mgmt_addr[9])
                state <=#TP CONFIG_OPERATE;
             else
                state <=#TP IDLE;
          end
      endcase
   end
end
 
/////////////////////////////////////////////
// Write Statistics Registers
/////////////////////////////////////////////
 
//--Receive Related
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_received_good <=#TP 1;
      else if(rxStatRegPlus[0])
         frame_received_good <=#TP frame_received_good + 1;
end // num of good frames have been received
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         fcs_error <=#TP 2;
      else if(rxStatRegPlus[1])
         fcs_error <=#TP fcs_error + 1;
end // num of frames that have failed in FCS checking
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         broadcast_received_good <=#TP 0;
      else if(rxStatRegPlus[2])
         broadcast_received_good <=#TP broadcast_received_good + 1;
end // num of broadcast frames that have been successfully received
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         multicast_received_good <=#TP 0;
      else if(rxStatRegPlus[3])
         multicast_received_good <=#TP multicast_received_good + 1;
end // num of multicast frames that have been successfully received
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_64_good <=#TP 0;
      else if(rxStatRegPlus[4])
         frame_64_good <=#TP frame_64_good + 1;
end //num of frames that have been successfully received, with length equal to 64
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_65_127_good <=#TP 0;
      else if(rxStatRegPlus[5])
         frame_65_127_good <=#TP frame_65_127_good + 1;
end //num of frames that have been successfully received, with length between 65 and 127
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_128_255_good <=#TP 0;
      else if(rxStatRegPlus[6])
         frame_128_255_good <=#TP frame_128_255_good + 1;
end //num of frames that have been successfully received, with length between 128 and 255
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_256_511_good <=#TP 0;
      else if(rxStatRegPlus[7])
         frame_256_511_good <=#TP frame_256_511_good + 1;
end //num of frames that have been successfully received, with length between 256 and 511
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_512_1023_good <=#TP 0;
      else if(rxStatRegPlus[8])
         frame_512_1023_good <=#TP frame_512_1023_good + 1;
end //num of frames that have been successfully received, with length between 512 and 1023
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_1024_max_good <=#TP 0;
      else if(rxStatRegPlus[9])
         frame_1024_max_good <=#TP frame_1024_max_good + 1;
end //num of frames that have been successfully received, with length between 1024 and max length
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              control_frame_good <=#TP 0;
           else if(rxStatRegPlus[10])
         control_frame_good <=#TP control_frame_good + 1;
end //num of control frames that have been successfully received
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              lt_out_range <=#TP 0;
           else if(rxStatRegPlus[11])
         lt_out_range <=#TP lt_out_range + 1;
end //num of frames whose length are too large
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              tagged_frame_good <=#TP 0;
           else if(rxStatRegPlus[12])
         tagged_frame_good <=#TP tagged_frame_good + 1;
end //num of tagged frames that have been successfully received
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              pause_frame_good <=#TP 0;
           else if(rxStatRegPlus[13])
         pause_frame_good <=#TP pause_frame_good + 1;
end //num of pause frames that have been successfully received
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              unsupported_control_frame <=#TP 0;
           else if(rxStatRegPlus[14])
         unsupported_control_frame <=#TP unsupported_control_frame + 1;
end //num of frames whose type filed haven't been defined in IEEE 802.3*
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              oversize_frame_good <=#TP 0;
           else if(rxStatRegPlus[15])
         oversize_frame_good <=#TP oversize_frame_good + 1;
end //num of frames which are good, only with large size
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              undersize_frame <=#TP 0;
           else if(rxStatRegPlus[16])
         undersize_frame <=#TP undersize_frame + 1;
end //num of frames whose length are too short
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              fragment_frame <=#TP 0;
           else if(rxStatRegPlus[17])
         fragment_frame <=#TP fragment_frame + 1;
end //num of fragment frames 
 
always@(posedge rxclk or posedge reset) begin
      if (reset)
              total_bytes_recved <=#TP 0;
           else if(rxStatRegPlus[18])
         total_bytes_recved <=#TP total_bytes_recved + 1;
end //bytes have been received
 
//--Transmit Related
always@(posedge txclk or posedge reset) begin
      if (reset)
              total_bytes_transed <=#TP 0;
           else if(txStatRegPlus[0])
         total_bytes_transed <=#TP total_bytes_transed + 1;
end //bytes have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              good_frame_transed <=#TP 0;
           else if(txStatRegPlus[1])
         good_frame_transed <=#TP good_frame_transed + 1;
end //num of error free frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              broadcast_frame_transed <=#TP 0;
           else if(txStatRegPlus[2])
         broadcast_frame_transed <=#TP broadcast_frame_transed + 1;
end //num of broadcast frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              multicast_frame_transed <=#TP 0;
           else if(txStatRegPlus[3])
         multicast_frame_transed <=#TP multicast_frame_transed + 1;
end //num of multicast frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              underrun_error <=#TP 0;
           else if(txStatRegPlus[4])
         underrun_error <=#TP underrun_error + 1;
end //num of underrun error frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              control_frame_transed <=#TP 0;
           else if(txStatRegPlus[5])
         control_frame_transed <=#TP control_frame_transed + 1;
end //num of control frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              frame_64_transed <=#TP 0;
           else if(txStatRegPlus[6])
         frame_64_transed <=#TP frame_64_transed + 1;
end //num of frames have been transmitted, with length equal 64
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              frame_65_127_transed <=#TP 0;
           else if(txStatRegPlus[7])
         frame_65_127_transed <=#TP frame_65_127_transed + 1;
end //num of frames have been transmitted, with length are between 65 and 127
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              frame_128_255_transed <=#TP 0;
           else if(txStatRegPlus[8])
         frame_128_255_transed <=#TP frame_128_255_transed + 1;
end //num of frames have been transmitted, with length are between 128 and 255
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              frame_256_511_transed <=#TP 0;
           else if(txStatRegPlus[9])
         frame_256_511_transed <=#TP frame_256_511_transed + 1;
end //num of frames have been transmitted, with length are between 256 and 511
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              frame_512_1023_transed <=#TP 0;
           else if(txStatRegPlus[10])
         frame_512_1023_transed <=#TP frame_512_1023_transed + 1;
end //num of frames have been transmitted, with length are between 512 and 1023
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              frame_1024_max_transed <=#TP 0;
           else if(txStatRegPlus[11])
         frame_1024_max_transed <=#TP frame_1024_max_transed + 1;
end //num of frames have been transmitted, with length are between 1024 and max length
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              tagged_frame_transed <=#TP 0;
           else if(txStatRegPlus[12])
         tagged_frame_transed <=#TP tagged_frame_transed + 1;
end //num of tagged frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              pause_frame_transed <=#TP 0;
           else if(txStatRegPlus[13])
         pause_frame_transed <=#TP pause_frame_transed + 1;
end //num of pause frames have been transmitted
 
always@(posedge txclk or posedge reset) begin
      if (reset)
              oversize_frame_transed <=#TP 0;
           else if(txStatRegPlus[14])
         oversize_frame_transed <=#TP oversize_frame_transed + 1;
end //num of frames whose length are larger than max length
 
/////////////////////////////////////////////
// Read Statistics Registers
/////////////////////////////////////////////
reg[63:0] stat_rd_data;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                  stat_rd_data <=#TP 0;
      else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])begin
                  case (mgmt_addr[7:0])
                      8'h00: stat_rd_data <= frame_received_good;
                      8'h01: stat_rd_data <= fcs_error;
                      8'h02: stat_rd_data <= broadcast_received_good;
                      8'h03: stat_rd_data <= multicast_received_good;
                      8'h04: stat_rd_data <= frame_64_good;
                      8'h05: stat_rd_data <= frame_65_127_good;
                      8'h06: stat_rd_data <= frame_128_255_good;
                      8'h07: stat_rd_data <= frame_256_511_good;
                      8'h08: stat_rd_data <= frame_512_1023_good;
                      8'h09: stat_rd_data <= frame_1024_max_good;
                      8'h0a: stat_rd_data <= control_frame_good;
                      8'h0b: stat_rd_data <= lt_out_range;
                      8'h0c: stat_rd_data <= tagged_frame_good;
                      8'h0d: stat_rd_data <= pause_frame_good;
                      8'h0e: stat_rd_data <= unsupported_control_frame;
                      8'h0f: stat_rd_data <= oversize_frame_good;
                      8'h10: stat_rd_data <= undersize_frame;
                      8'h11: stat_rd_data <= fragment_frame;
                      8'h12: stat_rd_data <= total_bytes_recved;
                      8'h13: stat_rd_data <= total_bytes_transed;
                      8'h20: stat_rd_data <= good_frame_transed;
                      8'h21: stat_rd_data <= broadcast_frame_transed;
                      8'h22: stat_rd_data <= multicast_frame_transed;
                      8'h23: stat_rd_data <= underrun_error;
                      8'h24: stat_rd_data <= control_frame_transed;
                      8'h25: stat_rd_data <= frame_64_transed;
                      8'h26: stat_rd_data <= frame_65_127_transed;
                      8'h27: stat_rd_data <= frame_128_255_transed;
                      8'h28: stat_rd_data <= frame_256_511_transed;
                      8'h29: stat_rd_data <= frame_512_1023_transed;
                      8'h2a: stat_rd_data <= frame_1024_max_transed;
                      8'h2b: stat_rd_data <= tagged_frame_transed;
                      8'h2c: stat_rd_data <= pause_frame_transed;
                      8'h2d: stat_rd_data <= oversize_frame_transed;
            default: stat_rd_data <= 0;
       endcase
    end
end
 
////////////////////////////////////////////////////////
// READ Statmachine
//
// Select which data to be writen to mgmt_rd_data
////////////////////////////////////////////////////////
reg[31:0] mgmt_rd_data;
reg mgmt_miim_rdy;
reg data_sel;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset) begin
         mgmt_rd_data <=#TP 0;
                        data_sel <=#TP 0; //0 select the lower 32bits of stat regs to mgmt_rd_data, while 1 select the higher 32bits
                        read_done <=#TP 0; // when asserted, it indicates read operation has been finished
                        mgmt_miim_rdy <=#TP 0;
                end
                else begin
         case (state)
                            IDLE: begin
                                     mgmt_rd_data <=#TP mgmt_rd_data;
                                     data_sel <=#TP 1'b0;
                                read_done <=#TP 0;
                                mgmt_miim_rdy <=#TP 1;
                                          if(mgmt_req & mgmt_miim_sel)
                                            mgmt_miim_rdy <=#TP 0;
                                 end
             STAT_OPERATE: begin // read statistics registers
                                     mgmt_miim_rdy <=#TP 1;
                                read_done <=#TP 1'b0;
                 if (~data_sel) begin
                                  mgmt_rd_data <=#TP stat_rd_data[31:0];
                                            data_sel <=#TP 1'b1;
                                          end
                                          else if(data_sel)begin
                                            mgmt_rd_data <=#TP stat_rd_data[63:32];
                                                 data_sel <=#TP 1'b0;
                                  read_done <=#TP 1'b1;
                                          end
                                 end
                                 CONFIG_OPERATE: begin // read configuration registers
                                     case (mgmt_addr_d1[8:4])
                                                5'h00: mgmt_rd_data <=#TP recv_config0;
                       5'h04: mgmt_rd_data <=#TP recv_config1;
                       5'h08: mgmt_rd_data <=#TP trans_config;
                       5'h0c: mgmt_rd_data <=#TP flow_control_config;
                       5'h10: mgmt_rd_data <=#TP rs_config;
                       5'h14: mgmt_rd_data <=#TP mgmt_config;
                                                          default: mgmt_rd_data <=#TP mgmt_rd_data;
                                          endcase
                                 end
             MDIO_OPERATE: begin // read/write MDIO registers
                                     if(~mdio_in_valid & mdio_in_valid_d1) begin
                    mgmt_rd_data[15:0] <=#TP mdio_data_in;
                                                  mgmt_rd_data[31:16] <=#TP 0;
                                                  mgmt_miim_rdy <=#TP 1'b1;
                                          end
                 else begin
                    mgmt_rd_data <=#TP mgmt_rd_data;
                                                  mgmt_miim_rdy <=#TP 1'b0;
                 end
             end
             default: begin
                 mgmt_rd_data <=#TP 0;
                                data_sel <=#TP 0;
                                read_done <=#TP 0;
                           mgmt_miim_rdy <=#TP 1;
             end
          endcase
      end
end
 
/////////////////////////////////////////////
// Write Configuration Registers
/////////////////////////////////////////////
reg[31:0] mgmt_wr_data_d1;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                   mgmt_wr_data_d1 <=#TP 0;
                else
                   mgmt_wr_data_d1 <=#TP mgmt_wr_data;
end
 
always@(posedge mgmt_clk or posedge reset)begin
      if(reset)begin
                  recv_config0 <=#TP 0;
        recv_config1 <=#TP 32'h10000000;
        trans_config <=#TP 32'h10000000;
        flow_control_config <=#TP 32'h60000000;
        rs_config <=#TP 0;
        mgmt_config <=#TP 32'h00100000;
                end
      else if(~mgmt_miim_sel & mgmt_addr[9]& ~mgmt_opcode[1]) begin // write configuration registers
        case (mgmt_addr[8:0])
          9'h000: recv_config0 <=#TP mgmt_wr_data;
          9'h040: recv_config1 <=#TP mgmt_wr_data;
          9'h080: trans_config <=#TP mgmt_wr_data;
          9'h0c0: flow_control_config <=#TP mgmt_wr_data;
          9'h100: rs_config <=#TP mgmt_wr_data;
          9'h140: mgmt_config <=#TP mgmt_wr_data;
                         default: begin
                           recv_config0 <=#TP recv_config0;
            recv_config1 <=#TP recv_config1;
            trans_config <=#TP trans_config;
            flow_control_config <=#TP flow_control_config;
            rs_config <=#TP rs_config;
            mgmt_config <=#TP mgmt_config;
                         end
        endcase
      end
end
 
///////////////////////////////////////////////////////
// Read Configuration Registers, 
// generates receive and transmit configuration vector
///////////////////////////////////////////////////////
 
assign cfgRxRegData = {recv_config1[31:27], recv_config1[15:0], recv_config0};
assign cfgTxRegData = {rs_config[27], trans_config[31:24],flow_control_config[30]};
 
///////////////////////////////////////////////
// Interface with MDIO module
// Generate control and data signals for MDIO
///////////////////////////////////////////////
reg[25:0] mdio_data_out; //output data, includes PHY address and data to be writen
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                   mdio_data_out <=#TP 0;
                else if(mgmt_req & mgmt_miim_sel)
                   mdio_data_out <=#TP {mgmt_addr[9:0], mgmt_wr_data[15:0]};
                else
                   mdio_data_out <=#TP mdio_data_out;
end
 
reg[1:0] mdio_opcode; //MDIO operation code, 2'b10 is read, while 2'b01 is write
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                  mdio_opcode <=#TP 0;
                else if(mgmt_req & mgmt_miim_sel)
                  mdio_opcode <=#TP mgmt_opcode;
end
 
reg[4:0] tmp_cnt; //used to longer the mdio_out_valid signal
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                   tmp_cnt <=#TP 0;
                else if(mgmt_req & mgmt_miim_sel)
                   tmp_cnt <=#TP 0;
                else if(tmp_cnt == 30)
                   tmp_cnt <=#TP tmp_cnt;
                else
                   tmp_cnt <=#TP tmp_cnt + 1;
end
 
reg mdio_out_valid; //indicates a MDIO request is valid, lasts for 31 cycles(mgmt_clk)
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
                        mdio_out_valid <=#TP 0;
                else if(mgmt_req & mgmt_miim_sel)
                   mdio_out_valid <=#TP 1'b1;
                else if(tmp_cnt ==30)
                   mdio_out_valid <=#TP 1'b0;
                else
         mdio_out_valid <= #TP mdio_out_valid;
end
 
endmodule

Line No.	Rev	Author	Line
1	59	fisher5090	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////`
3	70	fisher5090	`//// ////`
4			`//// MODULE NAME: manage_registers ////`
5			`//// ////`
6	59	fisher5090	`//// DESCRIPTION: implement read & write logic for configuration ////`
7			`//// and statistics registers ////`
8	70	fisher5090	`//// ////`
9	59	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
10	70	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
11			`//// ////`
12			`//// AUTHOR(S): ////`
13			`//// Zheng Cao ////`
14			`//// ////`
15	59	fisher5090	`//////////////////////////////////////////////////////////////////////`
16	70	fisher5090	`//// ////`
17			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
18			`//// ////`
19	59	fisher5090	`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38	70	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40	59	fisher5090	`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS REVISION HISTORY:`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	70	fisher5090	`// Revision 1.4 2006/06/15 12:12:27 fisher5090`
46			`// modify mgmt_miim_rdy timing sequence`
47			`//`
48	67	fisher5090	`// Revision 1.3 2006/06/15 08:25:42 fisher5090`
49			`// comments added`
50			`//`
51	66	fisher5090	`// Revision 1.2 2006/06/15 05:09:24 fisher5090`
52			`// bad coding style, but works, will be modified later`
53			`//`
54	59	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
55			`//`
56			`//`
57			`//`
58			`//////////////////////////////////////////////////////////////////////`
59			`module manage_registers(mgmt_clk, rxclk, txclk, reset, mgmt_opcode, mgmt_addr, mgmt_wr_data, mgmt_rd_data, mgmt_miim_sel, mgmt_req,`
60			`mgmt_miim_rdy, rxStatRegPlus, txStatRegPlus, cfgRxRegData, cfgTxRegData, mdio_opcode, mdio_data_out, mdio_data_in, mdio_in_valid,`
61			`mgmt_config, mdio_out_valid);`
62			`input mgmt_clk; //management clock`
63			`input rxclk; //receive clock`
64			`input txclk; //transmit clock`
65			`input reset; //system reset`
66			`input[1:0] mgmt_opcode; //management opcode(read/write/mdio)`
67			`input[9:0] mgmt_addr; //management address, including addresses of configuration, statistics and MDIO registers`
68			`input[31:0] mgmt_wr_data; //Data to be writen to Configuration/MDIO registers`
69			`output[31:0] mgmt_rd_data; //Data read from Configuration/Statistics/MDIO registers`
70			`input mgmt_miim_sel; //select internal register or MDIO registers`
71			`input mgmt_req; //Valid when operate statistics/MDIO registers, one clock valid____\|-\|____`
72			`output mgmt_miim_rdy; //Indicate the Management Module is in IDLE Status`
73			`input[18:0] rxStatRegPlus; //From Receive Module, one bit is related to one receive statistics register`
74			`input[14:0] txStatRegPlus; //From Transmit Module, one bit is related to one transmit statistics register`
75			`output[52:0] cfgRxRegData; //To Receive Module, config receive module`
76			`output[9:0] cfgTxRegData; //To Transmit Module, config transmit module`
77			`output[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode`
78			`output mdio_out_valid; //Indicate mdio_data_out is valid`
79	66	fisher5090	`output[25:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}`
80	65	fisher5090	`input[15:0] mdio_data_in; //Data read from MDIO`
81	59	fisher5090	`input mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid`
82			`output[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency`
83
84			`parameter IDLE =0, MDIO_OPERATE =1, STAT_OPERATE =2, CONFIG_OPERATE =3;`
85			`parameter TP = 1;`
86
87			`/////////////////////////////////////////////`
88			`// Statistics Register Definition`
89			`/////////////////////////////////////////////`
90
91			`//--Receive Related`
92			`reg[63:0] frame_received_good;`
93			`reg[63:0] fcs_error;`
94			`reg[63:0] broadcast_received_good;`
95			`reg[63:0] multicast_received_good;`
96			`reg[63:0] frame_64_good;`
97			`reg[63:0] frame_65_127_good;`
98			`reg[63:0] frame_128_255_good;`
99			`reg[63:0] frame_256_511_good;`
100			`reg[63:0] frame_512_1023_good;`
101			`reg[63:0] frame_1024_max_good;`
102			`reg[63:0] control_frame_good;`
103			`reg[63:0] lt_out_range;`
104			`reg[63:0] tagged_frame_good;`
105			`reg[63:0] pause_frame_good;`
106			`reg[63:0] unsupported_control_frame;`
107			`reg[63:0] oversize_frame_good;`
108			`reg[63:0] undersize_frame;`
109			`reg[63:0] fragment_frame;`
110			`reg[63:0] total_bytes_recved;`
111
112			`//--Transmit Related`
113			`reg[63:0] total_bytes_transed;`
114			`reg[63:0] good_frame_transed;`
115			`reg[63:0] broadcast_frame_transed;`
116			`reg[63:0] multicast_frame_transed;`
117			`reg[63:0] underrun_error;`
118			`reg[63:0] control_frame_transed;`
119			`reg[63:0] frame_64_transed;`
120			`reg[63:0] frame_65_127_transed;`
121			`reg[63:0] frame_128_255_transed;`
122			`reg[63:0] frame_256_511_transed;`
123			`reg[63:0] frame_512_1023_transed;`
124			`reg[63:0] frame_1024_max_transed;`
125			`reg[63:0] tagged_frame_transed;`
126			`reg[63:0] pause_frame_transed;`
127			`reg[63:0] oversize_frame_transed;`
128
129			`/////////////////////////////////////////////`
130			`// Configuration Registers Definition`
131			`/////////////////////////////////////////////`
132
133			`reg[31:0] recv_config0;`
134			`reg[31:0] recv_config1;`
135			`reg[31:0] trans_config;`
136			`reg[31:0] flow_control_config;`
137			`reg[31:0] rs_config;`
138			`reg[31:0] mgmt_config;`
139
140			`/////////////////////////////////////////////`
141			`// Input registers`
142			`/////////////////////////////////////////////`
143
144			`reg[8:0] mgmt_addr_d1;`
145			`always@(posedge mgmt_clk or posedge reset)begin`
146			`if(reset)`
147			`mgmt_addr_d1 <=#TP 0;`
148			`else`
149			`mgmt_addr_d1 <=#TP mgmt_addr[8:0];`
150			`end`
151
152			`reg mdio_in_valid_d1;`
153			`always@(posedge mgmt_clk or posedge reset) begin`
154			`if(reset)`
155			`mdio_in_valid_d1 <=#TP 1'b0;`
156			`else`
157			`mdio_in_valid_d1 <=#TP mdio_in_valid;`
158			`end`
159
160			`/////////////////////////////////////////////`
161			`// State Machine`
162			`/////////////////////////////////////////////`
163			`reg[1:0] state;`
164			`reg read_done;`
165			`always@(posedge mgmt_clk or posedge reset)begin`
166			`if (reset)`
167			`state <=#TP IDLE;`
168			`else begin`
169			`case (state)`
170			`IDLE: begin`
171	66	fisher5090	`if(mgmt_req & mgmt_miim_sel) // MDIO Operations`
172	59	fisher5090	`state <=#TP MDIO_OPERATE;`
173	66	fisher5090	`else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9]) // Operations on Statistics registers`
174	59	fisher5090	`state <=#TP STAT_OPERATE;`
175	66	fisher5090	`else if(~mgmt_miim_sel & mgmt_addr[9]) // Operations on Configuration registers`
176	59	fisher5090	`state <=#TP CONFIG_OPERATE;`
177			`else`
178			`state <=#TP IDLE;`
179			`end`
180			`MDIO_OPERATE: begin`
181	66	fisher5090	`if(~mdio_in_valid & mdio_in_valid_d1) // MDIO read/write done`
182	59	fisher5090	`state <=#TP IDLE;`
183			`else`
184			`state <=#TP MDIO_OPERATE;`
185			`end`
186	66	fisher5090	`STAT_OPERATE: begin`
187			`if(read_done) // for statistics registers, only read operation happens`
188	59	fisher5090	`state <=#TP IDLE;`
189			`else`
190			`state <=#TP STAT_OPERATE;`
191			`end`
192			`CONFIG_OPERATE: begin`
193	66	fisher5090	`if(mgmt_req & mgmt_miim_sel) //during operation on configuration registers,`
194	70	fisher5090	`//other request can be responsed. because such`
195			`//operations only take one cycle time.`
196			`state <=#TP MDIO_OPERATE`
197			`else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])`
198			`state <=#TP STAT_OPERATE;`
199			`else if(~mgmt_miim_sel & mgmt_addr[9])`
200			`state <=#TP CONFIG_OPERATE;`
201			`else`
202			`state <=#TP IDLE;`
203	59	fisher5090	`end`
204			`endcase`
205			`end`
206			`end`
207
208			`/////////////////////////////////////////////`
209			`// Write Statistics Registers`
210			`/////////////////////////////////////////////`
211
212			`//--Receive Related`
213			`always@(posedge rxclk or posedge reset) begin`
214			`if (reset)`
215	70	fisher5090	`frame_received_good <=#TP 1;`
216			`else if(rxStatRegPlus[0])`
217	59	fisher5090	`frame_received_good <=#TP frame_received_good + 1;`
218	66	fisher5090	`end // num of good frames have been received`
219	59	fisher5090
220			`always@(posedge rxclk or posedge reset) begin`
221			`if (reset)`
222	70	fisher5090	`fcs_error <=#TP 2;`
223			`else if(rxStatRegPlus[1])`
224	59	fisher5090	`fcs_error <=#TP fcs_error + 1;`
225	66	fisher5090	`end // num of frames that have failed in FCS checking`
226	59	fisher5090
227			`always@(posedge rxclk or posedge reset) begin`
228			`if (reset)`
229	70	fisher5090	`broadcast_received_good <=#TP 0;`
230			`else if(rxStatRegPlus[2])`
231	59	fisher5090	`broadcast_received_good <=#TP broadcast_received_good + 1;`
232	66	fisher5090	`end // num of broadcast frames that have been successfully received`
233	59	fisher5090
234			`always@(posedge rxclk or posedge reset) begin`
235			`if (reset)`
236	70	fisher5090	`multicast_received_good <=#TP 0;`
237			`else if(rxStatRegPlus[3])`
238	59	fisher5090	`multicast_received_good <=#TP multicast_received_good + 1;`
239	66	fisher5090	`end // num of multicast frames that have been successfully received`
240	59	fisher5090
241			`always@(posedge rxclk or posedge reset) begin`
242			`if (reset)`
243	70	fisher5090	`frame_64_good <=#TP 0;`
244			`else if(rxStatRegPlus[4])`
245	59	fisher5090	`frame_64_good <=#TP frame_64_good + 1;`
246	66	fisher5090	`end //num of frames that have been successfully received, with length equal to 64`
247	59	fisher5090
248			`always@(posedge rxclk or posedge reset) begin`
249			`if (reset)`
250	70	fisher5090	`frame_65_127_good <=#TP 0;`
251			`else if(rxStatRegPlus[5])`
252	59	fisher5090	`frame_65_127_good <=#TP frame_65_127_good + 1;`
253	66	fisher5090	`end //num of frames that have been successfully received, with length between 65 and 127`
254	59	fisher5090
255			`always@(posedge rxclk or posedge reset) begin`
256			`if (reset)`
257	70	fisher5090	`frame_128_255_good <=#TP 0;`
258			`else if(rxStatRegPlus[6])`
259	59	fisher5090	`frame_128_255_good <=#TP frame_128_255_good + 1;`
260	66	fisher5090	`end //num of frames that have been successfully received, with length between 128 and 255`
261	59	fisher5090
262			`always@(posedge rxclk or posedge reset) begin`
263			`if (reset)`
264	70	fisher5090	`frame_256_511_good <=#TP 0;`
265			`else if(rxStatRegPlus[7])`
266	59	fisher5090	`frame_256_511_good <=#TP frame_256_511_good + 1;`
267	66	fisher5090	`end //num of frames that have been successfully received, with length between 256 and 511`
268	59	fisher5090
269			`always@(posedge rxclk or posedge reset) begin`
270			`if (reset)`
271	70	fisher5090	`frame_512_1023_good <=#TP 0;`
272			`else if(rxStatRegPlus[8])`
273	59	fisher5090	`frame_512_1023_good <=#TP frame_512_1023_good + 1;`
274	66	fisher5090	`end //num of frames that have been successfully received, with length between 512 and 1023`
275	59	fisher5090
276			`always@(posedge rxclk or posedge reset) begin`
277			`if (reset)`
278	70	fisher5090	`frame_1024_max_good <=#TP 0;`
279			`else if(rxStatRegPlus[9])`
280	59	fisher5090	`frame_1024_max_good <=#TP frame_1024_max_good + 1;`
281	66	fisher5090	`end //num of frames that have been successfully received, with length between 1024 and max length`
282	59	fisher5090
283			`always@(posedge rxclk or posedge reset) begin`
284			`if (reset)`
285			`control_frame_good <=#TP 0;`
286			`else if(rxStatRegPlus[10])`
287			`control_frame_good <=#TP control_frame_good + 1;`
288	66	fisher5090	`end //num of control frames that have been successfully received`
289	59	fisher5090
290			`always@(posedge rxclk or posedge reset) begin`
291			`if (reset)`
292			`lt_out_range <=#TP 0;`
293			`else if(rxStatRegPlus[11])`
294			`lt_out_range <=#TP lt_out_range + 1;`
295	66	fisher5090	`end //num of frames whose length are too large`
296	59	fisher5090
297			`always@(posedge rxclk or posedge reset) begin`
298			`if (reset)`
299			`tagged_frame_good <=#TP 0;`
300			`else if(rxStatRegPlus[12])`
301			`tagged_frame_good <=#TP tagged_frame_good + 1;`
302	66	fisher5090	`end //num of tagged frames that have been successfully received`
303	59	fisher5090
304			`always@(posedge rxclk or posedge reset) begin`
305			`if (reset)`
306			`pause_frame_good <=#TP 0;`
307			`else if(rxStatRegPlus[13])`
308			`pause_frame_good <=#TP pause_frame_good + 1;`
309	66	fisher5090	`end //num of pause frames that have been successfully received`
310	59	fisher5090
311			`always@(posedge rxclk or posedge reset) begin`
312			`if (reset)`
313			`unsupported_control_frame <=#TP 0;`
314			`else if(rxStatRegPlus[14])`
315			`unsupported_control_frame <=#TP unsupported_control_frame + 1;`
316	66	fisher5090	`end //num of frames whose type filed haven't been defined in IEEE 802.3*`
317	59	fisher5090
318			`always@(posedge rxclk or posedge reset) begin`
319			`if (reset)`
320			`oversize_frame_good <=#TP 0;`
321			`else if(rxStatRegPlus[15])`
322			`oversize_frame_good <=#TP oversize_frame_good + 1;`
323	66	fisher5090	`end //num of frames which are good, only with large size`
324	59	fisher5090
325			`always@(posedge rxclk or posedge reset) begin`
326			`if (reset)`
327			`undersize_frame <=#TP 0;`
328			`else if(rxStatRegPlus[16])`
329			`undersize_frame <=#TP undersize_frame + 1;`
330	66	fisher5090	`end //num of frames whose length are too short`
331	59	fisher5090
332			`always@(posedge rxclk or posedge reset) begin`
333			`if (reset)`
334			`fragment_frame <=#TP 0;`
335			`else if(rxStatRegPlus[17])`
336			`fragment_frame <=#TP fragment_frame + 1;`
337	66	fisher5090	`end //num of fragment frames`
338	59	fisher5090
339			`always@(posedge rxclk or posedge reset) begin`
340			`if (reset)`
341			`total_bytes_recved <=#TP 0;`
342			`else if(rxStatRegPlus[18])`
343			`total_bytes_recved <=#TP total_bytes_recved + 1;`
344	66	fisher5090	`end //bytes have been received`
345	59	fisher5090
346			`//--Transmit Related`
347			`always@(posedge txclk or posedge reset) begin`
348			`if (reset)`
349			`total_bytes_transed <=#TP 0;`
350			`else if(txStatRegPlus[0])`
351			`total_bytes_transed <=#TP total_bytes_transed + 1;`
352	66	fisher5090	`end //bytes have been transmitted`
353	59	fisher5090
354			`always@(posedge txclk or posedge reset) begin`
355			`if (reset)`
356			`good_frame_transed <=#TP 0;`
357			`else if(txStatRegPlus[1])`
358			`good_frame_transed <=#TP good_frame_transed + 1;`
359	66	fisher5090	`end //num of error free frames have been transmitted`
360	59	fisher5090
361			`always@(posedge txclk or posedge reset) begin`
362			`if (reset)`
363			`broadcast_frame_transed <=#TP 0;`
364			`else if(txStatRegPlus[2])`
365			`broadcast_frame_transed <=#TP broadcast_frame_transed + 1;`
366	66	fisher5090	`end //num of broadcast frames have been transmitted`
367	59	fisher5090
368			`always@(posedge txclk or posedge reset) begin`
369			`if (reset)`
370			`multicast_frame_transed <=#TP 0;`
371			`else if(txStatRegPlus[3])`
372			`multicast_frame_transed <=#TP multicast_frame_transed + 1;`
373	66	fisher5090	`end //num of multicast frames have been transmitted`
374	59	fisher5090
375			`always@(posedge txclk or posedge reset) begin`
376			`if (reset)`
377			`underrun_error <=#TP 0;`
378			`else if(txStatRegPlus[4])`
379			`underrun_error <=#TP underrun_error + 1;`
380	66	fisher5090	`end //num of underrun error frames have been transmitted`
381	59	fisher5090
382			`always@(posedge txclk or posedge reset) begin`
383			`if (reset)`
384			`control_frame_transed <=#TP 0;`
385			`else if(txStatRegPlus[5])`
386			`control_frame_transed <=#TP control_frame_transed + 1;`
387	66	fisher5090	`end //num of control frames have been transmitted`
388	59	fisher5090
389			`always@(posedge txclk or posedge reset) begin`
390			`if (reset)`
391			`frame_64_transed <=#TP 0;`
392			`else if(txStatRegPlus[6])`
393			`frame_64_transed <=#TP frame_64_transed + 1;`
394	66	fisher5090	`end //num of frames have been transmitted, with length equal 64`
395	59	fisher5090
396			`always@(posedge txclk or posedge reset) begin`
397			`if (reset)`
398			`frame_65_127_transed <=#TP 0;`
399			`else if(txStatRegPlus[7])`
400			`frame_65_127_transed <=#TP frame_65_127_transed + 1;`
401	66	fisher5090	`end //num of frames have been transmitted, with length are between 65 and 127`
402	59	fisher5090
403			`always@(posedge txclk or posedge reset) begin`
404			`if (reset)`
405			`frame_128_255_transed <=#TP 0;`
406			`else if(txStatRegPlus[8])`
407			`frame_128_255_transed <=#TP frame_128_255_transed + 1;`
408	66	fisher5090	`end //num of frames have been transmitted, with length are between 128 and 255`
409	59	fisher5090
410			`always@(posedge txclk or posedge reset) begin`
411			`if (reset)`
412			`frame_256_511_transed <=#TP 0;`
413			`else if(txStatRegPlus[9])`
414			`frame_256_511_transed <=#TP frame_256_511_transed + 1;`
415	66	fisher5090	`end //num of frames have been transmitted, with length are between 256 and 511`
416	59	fisher5090
417			`always@(posedge txclk or posedge reset) begin`
418			`if (reset)`
419			`frame_512_1023_transed <=#TP 0;`
420			`else if(txStatRegPlus[10])`
421			`frame_512_1023_transed <=#TP frame_512_1023_transed + 1;`
422	66	fisher5090	`end //num of frames have been transmitted, with length are between 512 and 1023`
423	59	fisher5090
424			`always@(posedge txclk or posedge reset) begin`
425			`if (reset)`
426			`frame_1024_max_transed <=#TP 0;`
427			`else if(txStatRegPlus[11])`
428			`frame_1024_max_transed <=#TP frame_1024_max_transed + 1;`
429	66	fisher5090	`end //num of frames have been transmitted, with length are between 1024 and max length`
430	59	fisher5090
431			`always@(posedge txclk or posedge reset) begin`
432			`if (reset)`
433			`tagged_frame_transed <=#TP 0;`
434			`else if(txStatRegPlus[12])`
435			`tagged_frame_transed <=#TP tagged_frame_transed + 1;`
436	66	fisher5090	`end //num of tagged frames have been transmitted`
437	59	fisher5090
438			`always@(posedge txclk or posedge reset) begin`
439			`if (reset)`
440			`pause_frame_transed <=#TP 0;`
441			`else if(txStatRegPlus[13])`
442			`pause_frame_transed <=#TP pause_frame_transed + 1;`
443	66	fisher5090	`end //num of pause frames have been transmitted`
444	59	fisher5090
445			`always@(posedge txclk or posedge reset) begin`
446			`if (reset)`
447			`oversize_frame_transed <=#TP 0;`
448			`else if(txStatRegPlus[14])`
449			`oversize_frame_transed <=#TP oversize_frame_transed + 1;`
450	66	fisher5090	`end //num of frames whose length are larger than max length`
451	59	fisher5090
452			`/////////////////////////////////////////////`
453			`// Read Statistics Registers`
454			`/////////////////////////////////////////////`
455			`reg[63:0] stat_rd_data;`
456			`always@(posedge mgmt_clk or posedge reset) begin`
457			`if(reset)`
458			`stat_rd_data <=#TP 0;`
459			`else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])begin`
460			`case (mgmt_addr[7:0])`
461			`8'h00: stat_rd_data <= frame_received_good;`
462			`8'h01: stat_rd_data <= fcs_error;`
463			`8'h02: stat_rd_data <= broadcast_received_good;`
464			`8'h03: stat_rd_data <= multicast_received_good;`
465			`8'h04: stat_rd_data <= frame_64_good;`
466			`8'h05: stat_rd_data <= frame_65_127_good;`
467			`8'h06: stat_rd_data <= frame_128_255_good;`
468			`8'h07: stat_rd_data <= frame_256_511_good;`
469			`8'h08: stat_rd_data <= frame_512_1023_good;`
470			`8'h09: stat_rd_data <= frame_1024_max_good;`
471			`8'h0a: stat_rd_data <= control_frame_good;`
472			`8'h0b: stat_rd_data <= lt_out_range;`
473			`8'h0c: stat_rd_data <= tagged_frame_good;`
474			`8'h0d: stat_rd_data <= pause_frame_good;`
475			`8'h0e: stat_rd_data <= unsupported_control_frame;`
476			`8'h0f: stat_rd_data <= oversize_frame_good;`
477			`8'h10: stat_rd_data <= undersize_frame;`
478			`8'h11: stat_rd_data <= fragment_frame;`
479			`8'h12: stat_rd_data <= total_bytes_recved;`
480			`8'h13: stat_rd_data <= total_bytes_transed;`
481			`8'h20: stat_rd_data <= good_frame_transed;`
482			`8'h21: stat_rd_data <= broadcast_frame_transed;`
483			`8'h22: stat_rd_data <= multicast_frame_transed;`
484			`8'h23: stat_rd_data <= underrun_error;`
485			`8'h24: stat_rd_data <= control_frame_transed;`
486			`8'h25: stat_rd_data <= frame_64_transed;`
487			`8'h26: stat_rd_data <= frame_65_127_transed;`
488			`8'h27: stat_rd_data <= frame_128_255_transed;`
489			`8'h28: stat_rd_data <= frame_256_511_transed;`
490			`8'h29: stat_rd_data <= frame_512_1023_transed;`
491			`8'h2a: stat_rd_data <= frame_1024_max_transed;`
492			`8'h2b: stat_rd_data <= tagged_frame_transed;`
493			`8'h2c: stat_rd_data <= pause_frame_transed;`
494			`8'h2d: stat_rd_data <= oversize_frame_transed;`
495			`default: stat_rd_data <= 0;`
496			`endcase`
497			`end`
498			`end`
499
500			`////////////////////////////////////////////////////////`

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