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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [mgmt/] [mdio.v] - Blame information for rev 72

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// MODULE NAME: MDIO Interface                                                                                        ////
////                                                                                                                                                                    ////
//// DESCRIPTION: Generate MDIO Signals                           ////
////                                                                                                                                                                    ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                                              ////
////                                                                                                                                                                    ////
//// AUTHOR(S):                                                                                                                                 ////
//// Zheng Cao                                                               ////
////                                                                                                    ////
//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////
////                                                                                                                                                                    ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                                                   ////
////                                                                                                                                                                    ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2006/06/15 05:09:24  fisher5090
// bad coding style, but works, will be modified later
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`define PRE 31'h7fffffff
`define ST 2'b01
`define TA 2'b10
 
module mdio(mgmt_clk, reset, mdc, mdio_t, mdio_i, mdio_o, mdio_opcode, mdio_in_valid, mdio_data_in, mdio_out_valid, mdio_data_out, mgmt_config);
 
input mgmt_clk; //Management Clock
input reset; //System reset
output mdc; //MDIO clock
output mdio_t;
output mdio_o;
input mdio_i;
input[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode
output mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid
output[15:0] mdio_data_in; //Data read from MDIO
input mdio_out_valid; //Indicate mdio_data_out is valid
input[25:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}
input[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency
 
parameter IDLE =0, MDIO_WRITE =1, MDIO_READ =2;
parameter TP =1;
 
///////////////////////////////////////////
// MDIO Clock Gen
///////////////////////////////////////////
reg[4:0] clk_cnt;
always@(posedge mgmt_clk or posedge reset)begin
      if(reset)
                  clk_cnt <=#TP 0;
                else if(clk_cnt == mgmt_config[4:0])
                  clk_cnt <=#TP 0;
                else
                  clk_cnt <=#TP clk_cnt + 1;
end
 
reg mdc;
always@(posedge mgmt_clk or posedge reset)begin
      if(reset)
                  mdc <=#TP 0;
                else if(clk_cnt == mgmt_config[4:0])
                  mdc <=#TP ~mdc;
                else
        mdc <=#TP mdc;
end
 
////////////////////////////////////////////
// MDIO data initialization
////////////////////////////////////////////
reg transmitting;
reg[62:0] mdio_data;
 
always@(posedge mgmt_clk or posedge reset)begin
      if(reset)begin
                  mdio_data <=#TP 0;
                end
                else if(mdio_out_valid)begin
                  mdio_data <=#TP {`PRE, `ST, mdio_opcode, mdio_data_out[25:16], `TA, mdio_data_out[15:0]};
                end
end
 
reg[62:0] mdio_data_reg;
always@(posedge mdc or posedge reset)begin
      if(reset)
                  mdio_data_reg <=#TP 0;
                else if(transmitting)
                  mdio_data_reg <=#TP mdio_data_reg <<1;
                else
                  mdio_data_reg <=#TP mdio_data;
end
 
////////////////////////////////////////////
// counter used for transmitting data
////////////////////////////////////////////
 
reg[6:0] trans_cnt;
always@(posedge mdc or posedge reset)begin
      if(reset)begin
                  trans_cnt <=#TP 0;
                end
                else if(transmitting)begin
                  trans_cnt <=#TP trans_cnt + 1;
                end
                else begin
                  trans_cnt <=#TP 0;
                end
end
 
////////////////////////////////////////////
// MDIO SIGNAL DRIVER
////////////////////////////////////////////
wire mdio_operate_done; //indicates MDIO write/read operation has been finished
assign mdio_operate_done = (trans_cnt == 63);
 
reg receiving;
reg[1:0] state, nextstate;
always@(state, mdio_out_valid, mdio_opcode[1], mdio_operate_done, reset)begin
      if(reset)
                  nextstate <=#TP IDLE;
                else
                  case(state)
                     IDLE: begin
                             if(mdio_out_valid & ~mdio_opcode[1])
                 nextstate <=#TP MDIO_WRITE;
              else if(mdio_out_valid & mdio_opcode[1])
                 nextstate <=#TP MDIO_READ;
                                  else
                                     nextstate <=#TP nextstate;
                     end
                          MDIO_WRITE: begin
              if(mdio_operate_done)
                          nextstate <=#TP IDLE;
                        else
                nextstate <=#TP MDIO_WRITE;
                          end
           MDIO_READ: begin
              if(mdio_operate_done)
                          nextstate <=#TP IDLE;
                        else
                nextstate <=#TP MDIO_READ;
                          end
                 endcase
end
 
always@(posedge mdc or posedge reset)begin
      if(reset)
                  state <=#TP IDLE;
                else
        state <=#TP nextstate;
end
 
////////////////////////////////////////////////////
// MDIO control
//--receiving indicates receiving data from PHY
//--transmitting indicates transmitting data to PHY
////////////////////////////////////////////////////
 
reg mdio_o;
reg mdio_t;
always@(posedge mdc or posedge reset)begin
      if(reset) begin
        mdio_o <=#TP 0;
        mdio_t <=#TP 0;
                  transmitting <=#TP 0;
                  receiving <=#TP 0;
      end
      else begin
        case (state)
            IDLE:begin
               mdio_o <=#TP 1'b1;
               mdio_t <=#TP 0;
                         receiving <=#TP 0;
               transmitting <=#TP 0;
            end
                                MDIO_WRITE:begin
                                   transmitting <=#TP 1;
                                        mdio_o <=#TP mdio_data_reg[62];
                                        mdio_t <=#TP 1'b0;
                         receiving <=#TP 0;
                                        if (trans_cnt == 63)begin
                  transmitting <=#TP 0;
               end
                           end
            MDIO_READ:begin
                                        mdio_o <=#TP mdio_data_reg[62];
                                        mdio_t <=#TP 1'b0;
                                   transmitting <=#TP 1'b1;
                         receiving <=#TP 0;
               if (trans_cnt == 45)begin //transmitting TA
                                          mdio_t <=#TP 1'b1;
                                        end
                                        else if (trans_cnt == 63)begin //all data received
                                     transmitting <=#TP 1'b0;
                                          mdio_o <=#TP 1'b1;
                                        end
               else if(trans_cnt >= 46)begin //receiving Data
                                          mdio_t <=#TP 1'b1;
                 receiving <=#TP 1'b1;
                                        end
                           end
        endcase
    end
end
 
/////////////////////////////////////////////////
// Shift Registers to get data from PHY
/////////////////////////////////////////////////
reg mdio_in_valid;
always@(posedge mdc or posedge reset)begin
      if(reset)
                   mdio_in_valid <=#TP 1'b0;
      else if(mdio_operate_done)
         mdio_in_valid <=#TP 1'b1;
                else if(receiving)
                   mdio_in_valid <=#TP 1'b0;
      else
         mdio_in_valid <=#TP 1'b0;
end
 
reg[15:0] mdio_data_in;
always@(posedge mdc or posedge reset)begin
      if(reset)begin
                   mdio_data_in <=#TP 0;
                end
                else if(receiving)begin
                   mdio_data_in[0] <=#TP mdio_i;
                   mdio_data_in[1] <=#TP mdio_data_in[0];
                   mdio_data_in[2] <=#TP mdio_data_in[1];
                   mdio_data_in[3] <=#TP mdio_data_in[2];
                   mdio_data_in[4] <=#TP mdio_data_in[3];
                   mdio_data_in[5] <=#TP mdio_data_in[4];
                   mdio_data_in[6] <=#TP mdio_data_in[5];
                   mdio_data_in[7] <=#TP mdio_data_in[6];
                   mdio_data_in[8] <=#TP mdio_data_in[7];
                   mdio_data_in[9] <=#TP mdio_data_in[8];
                   mdio_data_in[10] <=#TP mdio_data_in[9];
                   mdio_data_in[11] <=#TP mdio_data_in[10];
                   mdio_data_in[12] <=#TP mdio_data_in[11];
                   mdio_data_in[13] <=#TP mdio_data_in[12];
                   mdio_data_in[14] <=#TP mdio_data_in[13];
                   mdio_data_in[15] <=#TP mdio_data_in[14];
           end
                else
                   mdio_data_in <=#TP mdio_data_in;
end
 
endmodule

Line No.	Rev	Author	Line
1	59	fisher5090	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// MODULE NAME: MDIO Interface ////`
5			`//// ////`
6			`//// DESCRIPTION: Generate MDIO Signals ////`
7			`//// ////`
8			`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
9			`//// http://www.opencores.org/projects/ethmac10g/ ////`
10			`//// ////`
11			`//// AUTHOR(S): ////`
12			`//// Zheng Cao ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS REVISION HISTORY:`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	66	fisher5090	`// Revision 1.2 2006/06/15 05:09:24 fisher5090`
45			`// bad coding style, but works, will be modified later`
46			`//`
47	59	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
48			`//`
49			`//`
50			`//`
51			`//////////////////////////////////////////////////////////////////////`
52
53			`define PRE 31'h7fffffff
54	65	fisher5090	`define ST 2'b01
55	59	fisher5090	`define TA 2'b10
56
57			`module mdio(mgmt_clk, reset, mdc, mdio_t, mdio_i, mdio_o, mdio_opcode, mdio_in_valid, mdio_data_in, mdio_out_valid, mdio_data_out, mgmt_config);`
58
59			`input mgmt_clk; //Management Clock`
60			`input reset; //System reset`
61			`output mdc; //MDIO clock`
62			`output mdio_t;`
63			`output mdio_o;`
64			`input mdio_i;`
65			`input[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode`
66			`output mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid`
67			`output[15:0] mdio_data_in; //Data read from MDIO`
68			`input mdio_out_valid; //Indicate mdio_data_out is valid`
69	66	fisher5090	`input[25:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}`
70	59	fisher5090	`input[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency`
71
72			`parameter IDLE =0, MDIO_WRITE =1, MDIO_READ =2;`
73			`parameter TP =1;`
74
75			`///////////////////////////////////////////`
76			`// MDIO Clock Gen`
77			`///////////////////////////////////////////`
78			`reg[4:0] clk_cnt;`
79			`always@(posedge mgmt_clk or posedge reset)begin`
80			`if(reset)`
81			`clk_cnt <=#TP 0;`
82			`else if(clk_cnt == mgmt_config[4:0])`
83			`clk_cnt <=#TP 0;`
84			`else`
85			`clk_cnt <=#TP clk_cnt + 1;`
86			`end`
87
88			`reg mdc;`
89			`always@(posedge mgmt_clk or posedge reset)begin`
90			`if(reset)`
91			`mdc <=#TP 0;`
92			`else if(clk_cnt == mgmt_config[4:0])`
93			`mdc <=#TP ~mdc;`
94			`else`
95			`mdc <=#TP mdc;`
96			`end`
97
98			`////////////////////////////////////////////`
99			`// MDIO data initialization`
100			`////////////////////////////////////////////`
101			`reg transmitting;`
102			`reg[62:0] mdio_data;`
103
104			`always@(posedge mgmt_clk or posedge reset)begin`
105			`if(reset)begin`
106			`mdio_data <=#TP 0;`
107			`end`
108			`else if(mdio_out_valid)begin`
109	66	fisher5090	mdio_data <=#TP {`PRE, `ST, mdio_opcode, mdio_data_out[25:16], `TA, mdio_data_out[15:0]};
110	59	fisher5090	`end`
111			`end`
112
113			`reg[62:0] mdio_data_reg;`
114			`always@(posedge mdc or posedge reset)begin`
115			`if(reset)`
116			`mdio_data_reg <=#TP 0;`
117			`else if(transmitting)`
118			`mdio_data_reg <=#TP mdio_data_reg <<1;`
119			`else`
120			`mdio_data_reg <=#TP mdio_data;`
121			`end`
122
123			`////////////////////////////////////////////`
124			`// counter used for transmitting data`
125			`////////////////////////////////////////////`
126
127			`reg[6:0] trans_cnt;`
128			`always@(posedge mdc or posedge reset)begin`
129			`if(reset)begin`
130			`trans_cnt <=#TP 0;`
131			`end`
132			`else if(transmitting)begin`
133			`trans_cnt <=#TP trans_cnt + 1;`
134			`end`
135			`else begin`
136			`trans_cnt <=#TP 0;`
137			`end`
138			`end`
139
140			`////////////////////////////////////////////`
141			`// MDIO SIGNAL DRIVER`
142			`////////////////////////////////////////////`
143			`wire mdio_operate_done; //indicates MDIO write/read operation has been finished`
144			`assign mdio_operate_done = (trans_cnt == 63);`
145
146			`reg receiving;`
147			`reg[1:0] state, nextstate;`
148			`always@(state, mdio_out_valid, mdio_opcode[1], mdio_operate_done, reset)begin`
149			`if(reset)`
150			`nextstate <=#TP IDLE;`
151			`else`
152			`case(state)`
153			`IDLE: begin`
154			`if(mdio_out_valid & ~mdio_opcode[1])`
155			`nextstate <=#TP MDIO_WRITE;`
156			`else if(mdio_out_valid & mdio_opcode[1])`
157			`nextstate <=#TP MDIO_READ;`
158			`else`
159			`nextstate <=#TP nextstate;`
160			`end`
161			`MDIO_WRITE: begin`
162			`if(mdio_operate_done)`
163			`nextstate <=#TP IDLE;`
164			`else`
165			`nextstate <=#TP MDIO_WRITE;`
166			`end`
167			`MDIO_READ: begin`
168			`if(mdio_operate_done)`
169			`nextstate <=#TP IDLE;`
170			`else`
171			`nextstate <=#TP MDIO_READ;`
172			`end`
173			`endcase`
174			`end`
175
176			`always@(posedge mdc or posedge reset)begin`
177			`if(reset)`
178			`state <=#TP IDLE;`
179			`else`
180			`state <=#TP nextstate;`
181			`end`
182
183			`////////////////////////////////////////////////////`
184			`// MDIO control`
185			`//--receiving indicates receiving data from PHY`
186			`//--transmitting indicates transmitting data to PHY`
187			`////////////////////////////////////////////////////`
188
189			`reg mdio_o;`
190			`reg mdio_t;`
191			`always@(posedge mdc or posedge reset)begin`
192			`if(reset) begin`
193			`mdio_o <=#TP 0;`
194	65	fisher5090	`mdio_t <=#TP 0;`
195	59	fisher5090	`transmitting <=#TP 0;`
196			`receiving <=#TP 0;`
197			`end`
198			`else begin`
199			`case (state)`
200			`IDLE:begin`
201	65	fisher5090	`mdio_o <=#TP 1'b1;`
202			`mdio_t <=#TP 0;`
203	59	fisher5090	`receiving <=#TP 0;`
204			`transmitting <=#TP 0;`
205			`end`
206			`MDIO_WRITE:begin`
207			`transmitting <=#TP 1;`
208			`mdio_o <=#TP mdio_data_reg[62];`
209			`mdio_t <=#TP 1'b0;`
210			`receiving <=#TP 0;`
211			`if (trans_cnt == 63)begin`
212	66	fisher5090	`transmitting <=#TP 0;`
213	59	fisher5090	`end`
214			`end`
215			`MDIO_READ:begin`
216			`mdio_o <=#TP mdio_data_reg[62];`
217	65	fisher5090	`mdio_t <=#TP 1'b0;`
218	59	fisher5090	`transmitting <=#TP 1'b1;`
219	65	fisher5090	`receiving <=#TP 0;`
220	66	fisher5090	`if (trans_cnt == 45)begin //transmitting TA`
221	59	fisher5090	`mdio_t <=#TP 1'b1;`
222	66	fisher5090	`end`
223	59	fisher5090	`else if (trans_cnt == 63)begin //all data received`
224	65	fisher5090	`transmitting <=#TP 1'b0;`
225			`mdio_o <=#TP 1'b1;`
226	59	fisher5090	`end`
227			`else if(trans_cnt >= 46)begin //receiving Data`
228	65	fisher5090	`mdio_t <=#TP 1'b1;`
229	59	fisher5090	`receiving <=#TP 1'b1;`
230			`end`
231			`end`
232			`endcase`
233			`end`
234			`end`
235
236			`/////////////////////////////////////////////////`
237			`// Shift Registers to get data from PHY`
238			`/////////////////////////////////////////////////`
239			`reg mdio_in_valid;`
240			`always@(posedge mdc or posedge reset)begin`
241			`if(reset)`
242			`mdio_in_valid <=#TP 1'b0;`
243			`else if(mdio_operate_done)`
244			`mdio_in_valid <=#TP 1'b1;`
245			`else if(receiving)`
246			`mdio_in_valid <=#TP 1'b0;`
247			`else`
248			`mdio_in_valid <=#TP 1'b0;`
249			`end`
250
251			`reg[15:0] mdio_data_in;`
252			`always@(posedge mdc or posedge reset)begin`
253			`if(reset)begin`
254			`mdio_data_in <=#TP 0;`
255			`end`
256			`else if(receiving)begin`
257			`mdio_data_in[0] <=#TP mdio_i;`
258			`mdio_data_in[1] <=#TP mdio_data_in[0];`
259			`mdio_data_in[2] <=#TP mdio_data_in[1];`
260			`mdio_data_in[3] <=#TP mdio_data_in[2];`
261			`mdio_data_in[4] <=#TP mdio_data_in[3];`
262			`mdio_data_in[5] <=#TP mdio_data_in[4];`
263			`mdio_data_in[6] <=#TP mdio_data_in[5];`
264			`mdio_data_in[7] <=#TP mdio_data_in[6];`
265			`mdio_data_in[8] <=#TP mdio_data_in[7];`
266			`mdio_data_in[9] <=#TP mdio_data_in[8];`
267			`mdio_data_in[10] <=#TP mdio_data_in[9];`
268			`mdio_data_in[11] <=#TP mdio_data_in[10];`
269			`mdio_data_in[12] <=#TP mdio_data_in[11];`
270			`mdio_data_in[13] <=#TP mdio_data_in[12];`
271			`mdio_data_in[14] <=#TP mdio_data_in[13];`
272			`mdio_data_in[15] <=#TP mdio_data_in[14];`
273			`end`
274			`else`
275			`mdio_data_in <=#TP mdio_data_in;`
276			`end`
277
278			`endmodule`

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