OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [CRC32_D8.v] - Blame information for rev 72

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 fisher5090
`timescale 1ns / 1ps
2
module CRC32_D8(DATA_IN, CLK, RESET, START, LOAD, CRC_IN, CRC_OUT);
3
 
4
  input [7:0] DATA_IN;
5
  input CLK;
6
  input RESET;
7
  input START;
8
  input LOAD;
9
  input [31:0] CRC_IN;
10
  output [31:0] CRC_OUT;
11
 
12
  reg [31:0] CRC_OUT;
13
//  reg start_int;
14
//  reg [7:0] data_int;
15
 
16
//always @(posedge CLK)
17
//begin
18
//  start_int <= START;
19
//  data_int <= DATA_IN;
20
//end
21
 
22
always @(posedge CLK or posedge RESET)
23
  begin
24
    if (RESET) begin
25
        CRC_OUT <= 0;
26
    end
27
    else if (START) begin
28
        CRC_OUT <= nextCRC32_D8(DATA_IN, CRC_OUT);
29
    end
30
    else if (LOAD) begin
31
        CRC_OUT <= CRC_IN;
32
    end
33
 
34
 
35
 
36
  end
37
 
38
 
39
///////////////////////////////////////////////////////////////////////
40
// File:  CRC32_D64.v                             
41
// Date:  Sun Nov 27 19:32:12 2005                                                      
42
//                                                                     
43
// Copyright (C) 1999-2003 Easics NV.                 
44
// This source file may be used and distributed without restriction    
45
// provided that this copyright statement is not removed from the file 
46
// and that any derivative work contains the original copyright notice
47
// and the associated disclaimer.
48
//
49
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
50
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
51
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
52
//
53
// Purpose: Verilog module containing a synthesizable CRC function
54
//   * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
55
//   * data width: 64
56
//                                                                     
57
// Info: tools@easics.be
58
//       http://www.easics.com                                  
59
///////////////////////////////////////////////////////////////////////
60
 
61
  // polynomial: (0 1 2 3 4 5 7 8 10 11 12 16 22 23 26 32)
62
  // data width: 8
63
  // convention: the first serial data bit is D[7]
64
  function [31:0] nextCRC32_D8;
65
 
66
    input [7:0] Data;
67
    input [31:0] CRC;
68
 
69
    reg [7:0] D;
70
    reg [31:0] C;
71
    reg [31:0] NewCRC;
72
 
73
  begin
74
 
75
    D = Data;
76
    C = CRC;
77
 
78
 
79
    NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
80
    NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^
81
                C[31];
82
    NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^
83
                C[26] ^ C[30] ^ C[31];
84
    NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^
85
                C[31];
86
    NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
87
                C[27] ^ C[28] ^ C[30];
88
    NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^
89
                C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
90
    NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^
91
                C[28] ^ C[29] ^ C[30] ^ C[31];
92
    NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
93
                C[27] ^ C[29] ^ C[31];
94
    NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^
95
                C[27] ^ C[28];
96
    NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^
97
                C[28] ^ C[29];
98
    NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^
99
                 C[27] ^ C[29];
100
    NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^
101
                 C[27] ^ C[28];
102
    NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^
103
                 C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
104
    NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^
105
                 C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
106
    NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^
107
                 C[28] ^ C[30] ^ C[31];
108
    NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^
109
                 C[29] ^ C[31];
110
    NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
111
    NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
112
    NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
113
    NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
114
    NewCRC[20] = D[4] ^ C[12] ^ C[28];
115
    NewCRC[21] = D[5] ^ C[13] ^ C[29];
116
    NewCRC[22] = D[0] ^ C[14] ^ C[24];
117
    NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
118
    NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
119
    NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
120
    NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^
121
                 C[28] ^ C[30];
122
    NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^
123
                 C[29] ^ C[31];
124
    NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
125
    NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
126
    NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
127
    NewCRC[31] = D[5] ^ C[23] ^ C[29];
128
 
129
    nextCRC32_D8 = NewCRC;
130
 
131
  end
132
 
133
  endfunction
134
 
135
endmodule
136
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.