Subversion Repositories ethmac10g

`include "timescale.v"

//////////////////////////////////////////////////////////////////////

////                                                                                                                                                                    ////

//// MODULE NAME: counter                                                                                               ////

////                                                                                                                                                                    ////

//// DESCRIPTION: 8bit counter                                    ////

////                                                              ////

////                                                                                                                                                                    ////

//// This file is part of the 10 Gigabit Ethernet IP core project ////

////  http://www.opencores.org/projects/ethmac10g/                                              ////

////                                                                                                                                                                    ////

//// AUTHOR(S):                                                                                                                                 ////

//// Zheng Cao                                                               ////

////                                                                                                    ////

//////////////////////////////////////////////////////////////////////

////                                                                                                                                                                    ////

//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////

////                                                                                                                                                                    ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                                                   ////

////                                                                                                                                                                    ////

//////////////////////////////////////////////////////////////////////

//

// CVS REVISION HISTORY:

//

// $Log: not supported by cvs2svn $

// Revision 1.1  2005/12/25 16:43:10  Zheng Cao

// 

// 

//

//////////////////////////////////////////////////////////////////////

module counter(clk, reset, load, en, value);

    input clk;

    input reset;

    input load;

    input en;

         parameter WIDTH = 8;

    output[WIDTH-1:0] value;

         reg [WIDTH-1:0] value;

    always @(posedge clk or posedge reset)

       if (reset)

          value <= 0;

       else begin

                    if (load)

             value <= 0;

          else if (en)

             value <= value + 1;

                 end

endmodule