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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [counter.v] - Blame information for rev 72

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`include "timescale.v"
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: counter                                         ////
////                                                              ////
//// DESCRIPTION: 8bit counter                                    ////
////                                                              ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2006/06/06 05:02:11  Zheng Cao
// no message
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
module counter(clk, reset, load, en, value);
    input clk;
    input reset;
    input load;
    input en;
 
    parameter WIDTH = 8;
    output[WIDTH-1:0] value;
 
    reg [WIDTH-1:0] value;
 
    always @(posedge clk or posedge reset)
       if (reset)
          value <= 0;
       else begin
       if (load)
             value <= 0;
          else if (en)
             value <= value + 1;
      end
 
endmodule

Line No.	Rev	Author	Line
1	41	fisher5090	`include "timescale.v"
2			`//////////////////////////////////////////////////////////////////////`
3	69	fisher5090	`//// ////`
4			`//// MODULE NAME: counter ////`
5			`//// ////`
6	41	fisher5090	`//// DESCRIPTION: 8bit counter ////`
7			`//// ////`
8	69	fisher5090	`//// ////`
9	41	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
10	69	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
11			`//// ////`
12			`//// AUTHOR(S): ////`
13			`//// Zheng Cao ////`
14			`//// ////`
15	41	fisher5090	`//////////////////////////////////////////////////////////////////////`
16	69	fisher5090	`//// ////`
17			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
18			`//// ////`
19	41	fisher5090	`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38	69	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40	41	fisher5090	`//////////////////////////////////////////////////////////////////////`
41	39	fisher5090	`//`
42	41	fisher5090	`// CVS REVISION HISTORY:`
43	39	fisher5090	`//`
44	41	fisher5090	`// $Log: not supported by cvs2svn $`
45	69	fisher5090	`// Revision 1.2 2006/06/06 05:02:11 Zheng Cao`
46			`// no message`
47			`//`
48	41	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
49	39	fisher5090	`//`
50			`//`
51	41	fisher5090	`//`
52			`//////////////////////////////////////////////////////////////////////`
53	39	fisher5090	`module counter(clk, reset, load, en, value);`
54			`input clk;`
55			`input reset;`
56			`input load;`
57			`input en;`
58
59	69	fisher5090	`parameter WIDTH = 8;`
60	39	fisher5090	`output[WIDTH-1:0] value;`
61
62	69	fisher5090	`reg [WIDTH-1:0] value;`
63	39	fisher5090
64			`always @(posedge clk or posedge reset)`
65			`if (reset)`
66			`value <= 0;`
67			`else begin`
68	69	fisher5090	`if (load)`
69	39	fisher5090	`value <= 0;`
70			`else if (en)`
71			`value <= value + 1;`
72	69	fisher5090	`end`
73
74	39	fisher5090	`endmodule`

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [counter.v] - Blame information for rev 72