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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxCRC.v] - Blame information for rev 72

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: rxCRC                                           ////
////                                                              ////
//// DESCRIPTION: CRC Checker, by using magic word c704dd7b.      ////
////                                                              ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2006/05/31 05:59:41  Zheng Cao
// first version
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxCRC(rxclk, reset, receiving, receiving_d1, CRC_DATA, get_terminator,
 get_terminator_d1, wait_crc_check,crc_check_invalid, crc_check_valid, terminator_location,get_error_code);
    input rxclk;
    input reset;
    input get_terminator;
    input [63:0] CRC_DATA;
    input receiving;
    input receiving_d1;
    input [2:0] terminator_location;
    input wait_crc_check;
 
    output crc_check_invalid;
    output crc_check_valid;
    output get_terminator_d1;
    input get_error_code;
 
    parameter TP = 1;
 
   ///////////////////////////////////////////////////
   // Input registers
   ///////////////////////////////////////////////////
 
   reg get_terminator_d1, get_terminator_d2,get_terminator_d3;
   always@(posedge rxclk or posedge reset) begin
        if(reset)begin
          get_terminator_d1 <=#TP 0;
          get_terminator_d2 <=#TP 0;
          get_terminator_d3 <=#TP 0;
        end
        else begin
          get_terminator_d1 <=#TP get_terminator;
          get_terminator_d2 <=#TP get_terminator_d1;
          get_terminator_d3 <=#TP get_terminator_d2;
        end
   end
 
   reg[2:0] bytes_cnt;
   reg crc_8_en;//enable 8bit CRC
   always@(posedge rxclk or posedge reset) begin
        if (reset)
           bytes_cnt <=#TP 0;
        else if (get_terminator)
           bytes_cnt <=#TP terminator_location;
        else if (crc_8_en)
           bytes_cnt <=#TP bytes_cnt-1;
   end
 
   reg[63:0] terminator_data;
   always@(posedge rxclk or posedge reset) begin
        if(reset)
           terminator_data <=#TP 0;
        else if (get_terminator_d2)
           terminator_data <=#TP CRC_DATA;
        else
           terminator_data <=#TP terminator_data<<8;
   end
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // 64bits CRC 
   // start: crc_valid = 8'hff and receiving_frame = 1
   // end  : crc_valid != 8'hff or receiving_frame = 0
   // if bits_more is 0, then CRC check will happen when end happens.
   // else 8bits CRC should begin
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   wire [31:0] crc_from_64;
 
   reg crc_64_en; // 64bit CRC Enable
   always@(posedge rxclk or posedge reset) begin
        if(reset)
          crc_64_en <= #TP 1'b0;
        else if(get_error_code) //if error, stop crc checking
          crc_64_en <= #TP 1'b0;
        else if(receiving_d1 & receiving)
          crc_64_en <= #TP 1'b1;
        else
          crc_64_en <= #TP 1'b0;
   end
 
   CRC32_D64 crc64(.DATA_IN(CRC_DATA), .CLK(rxclk), .RESET(reset), .START(crc_64_en), .CRC_OUT(crc_from_64), .init(get_terminator_d3|get_error_code));
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // 8bits CRC
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   reg[7:0] CRC_DATA_TMP;
   always@(posedge rxclk or posedge reset) begin
        if(reset)
          CRC_DATA_TMP <=#TP 0;
        else
          CRC_DATA_TMP <=#TP terminator_data[63:56];
        end
 
   always@(posedge rxclk or posedge reset) begin
        if(reset)
          crc_8_en <=#TP 0;
        else if (get_terminator_d3)
          crc_8_en <=#TP 1'b1;
        else if(bytes_cnt==1)
           crc_8_en <=#TP 1'b0;
   end
 
   reg do_crc_check;
   always@(posedge rxclk or posedge reset) begin
        if (reset)
          do_crc_check <=#TP 0;
        else if(terminator_location == 0)
          do_crc_check <=#TP get_terminator_d2;
        else
          do_crc_check <=#TP wait_crc_check & (bytes_cnt==1);
   end
 
   wire[31:0] crc_from_8;
   CRC32_D8  crc8(.DATA_IN(CRC_DATA_TMP), .CLK(rxclk), .RESET(reset), .START(crc_8_en), .LOAD(~crc_8_en), .CRC_IN(crc_from_64), .CRC_OUT(crc_from_8));
 
   ////////////////////////////////////////////////////////////////////////////////////////////
   // CRC check
   ////////////////////////////////////////////////////////////////////////////////////////////
   wire crc_check_valid, crc_check_invalid;
 
   assign crc_check_valid  = wait_crc_check & do_crc_check & (crc_from_8==32'hc704dd7b);
   assign crc_check_invalid = wait_crc_check & do_crc_check  & (crc_from_8!=32'hc704dd7b);
 
endmodule

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2	69	fisher5090	`//// ////`
3			`//// MODULE NAME: rxCRC ////`
4			`//// ////`
5	39	fisher5090	`//// DESCRIPTION: CRC Checker, by using magic word c704dd7b. ////`
6			`//// ////`
7	69	fisher5090	`//// ////`
8	39	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
9	69	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
10			`//// ////`
11			`//// AUTHOR(S): ////`
12			`//// Zheng Cao ////`
13			`//// ////`
14	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
15	69	fisher5090	`//// ////`
16			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
17			`//// ////`
18	39	fisher5090	`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37	69	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS REVISION HISTORY:`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	69	fisher5090	`// Revision 1.1.1.1 2006/05/31 05:59:41 Zheng Cao`
45			`// first version`
46			`//`
47	39	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
48			`//`
49			`//`
50			`//`
51			`//////////////////////////////////////////////////////////////////////`
52
53			`include "timescale.v"
54			`include "xgiga_define.v"
55
56			`module rxCRC(rxclk, reset, receiving, receiving_d1, CRC_DATA, get_terminator,`
57			`get_terminator_d1, wait_crc_check,crc_check_invalid, crc_check_valid, terminator_location,get_error_code);`
58			`input rxclk;`
59			`input reset;`
60	69	fisher5090	`input get_terminator;`
61	39	fisher5090	`input [63:0] CRC_DATA;`
62	69	fisher5090	`input receiving;`
63			`input receiving_d1;`
64			`input [2:0] terminator_location;`
65			`input wait_crc_check;`
66	39	fisher5090
67	69	fisher5090	`output crc_check_invalid;`
68			`output crc_check_valid;`
69			`output get_terminator_d1;`
70			`input get_error_code;`
71	39	fisher5090
72	69	fisher5090	`parameter TP = 1;`
73	39	fisher5090
74	69	fisher5090	`///////////////////////////////////////////////////`
75			`// Input registers`
76			`///////////////////////////////////////////////////`
77	39	fisher5090
78	69	fisher5090	`reg get_terminator_d1, get_terminator_d2,get_terminator_d3;`
79			`always@(posedge rxclk or posedge reset) begin`
80			`if(reset)begin`
81			`get_terminator_d1 <=#TP 0;`
82			`get_terminator_d2 <=#TP 0;`
83			`get_terminator_d3 <=#TP 0;`
84			`end`
85			`else begin`
86			`get_terminator_d1 <=#TP get_terminator;`
87			`get_terminator_d2 <=#TP get_terminator_d1;`
88			`get_terminator_d3 <=#TP get_terminator_d2;`
89			`end`
90			`end`
91	39	fisher5090
92	69	fisher5090	`reg[2:0] bytes_cnt;`
93			`reg crc_8_en;//enable 8bit CRC`
94			`always@(posedge rxclk or posedge reset) begin`
95			`if (reset)`
96			`bytes_cnt <=#TP 0;`
97			`else if (get_terminator)`
98			`bytes_cnt <=#TP terminator_location;`
99			`else if (crc_8_en)`
100			`bytes_cnt <=#TP bytes_cnt-1;`
101			`end`
102	39	fisher5090
103	69	fisher5090	`reg[63:0] terminator_data;`
104			`always@(posedge rxclk or posedge reset) begin`
105			`if(reset)`
106			`terminator_data <=#TP 0;`
107			`else if (get_terminator_d2)`
108			`terminator_data <=#TP CRC_DATA;`
109			`else`
110			`terminator_data <=#TP terminator_data<<8;`
111			`end`
112	39	fisher5090
113	69	fisher5090	`/////////////////////////////////////////////////////////////////////////////////////////////`
114			`// 64bits CRC`
115			`// start: crc_valid = 8'hff and receiving_frame = 1`
116			`// end : crc_valid != 8'hff or receiving_frame = 0`
117			`// if bits_more is 0, then CRC check will happen when end happens.`
118			`// else 8bits CRC should begin`
119			`/////////////////////////////////////////////////////////////////////////////////////////////`
120	39	fisher5090
121	69	fisher5090	`wire [31:0] crc_from_64;`
122
123			`reg crc_64_en; // 64bit CRC Enable`
124			`always@(posedge rxclk or posedge reset) begin`
125			`if(reset)`
126			`crc_64_en <= #TP 1'b0;`
127			`else if(get_error_code) //if error, stop crc checking`
128			`crc_64_en <= #TP 1'b0;`
129			`else if(receiving_d1 & receiving)`
130			`crc_64_en <= #TP 1'b1;`
131			`else`
132			`crc_64_en <= #TP 1'b0;`
133			`end`
134
135			`CRC32_D64 crc64(.DATA_IN(CRC_DATA), .CLK(rxclk), .RESET(reset), .START(crc_64_en), .CRC_OUT(crc_from_64), .init(get_terminator_d3\|get_error_code));`
136	39	fisher5090
137	69	fisher5090	`/////////////////////////////////////////////////////////////////////////////////////////////`
138			`// 8bits CRC`
139			`/////////////////////////////////////////////////////////////////////////////////////////////`
140	39	fisher5090
141	69	fisher5090	`reg[7:0] CRC_DATA_TMP;`
142			`always@(posedge rxclk or posedge reset) begin`
143			`if(reset)`
144			`CRC_DATA_TMP <=#TP 0;`
145			`else`
146			`CRC_DATA_TMP <=#TP terminator_data[63:56];`
147			`end`
148	39	fisher5090
149	69	fisher5090	`always@(posedge rxclk or posedge reset) begin`
150			`if(reset)`
151			`crc_8_en <=#TP 0;`
152			`else if (get_terminator_d3)`
153			`crc_8_en <=#TP 1'b1;`
154			`else if(bytes_cnt==1)`
155	39	fisher5090	`crc_8_en <=#TP 1'b0;`
156	69	fisher5090	`end`
157
158			`reg do_crc_check;`
159			`always@(posedge rxclk or posedge reset) begin`
160			`if (reset)`
161			`do_crc_check <=#TP 0;`
162			`else if(terminator_location == 0)`
163			`do_crc_check <=#TP get_terminator_d2;`
164			`else`
165			`do_crc_check <=#TP wait_crc_check & (bytes_cnt==1);`
166			`end`
167
168			`wire[31:0] crc_from_8;`
169			`CRC32_D8 crc8(.DATA_IN(CRC_DATA_TMP), .CLK(rxclk), .RESET(reset), .START(crc_8_en), .LOAD(~crc_8_en), .CRC_IN(crc_from_64), .CRC_OUT(crc_from_8));`
170	39	fisher5090
171	69	fisher5090	`////////////////////////////////////////////////////////////////////////////////////////////`
172			`// CRC check`
173			`////////////////////////////////////////////////////////////////////////////////////////////`
174			`wire crc_check_valid, crc_check_invalid;`
175	39	fisher5090
176	69	fisher5090	`assign crc_check_valid = wait_crc_check & do_crc_check & (crc_from_8==32'hc704dd7b);`
177			`assign crc_check_invalid = wait_crc_check & do_crc_check & (crc_from_8!=32'hc704dd7b);`
178
179	39	fisher5090	`endmodule`

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxCRC.v] - Blame information for rev 72