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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxDataPath.v] - Blame information for rev 72

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: Data Path of Receive Module                     ////
////                                                              ////
//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit       ////
////     Ethernet MAC. Used to recognize every field of a         ////
////     frame, including SOF, EOF, Length, Destination Addr      ////
////     , Source Addr and Data field.                            ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/                 ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2006/06/16 06:36:28  fisher5090
// no message
//
// Revision 1.5  2006/06/12 18:58:36  Zheng Cao
// no message
//
// Revision 1.4  2006/06/12 18:53:02  Zheng Cao
// remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation
// 
// Revision 1.3  2006/06/12 04:11:19  Zheng Cao
// both inband fcs and no inband fcs are OK, no remove PAD function
// 
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,
                  get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,
                  rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);
//                fcTxPauseData);
    input rxclk;
    input reset;
    input [63:0] rxd64;
    input [7:0] rxc8;
    input inband_fcs;
    input receiving;
    input start_da;
    input start_lt;
    input wait_crc_check;
    input get_terminator_d1;
    input bad_frame_get;
    input good_frame_get;
 
    output get_sfd;
    output get_terminator; //get T indicator
    output get_error_code; //get Error indicator
    output tagged_frame;
    output pause_frame;
    output[47:0] da_addr;
    output[2:0] terminator_location;
    output[63:0] CRC_DATA;
    output[7:0] rx_data_valid;
    output[63:0] rx_data;
    output check_reset;
    output rx_good_frame;
    output rx_bad_frame;
//  output [31:0]fcTxPauseData;
 
    parameter TP = 1;
    parameter IDLE = 0, READ = 2, WAIT_TMP = 3, WAIT = 1;
 
    //////////////////////////////////////////////
    // Pipe Line Stage
    //////////////////////////////////////////////
    reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
    reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;
    reg receiving_d1, receiving_d2;
    reg wait_crc_check_d1;
 
 // assign fcTxPauseData = rxd64_d1[31:0];
 // Data pipeline
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
            rxd64_d1<=#TP 0;
            rxd64_d2<=#TP 0;
            rxd64_d3<=#TP 0;
            CRC_DATA<=0;
         end
         else begin
            rxd64_d1<=#TP rxd64;
            rxd64_d2<=#TP rxd64_d1;
            rxd64_d3<=#TP rxd64_d2;
            CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],
                        rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],
                        rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],
                        rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],
                        rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],
                        rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],
                        rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],
                        rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};
         end
    end
    //control pipeline
    always@(posedge rxclk or posedge reset)begin
         if (reset)     begin
            rxc8_d1<=#TP 0;
            rxc8_d2<=#TP 0;
            rxc8_d3<=#TP 0;
         end
         else begin
            rxc8_d1<=#TP rxc8;
            rxc8_d2<=#TP rxc8_d1;
            rxc8_d3<=#TP rxc8_d2;
         end
    end
 
    always @(posedge rxclk or posedge reset)begin
         if (reset) begin
            receiving_d1 <=#TP 0;
            receiving_d2 <=#TP 0;
            wait_crc_check_d1 <=#TP 0;
         end
         else   begin
            receiving_d1 <=#TP receiving;
            receiving_d2 <=#TP receiving_d1;
            wait_crc_check_d1 <=#TP wait_crc_check;
         end
    end
 
    ////////////////////////////////////////////
    // Frame analysis
    ////////////////////////////////////////////
    reg get_sfd; //get sfd indicator
    reg get_terminator; //get T indicator
    reg get_error_code; //get Error indicator
    reg[7:0] get_e_chk;
    reg[7:0] rxc_end_data; //seperate DATA with FCS
    reg [2:0]terminator_location; //for n*8bits(n<8), get n
    reg[47:0] da_addr; //get Desetination Address
    reg tagged_frame;  //Tagged frame indicator(type interpret)
    reg pause_frame;   //Pause frame indicator(type interpret)
 
    //1. SFD 
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           get_sfd <=#TP 0;
         else
           get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
    end
 
    //2. EFD
    reg this_cycle;
    // -----------------------------------------------
    //|  0  |  1  |  2  |  3  |  4  |  5  |  6  |  7  | 
    // -----------------------------------------------
    //|<-------- EFD -------->|<-------- EFD -------->|
    //|<-- this_cycle = '1' ->|<-- this_cycle = '0' ->|
 
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
            get_terminator <=#TP 0;
            terminator_location <=#TP 0;
            this_cycle <=#TP 1'b0;
            rxc_end_data <=#TP 0;
         end
         else begin
            if (rxc8[0] & (rxd64[7:0]  ==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 0;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b00001111;
            end
            else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 1;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b00011111;
            end
            else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 2;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b00111111;
            end
            else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 3;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b01111111;
            end
            else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 4;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b11111111;
            end
            else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 5;
               this_cycle <=#TP 1'b0;
               rxc_end_data <=#TP 8'b00000001;
            end
            else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 6;
               this_cycle <=#TP 1'b0;
               rxc_end_data <=#TP 8'b00000011;
            end
            else if (rxc8[7] & (rxd64[63:56]==`TERMINATE))begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 7;
               this_cycle <=#TP 1'b0;
               rxc_end_data <=#TP 8'b00000111;
            end
            else begin
               get_terminator <=#TP 1'b0;
               terminator_location <=#TP terminator_location;
               this_cycle <=#TP this_cycle;
               rxc_end_data <=#TP rxc_end_data;
            end
        end
    end
 
    //3. Error Character
    always@(posedge rxclk or posedge reset) begin
          if (reset)
             get_e_chk <=#TP 0;
          else begin
             get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0]  ==`ERROR);
             get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
             get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
             get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
             get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
             get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
             get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
             get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
          end
    end
 
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            get_error_code <=#TP 0;
          else
            get_error_code <=#TP receiving & (| get_e_chk);
    end
 
    //////////////////////////////////////
    // Get Destination Address
    //////////////////////////////////////
 
    always@(posedge rxclk or posedge reset)begin
         if (reset)
           da_addr <=#TP 0;
         else if (start_da)
           da_addr <=#TP rxd64_d1[47:0];
         else
           da_addr <=#TP da_addr;
    end
 
    //////////////////////////////////////
    // Get Length/Type Field
    //////////////////////////////////////
 
    reg[15:0] lt_data;
    always@(posedge rxclk or posedge reset)begin
         if (reset)
           lt_data <=#TP 0;
         else if (start_lt)
           lt_data <=#TP {rxd64_d1[39:32], rxd64_d1[47:40]};
         else
           lt_data <=#TP lt_data;
    end
 
    reg[5:0] pad_integer;
    reg[5:0] pad_remain;
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
           pad_integer <=#TP 0;
           pad_remain <=#TP 0;
         end
         else begin
           pad_integer <=#TP (lt_data[5:0] - 2)>>3;
           pad_remain <=#TP lt_data[5:0] - 2;
         end
    end
    //Remove PAD counter
    reg[2:0] pad_cnt;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           pad_cnt <=#TP 0;
         else if(lt_data[5:0] == 1)
           pad_cnt <=#TP 1;
         else
           pad_cnt <=#TP pad_integer[2:0] + 2;
    end
 
    reg [7:0] pad_last_rxc;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           pad_last_rxc <=#TP 0;
         else if(lt_data[5:0] == 1)
           pad_last_rxc <=#TP 8'h7f;
         else begin
             case (pad_remain[2:0])
                0: pad_last_rxc <=#TP 8'h00;
                1: pad_last_rxc <=#TP 8'h01;
                2: pad_last_rxc <=#TP 8'h03;
                3: pad_last_rxc <=#TP 8'h07;
                4: pad_last_rxc <=#TP 8'h0f;
                5: pad_last_rxc <=#TP 8'h1f;
                6: pad_last_rxc <=#TP 8'h3f;
                7: pad_last_rxc <=#TP 8'h7f;
             endcase
       end
    end
 
    reg pad_frame;
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            pad_frame <=#TP 0;
          else if(~(lt_data[0]|lt_data[1]|lt_data[2]|lt_data[3]|lt_data[4]|lt_data[5]))
            pad_frame <=#TP 1'b0;
          else if(lt_data<46)
            pad_frame <=#TP 1'b1;
          else
            pad_frame <=#TP 1'b0;
    end
 
    //tagged frame indicator
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            tagged_frame <=#TP 1'b0;
          else if (start_lt)
            tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
          else
            tagged_frame <=#TP tagged_frame;
    end
    //pause frame indicator
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            pause_frame <=#TP 1'b0;
          else if (start_lt)
            pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
          else
            pause_frame <=#TP 1'b0;
    end
 
    /////////////////////////////////////////////
    // Generate proper rxc to FIFO                                              
    /////////////////////////////////////////////
 
    reg [7:0]rxc_final;
    wire [7:0]rxc_fifo; //rxc send to fifo
 
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           rxc_final <=#TP 0;
         else if (get_terminator & this_cycle)
           rxc_final <=#TP rxc_end_data;
         else if (get_terminator_d1 & ~this_cycle)
           rxc_final <=#TP rxc_end_data;
         else if (get_error_code)
           rxc_final <=#TP 0;
         else if (receiving)
             rxc_final <=#TP `ALLONES8;
         else
             rxc_final <=#TP 0;
    end
 
    assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;
 
    ////////////////////////////////////////////////////////////////
    // FIFO management, to generate rx_good_frame/rx_bad_frame
    // after a frame has been totally received.
    ////////////////////////////////////////////////////////////////
    wire rxfifo_full;
    wire rxfifo_empty;
    wire fifo_wr_en;
    wire [63:0] rx_data_tmp;
    wire [7:0] rx_data_valid_tmp;
 
    reg fifo_rd_en;
    reg[1:0] fifo_state;
    wire rx_good_frame;
    wire rx_bad_frame;
    reg check_reset;
    always@(posedge rxclk or posedge reset) begin
         if(reset) begin
           fifo_rd_en <=#TP 1'b0;
           fifo_state <=#TP IDLE;
           check_reset <=#TP 1'b0;
         end
         else
             case (fifo_state)
                 IDLE: begin
                      check_reset <=#TP 1'b0;
                      fifo_state <=#TP IDLE;
                      fifo_rd_en <=#TP 1'b0;
                      if(~rxfifo_empty) begin
                         fifo_rd_en <=#TP 1'b1;
                         fifo_state <=#TP WAIT_TMP;
                      end
                 end
                 READ: begin
                      check_reset <=#TP 1'b0;
                      fifo_rd_en <=#TP 1'b1;
                      fifo_state <=#TP READ;
                      if(rx_data_valid_tmp!=8'hff) begin
                         fifo_state <=#TP WAIT;
                         fifo_rd_en <=#TP 1'b0;
                      end
                 end
                 WAIT_TMP: begin
                      if(rx_data_valid_tmp == 8'hff)
                         fifo_state <=#TP READ;
                      else
                         fifo_state <=#TP WAIT_TMP;
                 end
                 WAIT: begin
                      fifo_state <=#TP WAIT;
                      check_reset <=#TP 1'b0;
                      fifo_rd_en <=#TP 1'b0;
                      if(bad_frame_get | good_frame_get)begin
                         fifo_state <=#TP IDLE;
                         check_reset <=#TP 1'b1;
                      end
                 end
             endcase
    end
 
    reg[2:0] pad_cnt_reg;
    always@(posedge rxclk or posedge reset) begin
         if(reset)
           pad_cnt_reg <=#TP 0;
         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)
           pad_cnt_reg <=#TP pad_cnt;
         else if(pad_cnt_reg ==0)
           pad_cnt_reg <=#TP 0;
         else if(fifo_state[1])
           pad_cnt_reg <=#TP pad_cnt_reg-1;
         else
           pad_cnt_reg <=#TP 0;
    end
 
    reg[7:0] pad_rxc_reg;
    always@(posedge rxclk or posedge reset)begin
         if(reset)
           pad_rxc_reg <=#TP 0;
         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)
           pad_rxc_reg <=#TP pad_last_rxc;
         else
           pad_rxc_reg <=#TP pad_rxc_reg;
    end
 
    reg pad_frame_d1;
    always@(posedge rxclk or posedge reset) begin
         if(reset)
           pad_frame_d1<=#TP 1'b0;
         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)
           pad_frame_d1<=#TP 1'b1;
         else if(fifo_state == WAIT)
           pad_frame_d1 <=#TP 1'b0;
         else
           pad_frame_d1 <=#TP pad_frame_d1;
    end
 
    assign rx_good_frame = good_frame_get & (fifo_state == WAIT);
    assign rx_bad_frame = bad_frame_get & (fifo_state == WAIT);
 
    assign fifo_wr_en = receiving_d2;
 
    defparam rxdatain.pWordWidth = 64;
    defparam rxdatain.pDepthWidth = 7;
 
    SwitchSyncFIFO rxdatain(
        .nReset(!reset),
        .iClk(rxclk),
        .iWEn(fifo_wr_en),
        .ivDataIn(rxd64_d3),
        .iREn(fifo_rd_en),
        .ovDataOut(rx_data_tmp),
        .qEmpty(rxfifo_empty),
        .qFull(rxfifo_full),
        .qvCount()
    );
    defparam rxcntrlin.pWordWidth = 8;
    defparam rxcntrlin.pDepthWidth = 7;
 
    SwitchSyncFIFO rxcntrlin(
        .nReset(!reset),
        .iClk(rxclk),
        .iWEn(fifo_wr_en),
        .ivDataIn(rxc_fifo),
        .iREn(fifo_rd_en),
        .ovDataOut(rx_data_valid_tmp),
        .qEmpty(),
        .qFull(),
        .qvCount()
    );
    reg [63:0] rx_data;
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
            rx_data <=#TP 0;
         end
         else begin
            rx_data <=#TP rx_data_tmp;
         end
    end
 
    reg [7:0] rx_data_valid;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
            rx_data_valid <=#TP 0;
         else if(fifo_state[1] & pad_frame_d1)
            if(pad_cnt_reg==1)
               rx_data_valid <=#TP pad_rxc_reg;
            else if(pad_cnt_reg==0)
               rx_data_valid <=#TP 0;
            else
               rx_data_valid <=#TP rx_data_valid_tmp;
         else if(fifo_state[1] & ~pad_frame_d1)
            rx_data_valid <=#TP rx_data_valid_tmp;
         else
            rx_data_valid <=#TP 0;
    end
 
endmodule

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2	69	fisher5090	`//// ////`
3			`//// MODULE NAME: Data Path of Receive Module ////`
4			`//// ////`
5	39	fisher5090	`//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit ////`
6			`//// Ethernet MAC. Used to recognize every field of a ////`
7	69	fisher5090	`//// frame, including SOF, EOF, Length, Destination Addr ////`
8	39	fisher5090	`//// , Source Addr and Data field. ////`
9	69	fisher5090	`//// ////`
10	39	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
11	69	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
12			`//// ////`
13			`//// AUTHOR(S): ////`
14			`//// Zheng Cao ////`
15			`//// ////`
16	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
17	69	fisher5090	`//// ////`
18			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
19			`//// ////`
20	39	fisher5090	`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39	69	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS REVISION HISTORY:`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	71	fisher5090	`// Revision 1.6 2006/06/16 06:36:28 fisher5090`
47			`// no message`
48			`//`
49	69	fisher5090	`// Revision 1.5 2006/06/12 18:58:36 Zheng Cao`
50			`// no message`
51			`//`
52			`// Revision 1.4 2006/06/12 18:53:02 Zheng Cao`
53	64	fisher5090	`// remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation`
54			`//`
55	69	fisher5090	`// Revision 1.3 2006/06/12 04:11:19 Zheng Cao`
56	64	fisher5090	`// both inband fcs and no inband fcs are OK, no remove PAD function`
57			`//`
58	39	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
59			`//`
60			`//`
61			`//`
62			`//////////////////////////////////////////////////////////////////////`
63
64			`include "timescale.v"
65			`include "xgiga_define.v"
66
67			`module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,`
68			`get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,`
69	69	fisher5090	`rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);`
70			`// fcTxPauseData);`
71	39	fisher5090	`input rxclk;`
72			`input reset;`
73			`input [63:0] rxd64;`
74			`input [7:0] rxc8;`
75	69	fisher5090	`input inband_fcs;`
76			`input receiving;`
77			`input start_da;`
78			`input start_lt;`
79			`input wait_crc_check;`
80			`input get_terminator_d1;`
81			`input bad_frame_get;`
82			`input good_frame_get;`
83
84			`output get_sfd;`
85			`output get_terminator; //get T indicator`
86			`output get_error_code; //get Error indicator`
87	39	fisher5090	`output tagged_frame;`
88	69	fisher5090	`output pause_frame;`
89			`output[47:0] da_addr;`
90			`output[2:0] terminator_location;`
91	39	fisher5090	`output[63:0] CRC_DATA;`
92	69	fisher5090	`output[7:0] rx_data_valid;`
93			`output[63:0] rx_data;`
94			`output check_reset;`
95			`output rx_good_frame;`
96			`output rx_bad_frame;`
97			`// output [31:0]fcTxPauseData;`
98
99			`parameter TP = 1;`
100			`parameter IDLE = 0, READ = 2, WAIT_TMP = 3, WAIT = 1;`
101
102			`//////////////////////////////////////////////`
103			`// Pipe Line Stage`
104			`//////////////////////////////////////////////`
105			`reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;`
106			`reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;`
107			`reg receiving_d1, receiving_d2;`
108			`reg wait_crc_check_d1;`
109
110			`// assign fcTxPauseData = rxd64_d1[31:0];`
111			`// Data pipeline`
112			`always@(posedge rxclk or posedge reset) begin`
113			`if (reset) begin`
114			`rxd64_d1<=#TP 0;`
115			`rxd64_d2<=#TP 0;`
116			`rxd64_d3<=#TP 0;`
117			`CRC_DATA<=0;`
118			`end`
119			`else begin`
120			`rxd64_d1<=#TP rxd64;`
121			`rxd64_d2<=#TP rxd64_d1;`
122			`rxd64_d3<=#TP rxd64_d2;`
123			`CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],`
124			`rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],`
125			`rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],`
126			`rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],`
127			`rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],`
128			`rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],`
129			`rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],`
130			`rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};`
131			`end`
132			`end`
133			`//control pipeline`
134			`always@(posedge rxclk or posedge reset)begin`
135			`if (reset) begin`
136			`rxc8_d1<=#TP 0;`
137			`rxc8_d2<=#TP 0;`
138			`rxc8_d3<=#TP 0;`
139			`end`
140			`else begin`
141			`rxc8_d1<=#TP rxc8;`
142			`rxc8_d2<=#TP rxc8_d1;`
143			`rxc8_d3<=#TP rxc8_d2;`
144			`end`
145			`end`
146	39	fisher5090
147	69	fisher5090	`always @(posedge rxclk or posedge reset)begin`
148			`if (reset) begin`
149			`receiving_d1 <=#TP 0;`
150			`receiving_d2 <=#TP 0;`
151			`wait_crc_check_d1 <=#TP 0;`
152			`end`
153			`else begin`
154			`receiving_d1 <=#TP receiving;`
155			`receiving_d2 <=#TP receiving_d1;`
156			`wait_crc_check_d1 <=#TP wait_crc_check;`
157			`end`
158			`end`
159
160			`////////////////////////////////////////////`
161			`// Frame analysis`
162			`////////////////////////////////////////////`
163			`reg get_sfd; //get sfd indicator`
164			`reg get_terminator; //get T indicator`
165			`reg get_error_code; //get Error indicator`
166			`reg[7:0] get_e_chk;`
167			`reg[7:0] rxc_end_data; //seperate DATA with FCS`
168			`reg [2:0]terminator_location; //for n*8bits(n<8), get n`
169			`reg[47:0] da_addr; //get Desetination Address`
170			`reg tagged_frame; //Tagged frame indicator(type interpret)`
171			`reg pause_frame; //Pause frame indicator(type interpret)`
172
173			`//1. SFD`
174	39	fisher5090	`always@(posedge rxclk or posedge reset) begin`
175	69	fisher5090	`if (reset)`
176			`get_sfd <=#TP 0;`
177			`else`
178			get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
179			`end`
180
181			`//2. EFD`
182			`reg this_cycle;`
183			`// -----------------------------------------------`
184			`//\| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \|`
185			`// -----------------------------------------------`
186			`//\|<-------- EFD -------->\|<-------- EFD -------->\|`
187			`//\|<-- this_cycle = '1' ->\|<-- this_cycle = '0' ->\|`
188
189			`always@(posedge rxclk or posedge reset) begin`
190			`if (reset) begin`
191			`get_terminator <=#TP 0;`
192			`terminator_location <=#TP 0;`
193			`this_cycle <=#TP 1'b0;`
194			`rxc_end_data <=#TP 0;`
195			`end`
196			`else begin`
197			if (rxc8[0] & (rxd64[7:0] ==`TERMINATE)) begin
198			`get_terminator <=#TP 1'b1;`
199			`terminator_location <=#TP 0;`
200			`this_cycle <=#TP 1'b1;`
201			`rxc_end_data <=#TP 8'b00001111;`
202			`end`
203			else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
204			`get_terminator <=#TP 1'b1;`
205			`terminator_location <=#TP 1;`
206			`this_cycle <=#TP 1'b1;`
207			`rxc_end_data <=#TP 8'b00011111;`
208			`end`
209			else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
210			`get_terminator <=#TP 1'b1;`
211			`terminator_location <=#TP 2;`
212			`this_cycle <=#TP 1'b1;`
213			`rxc_end_data <=#TP 8'b00111111;`
214			`end`
215			else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
216			`get_terminator <=#TP 1'b1;`
217			`terminator_location <=#TP 3;`
218			`this_cycle <=#TP 1'b1;`
219			`rxc_end_data <=#TP 8'b01111111;`
220			`end`
221			else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
222			`get_terminator <=#TP 1'b1;`
223			`terminator_location <=#TP 4;`
224			`this_cycle <=#TP 1'b1;`
225			`rxc_end_data <=#TP 8'b11111111;`
226			`end`
227			else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
228			`get_terminator <=#TP 1'b1;`
229			`terminator_location <=#TP 5;`
230			`this_cycle <=#TP 1'b0;`
231			`rxc_end_data <=#TP 8'b00000001;`
232			`end`
233			else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
234			`get_terminator <=#TP 1'b1;`
235			`terminator_location <=#TP 6;`
236			`this_cycle <=#TP 1'b0;`
237			`rxc_end_data <=#TP 8'b00000011;`
238			`end`
239			else if (rxc8[7] & (rxd64[63:56]==`TERMINATE))begin
240			`get_terminator <=#TP 1'b1;`
241			`terminator_location <=#TP 7;`
242			`this_cycle <=#TP 1'b0;`
243			`rxc_end_data <=#TP 8'b00000111;`
244			`end`
245			`else begin`
246			`get_terminator <=#TP 1'b0;`
247			`terminator_location <=#TP terminator_location;`
248			`this_cycle <=#TP this_cycle;`
249			`rxc_end_data <=#TP rxc_end_data;`
250			`end`
251			`end`
252			`end`
253
254			`//3. Error Character`
255			`always@(posedge rxclk or posedge reset) begin`
256			`if (reset)`
257			`get_e_chk <=#TP 0;`
258			`else begin`
259			get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0] ==`ERROR);
260			get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
261	39	fisher5090	get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
262			get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
263	69	fisher5090	get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
264	39	fisher5090	get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
265			get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
266			get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
267	69	fisher5090	`end`
268			`end`
269
270			`always@(posedge rxclk or posedge reset) begin`
271			`if (reset)`
272			`get_error_code <=#TP 0;`
273	39	fisher5090	`else`
274	69	fisher5090	`get_error_code <=#TP receiving & (\| get_e_chk);`
275			`end`
276	39	fisher5090
277	69	fisher5090	`//////////////////////////////////////`
278			`// Get Destination Address`
279			`//////////////////////////////////////`
280
281			`always@(posedge rxclk or posedge reset)begin`
282			`if (reset)`
283			`da_addr <=#TP 0;`
284			`else if (start_da)`
285			`da_addr <=#TP rxd64_d1[47:0];`
286			`else`
287			`da_addr <=#TP da_addr;`
288	39	fisher5090	`end`
289
290	69	fisher5090	`//////////////////////////////////////`
291			`// Get Length/Type Field`
292			`//////////////////////////////////////`
293	39	fisher5090
294	69	fisher5090	`reg[15:0] lt_data;`
295			`always@(posedge rxclk or posedge reset)begin`
296			`if (reset)`
297			`lt_data <=#TP 0;`
298			`else if (start_lt)`
299			`lt_data <=#TP {rxd64_d1[39:32], rxd64_d1[47:40]};`
300			`else`
301			`lt_data <=#TP lt_data;`
302	52	fisher5090	`end`
303	69	fisher5090
304			`reg[5:0] pad_integer;`
305			`reg[5:0] pad_remain;`
306			`always@(posedge rxclk or posedge reset) begin`
307			`if (reset) begin`
308			`pad_integer <=#TP 0;`
309			`pad_remain <=#TP 0;`
310			`end`
311			`else begin`
312			`pad_integer <=#TP (lt_data[5:0] - 2)>>3;`
313			`pad_remain <=#TP lt_data[5:0] - 2;`
314			`end`
315			`end`
316			`//Remove PAD counter`
317			`reg[2:0] pad_cnt;`
318			`always@(posedge rxclk or posedge reset) begin`
319			`if (reset)`
320			`pad_cnt <=#TP 0;`
321			`else if(lt_data[5:0] == 1)`
322			`pad_cnt <=#TP 1;`
323			`else`
324			`pad_cnt <=#TP pad_integer[2:0] + 2;`
325			`end`
326	39	fisher5090
327	63	fisher5090	`reg [7:0] pad_last_rxc;`
328			`always@(posedge rxclk or posedge reset) begin`
329	69	fisher5090	`if (reset)`
330			`pad_last_rxc <=#TP 0;`
331			`else if(lt_data[5:0] == 1)`
332			`pad_last_rxc <=#TP 8'h7f;`
333			`else begin`
334			`case (pad_remain[2:0])`
335			`0: pad_last_rxc <=#TP 8'h00;`
336			`1: pad_last_rxc <=#TP 8'h01;`
337			`2: pad_last_rxc <=#TP 8'h03;`
338			`3: pad_last_rxc <=#TP 8'h07;`
339			`4: pad_last_rxc <=#TP 8'h0f;`
340			`5: pad_last_rxc <=#TP 8'h1f;`
341			`6: pad_last_rxc <=#TP 8'h3f;`
342			`7: pad_last_rxc <=#TP 8'h7f;`
343			`endcase`
344	63	fisher5090	`end`
345	69	fisher5090	`end`
346	63	fisher5090
347	69	fisher5090	`reg pad_frame;`
348	63	fisher5090	`always@(posedge rxclk or posedge reset) begin`
349	69	fisher5090	`if (reset)`
350			`pad_frame <=#TP 0;`
351			`else if(~(lt_data[0]\|lt_data[1]\|lt_data[2]\|lt_data[3]\|lt_data[4]\|lt_data[5]))`
352			`pad_frame <=#TP 1'b0;`
353			`else if(lt_data<46)`
354			`pad_frame <=#TP 1'b1;`
355			`else`
356			`pad_frame <=#TP 1'b0;`
357			`end`
358
359	39	fisher5090	`//tagged frame indicator`
360	69	fisher5090	`always@(posedge rxclk or posedge reset) begin`
361			`if (reset)`
362			`tagged_frame <=#TP 1'b0;`
363			`else if (start_lt)`
364			tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
365			`else`
366			`tagged_frame <=#TP tagged_frame;`
367			`end`
368			`//pause frame indicator`
369			`always@(posedge rxclk or posedge reset) begin`
370			`if (reset)`
371			`pause_frame <=#TP 1'b0;`
372			`else if (start_lt)`
373			pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
374			`else`
375			`pause_frame <=#TP 1'b0;`
376			`end`
377	39	fisher5090
378			`/////////////////////////////////////////////`
379			`// Generate proper rxc to FIFO`
380			`/////////////////////////////////////////////`
381
382	69	fisher5090	`reg [7:0]rxc_final;`
383			`wire [7:0]rxc_fifo; //rxc send to fifo`
384	39	fisher5090
385			`always@(posedge rxclk or posedge reset) begin`
386	69	fisher5090	`if (reset)`
387			`rxc_final <=#TP 0;`
388			`else if (get_terminator & this_cycle)`
389			`rxc_final <=#TP rxc_end_data;`
390			`else if (get_terminator_d1 & ~this_cycle)`
391			`rxc_final <=#TP rxc_end_data;`
392			`else if (get_error_code)`
393			`rxc_final <=#TP 0;`
394			`else if (receiving)`
395	57	fisher5090	rxc_final <=#TP `ALLONES8;
396	69	fisher5090	`else`
397			`rxc_final <=#TP 0;`
398			`end`
399	39	fisher5090
400	69	fisher5090	`assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;`
401	39	fisher5090
402			`////////////////////////////////////////////////////////////////`
403			`// FIFO management, to generate rx_good_frame/rx_bad_frame`
404			`// after a frame has been totally received.`
405			`////////////////////////////////////////////////////////////////`
406	69	fisher5090	`wire rxfifo_full;`
407			`wire rxfifo_empty;`
408			`wire fifo_wr_en;`
409	39	fisher5090	`wire [63:0] rx_data_tmp;`
410	69	fisher5090	`wire [7:0] rx_data_valid_tmp;`
411
412			`reg fifo_rd_en;`
413			`reg[1:0] fifo_state;`
414			`wire rx_good_frame;`
415			`wire rx_bad_frame;`
416			`reg check_reset;`
417			`always@(posedge rxclk or posedge reset) begin`
418			`if(reset) begin`
419			`fifo_rd_en <=#TP 1'b0;`
420			`fifo_state <=#TP IDLE;`
421			`check_reset <=#TP 1'b0;`
422			`end`
423			`else`
424			`case (fifo_state)`
425			`IDLE: begin`
426			`check_reset <=#TP 1'b0;`
427			`fifo_state <=#TP IDLE;`
428			`fifo_rd_en <=#TP 1'b0;`
429			`if(~rxfifo_empty) begin`
430			`fifo_rd_en <=#TP 1'b1;`
431			`fifo_state <=#TP WAIT_TMP;`
432			`end`
433			`end`
434			`READ: begin`
435			`check_reset <=#TP 1'b0;`
436			`fifo_rd_en <=#TP 1'b1;`
437			`fifo_state <=#TP READ;`
438			`if(rx_data_valid_tmp!=8'hff) begin`
439			`fifo_state <=#TP WAIT;`
440			`fifo_rd_en <=#TP 1'b0;`
441			`end`
442			`end`
443			`WAIT_TMP: begin`
444			`if(rx_data_valid_tmp == 8'hff)`
445			`fifo_state <=#TP READ;`
446			`else`
447			`fifo_state <=#TP WAIT_TMP;`
448			`end`
449			`WAIT: begin`
450			`fifo_state <=#TP WAIT;`
451			`check_reset <=#TP 1'b0;`
452			`fifo_rd_en <=#TP 1'b0;`
453			`if(bad_frame_get \| good_frame_get)begin`
454			`fifo_state <=#TP IDLE;`
455			`check_reset <=#TP 1'b1;`
456			`end`
457			`end`
458			`endcase`
459	39	fisher5090	`end`
460	69	fisher5090
461			`reg[2:0] pad_cnt_reg;`
462			`always@(posedge rxclk or posedge reset) begin`
463			`if(reset)`
464			`pad_cnt_reg <=#TP 0;`
465			`else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)`
466			`pad_cnt_reg <=#TP pad_cnt;`
467			`else if(pad_cnt_reg ==0)`
468			`pad_cnt_reg <=#TP 0;`
469			`else if(fifo_state[1])`
470			`pad_cnt_reg <=#TP pad_cnt_reg-1;`
471			`else`
472			`pad_cnt_reg <=#TP 0;`
473			`end`
474
475			`reg[7:0] pad_rxc_reg;`
476			`always@(posedge rxclk or posedge reset)begin`
477			`if(reset)`
478			`pad_rxc_reg <=#TP 0;`
479			`else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)`
480			`pad_rxc_reg <=#TP pad_last_rxc;`
481			`else`
482			`pad_rxc_reg <=#TP pad_rxc_reg;`
483			`end`
484
485			`reg pad_frame_d1;`
486			`always@(posedge rxclk or posedge reset) begin`
487			`if(reset)`
488			`pad_frame_d1<=#TP 1'b0;`
489			`else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)`
490			`pad_frame_d1<=#TP 1'b1;`
491			`else if(fifo_state == WAIT)`
492			`pad_frame_d1 <=#TP 1'b0;`
493			`else`
494			`pad_frame_d1 <=#TP pad_frame_d1;`
495			`end`
496	52	fisher5090
497	69	fisher5090	`assign rx_good_frame = good_frame_get & (fifo_state == WAIT);`
498			`assign rx_bad_frame = bad_frame_get & (fifo_state == WAIT);`
499	52	fisher5090
500	69	fisher5090	`assign fifo_wr_en = receiving_d2;`

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxDataPath.v] - Blame information for rev 72