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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: Data Path of Receive Module                     ////
////                                                              ////
//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit       ////
////     Ethernet MAC. Used to recognize every field of a         ////
////     frame, including SOF, EOF, Length, Destination Addr      ////
////     , Source Addr and Data field.                            ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/                 ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2006/06/12 18:58:36  Zheng Cao
// no message
//
// Revision 1.4  2006/06/12 18:53:02  Zheng Cao
// remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation
// 
// Revision 1.3  2006/06/12 04:11:19  Zheng Cao
// both inband fcs and no inband fcs are OK, no remove PAD function
// 
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,
                  get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,
                  rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);
//                fcTxPauseData);
    input rxclk;
    input reset;
    input [63:0] rxd64;
    input [7:0] rxc8;
    input inband_fcs;
    input receiving;
    input start_da;
    input start_lt;
    input wait_crc_check;
    input get_terminator_d1;
    input bad_frame_get;
    input good_frame_get;
 
    output get_sfd;
    output get_terminator; //get T indicator
    output get_error_code; //get Error indicator
    output tagged_frame;
    output pause_frame;
    output[47:0] da_addr;
    output[2:0] terminator_location;
    output[63:0] CRC_DATA;
    output[7:0] rx_data_valid;
    output[63:0] rx_data;
    output check_reset;
    output rx_good_frame;
    output rx_bad_frame;
//  output [31:0]fcTxPauseData;
 
    parameter TP = 1;
    parameter IDLE = 0, READ = 2, WAIT_TMP = 3, WAIT = 1;
 
    //////////////////////////////////////////////
    // Pipe Line Stage
    //////////////////////////////////////////////
    reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
    reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;
    reg receiving_d1, receiving_d2;
    reg wait_crc_check_d1;
 
 // assign fcTxPauseData = rxd64_d1[31:0];
 // Data pipeline
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
            rxd64_d1<=#TP 0;
            rxd64_d2<=#TP 0;
            rxd64_d3<=#TP 0;
            CRC_DATA<=0;
         end
         else begin
            rxd64_d1<=#TP rxd64;
            rxd64_d2<=#TP rxd64_d1;
            rxd64_d3<=#TP rxd64_d2;
            CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],
                        rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],
                        rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],
                        rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],
                        rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],
                        rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],
                        rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],
                        rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};
         end
    end
    //control pipeline
    always@(posedge rxclk or posedge reset)begin
         if (reset)     begin
            rxc8_d1<=#TP 0;
            rxc8_d2<=#TP 0;
            rxc8_d3<=#TP 0;
         end
         else begin
            rxc8_d1<=#TP rxc8;
            rxc8_d2<=#TP rxc8_d1;
            rxc8_d3<=#TP rxc8_d2;
         end
    end
 
    always @(posedge rxclk or posedge reset)begin
         if (reset) begin
            receiving_d1 <=#TP 0;
            receiving_d2 <=#TP 0;
            wait_crc_check_d1 <=#TP 0;
         end
         else   begin
            receiving_d1 <=#TP receiving;
            receiving_d2 <=#TP receiving_d1;
            wait_crc_check_d1 <=#TP wait_crc_check;
         end
    end
 
    ////////////////////////////////////////////
    // Frame analysis
    ////////////////////////////////////////////
    reg get_sfd; //get sfd indicator
    reg get_terminator; //get T indicator
    reg get_error_code; //get Error indicator
    reg[7:0] get_e_chk;
    reg[7:0] rxc_end_data; //seperate DATA with FCS
    reg [2:0]terminator_location; //for n*8bits(n<8), get n
    reg[47:0] da_addr; //get Desetination Address
    reg tagged_frame;  //Tagged frame indicator(type interpret)
    reg pause_frame;   //Pause frame indicator(type interpret)
 
    //1. SFD 
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           get_sfd <=#TP 0;
         else
           get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
    end
 
    //2. EFD
    reg this_cycle;
    // -----------------------------------------------
    //|  0  |  1  |  2  |  3  |  4  |  5  |  6  |  7  | 
    // -----------------------------------------------
    //|<-------- EFD -------->|<-------- EFD -------->|
    //|<-- this_cycle = '1' ->|<-- this_cycle = '0' ->|
 
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
            get_terminator <=#TP 0;
            terminator_location <=#TP 0;
            this_cycle <=#TP 1'b0;
            rxc_end_data <=#TP 0;
         end
         else begin
            if (rxc8[0] & (rxd64[7:0]  ==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 0;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b00001111;
            end
            else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 1;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b00011111;
            end
            else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 2;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b00111111;
            end
            else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 3;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b01111111;
            end
            else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 4;
               this_cycle <=#TP 1'b1;
               rxc_end_data <=#TP 8'b11111111;
            end
            else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 5;
               this_cycle <=#TP 1'b0;
               rxc_end_data <=#TP 8'b00000001;
            end
            else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 6;
               this_cycle <=#TP 1'b0;
               rxc_end_data <=#TP 8'b00000011;
            end
            else if (rxc8[7] & (rxd64[63:56]==`TERMINATE))begin
               get_terminator <=#TP 1'b1;
               terminator_location <=#TP 7;
               this_cycle <=#TP 1'b0;
               rxc_end_data <=#TP 8'b00000111;
            end
            else begin
               get_terminator <=#TP 1'b0;
               terminator_location <=#TP terminator_location;
               this_cycle <=#TP this_cycle;
               rxc_end_data <=#TP rxc_end_data;
            end
        end
    end
 
    //3. Error Character
    always@(posedge rxclk or posedge reset) begin
          if (reset)
             get_e_chk <=#TP 0;
          else begin
             get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0]  ==`ERROR);
             get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
             get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
             get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
             get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
             get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
             get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
             get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
          end
    end
 
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            get_error_code <=#TP 0;
          else
            get_error_code <=#TP receiving & (| get_e_chk);
    end
 
    //////////////////////////////////////
    // Get Destination Address
    //////////////////////////////////////
 
    always@(posedge rxclk or posedge reset)begin
         if (reset)
           da_addr <=#TP 0;
         else if (start_da)
           da_addr <=#TP rxd64_d1[47:0];
         else
           da_addr <=#TP da_addr;
    end
 
    //////////////////////////////////////
    // Get Length/Type Field
    //////////////////////////////////////
 
    reg[15:0] lt_data;
    always@(posedge rxclk or posedge reset)begin
         if (reset)
           lt_data <=#TP 0;
         else if (start_lt)
           lt_data <=#TP {rxd64_d1[39:32], rxd64_d1[47:40]};
         else
           lt_data <=#TP lt_data;
    end
 
    reg[5:0] pad_integer;
    reg[5:0] pad_remain;
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
           pad_integer <=#TP 0;
           pad_remain <=#TP 0;
         end
         else begin
           pad_integer <=#TP (lt_data[5:0] - 2)>>3;
           pad_remain <=#TP lt_data[5:0] - 2;
         end
    end
    //Remove PAD counter
    reg[2:0] pad_cnt;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           pad_cnt <=#TP 0;
         else if(lt_data[5:0] == 1)
           pad_cnt <=#TP 1;
         else
           pad_cnt <=#TP pad_integer[2:0] + 2;
    end
 
    reg [7:0] pad_last_rxc;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           pad_last_rxc <=#TP 0;
         else if(lt_data[5:0] == 1)
           pad_last_rxc <=#TP 8'h7f;
         else begin
             case (pad_remain[2:0])
                0: pad_last_rxc <=#TP 8'h00;
                1: pad_last_rxc <=#TP 8'h01;
                2: pad_last_rxc <=#TP 8'h03;
                3: pad_last_rxc <=#TP 8'h07;
                4: pad_last_rxc <=#TP 8'h0f;
                5: pad_last_rxc <=#TP 8'h1f;
                6: pad_last_rxc <=#TP 8'h3f;
                7: pad_last_rxc <=#TP 8'h7f;
             endcase
       end
    end
 
    reg pad_frame;
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            pad_frame <=#TP 0;
          else if(~(lt_data[0]|lt_data[1]|lt_data[2]|lt_data[3]|lt_data[4]|lt_data[5]))
            pad_frame <=#TP 1'b0;
          else if(lt_data<46)
            pad_frame <=#TP 1'b1;
          else
            pad_frame <=#TP 1'b0;
    end
 
    //tagged frame indicator
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            tagged_frame <=#TP 1'b0;
          else if (start_lt)
            tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
          else
            tagged_frame <=#TP tagged_frame;
    end
    //pause frame indicator
    always@(posedge rxclk or posedge reset) begin
          if (reset)
            pause_frame <=#TP 1'b0;
          else if (start_lt)
            pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
          else
            pause_frame <=#TP 1'b0;
    end
 
    /////////////////////////////////////////////
    // Generate proper rxc to FIFO                                              
    /////////////////////////////////////////////
 
    reg [7:0]rxc_final;
    wire [7:0]rxc_fifo; //rxc send to fifo
 
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           rxc_final <=#TP 0;
         else if (get_terminator & this_cycle)
           rxc_final <=#TP rxc_end_data;
         else if (get_terminator_d1 & ~this_cycle)
           rxc_final <=#TP rxc_end_data;
         else if (get_error_code)
           rxc_final <=#TP 0;
         else if (receiving)
             rxc_final <=#TP `ALLONES8;
         else
             rxc_final <=#TP 0;
    end
 
    assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;
 
    ////////////////////////////////////////////////////////////////
    // FIFO management, to generate rx_good_frame/rx_bad_frame
    // after a frame has been totally received.
    ////////////////////////////////////////////////////////////////
    wire rxfifo_full;
    wire rxfifo_empty;
    wire fifo_wr_en;
    wire [63:0] rx_data_tmp;
    wire [7:0] rx_data_valid_tmp;
 
    reg fifo_rd_en;
    reg[1:0] fifo_state;
    wire rx_good_frame;
    wire rx_bad_frame;
    reg check_reset;
    always@(posedge rxclk or posedge reset) begin
         if(reset) begin
           fifo_rd_en <=#TP 1'b0;
           fifo_state <=#TP IDLE;
           check_reset <=#TP 1'b0;
         end
         else
             case (fifo_state)
                 IDLE: begin
                      check_reset <=#TP 1'b0;
                      fifo_state <=#TP IDLE;
                      fifo_rd_en <=#TP 1'b0;
                      if(~rxfifo_empty) begin
                         fifo_rd_en <=#TP 1'b1;
                         fifo_state <=#TP WAIT_TMP;
                      end
                 end
                 READ: begin
                      check_reset <=#TP 1'b0;
                      fifo_rd_en <=#TP 1'b1;
                      fifo_state <=#TP READ;
                      if(rx_data_valid_tmp!=8'hff) begin
                         fifo_state <=#TP WAIT;
                         fifo_rd_en <=#TP 1'b0;
                      end
                 end
                 WAIT_TMP: begin
                      if(rx_data_valid_tmp == 8'hff)
                         fifo_state <=#TP READ;
                      else
                         fifo_state <=#TP WAIT_TMP;
                 end
                 WAIT: begin
                      fifo_state <=#TP WAIT;
                      check_reset <=#TP 1'b0;
                      fifo_rd_en <=#TP 1'b0;
                      if(bad_frame_get | good_frame_get)begin
                         fifo_state <=#TP IDLE;
                         check_reset <=#TP 1'b1;
                      end
                 end
             endcase
    end
 
    reg[2:0] pad_cnt_reg;
    always@(posedge rxclk or posedge reset) begin
         if(reset)
           pad_cnt_reg <=#TP 0;
         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)
           pad_cnt_reg <=#TP pad_cnt;
         else if(pad_cnt_reg ==0)
           pad_cnt_reg <=#TP 0;
         else if(fifo_state[1])
           pad_cnt_reg <=#TP pad_cnt_reg-1;
         else
           pad_cnt_reg <=#TP 0;
    end
 
    reg[7:0] pad_rxc_reg;
    always@(posedge rxclk or posedge reset)begin
         if(reset)
           pad_rxc_reg <=#TP 0;
         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)
           pad_rxc_reg <=#TP pad_last_rxc;
         else
           pad_rxc_reg <=#TP pad_rxc_reg;
    end
 
    reg pad_frame_d1;
    always@(posedge rxclk or posedge reset) begin
         if(reset)
           pad_frame_d1<=#TP 1'b0;
         else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)
           pad_frame_d1<=#TP 1'b1;
         else if(fifo_state == WAIT)
           pad_frame_d1 <=#TP 1'b0;
         else
           pad_frame_d1 <=#TP pad_frame_d1;
    end
 
    assign rx_good_frame = good_frame_get & (fifo_state == WAIT);
    assign rx_bad_frame = bad_frame_get & (fifo_state == WAIT);
 
    assign fifo_wr_en = receiving_d2;
 
    rxdatafifo rxdatain(.clk(rxclk),
                        .sinit(reset),
                        .din(rxd64_d3),
                        .wr_en(fifo_wr_en),
                        .rd_en(fifo_rd_en),
                        .dout(rx_data_tmp),
                        .full(rxfifo_full),
                        .empty(rxfifo_empty));
 
    rxcntrlfifo rxcntrlin(.clk(rxclk),
                          .sinit(reset),
                          .din(rxc_fifo),
                          .wr_en(fifo_wr_en),
                          .rd_en(fifo_rd_en),
                          .dout(rx_data_valid_tmp),
                          .full(),
                          .empty());
    reg [63:0] rx_data;
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
            rx_data <=#TP 0;
         end
         else begin
            rx_data <=#TP rx_data_tmp;
         end
    end
 
    reg [7:0] rx_data_valid;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
            rx_data_valid <=#TP 0;
         else if(fifo_state[1] & pad_frame_d1)
            if(pad_cnt_reg==1)
               rx_data_valid <=#TP pad_rxc_reg;
            else if(pad_cnt_reg==0)
               rx_data_valid <=#TP 0;
            else
               rx_data_valid <=#TP rx_data_valid_tmp;
         else if(fifo_state[1] & ~pad_frame_d1)
            rx_data_valid <=#TP rx_data_valid_tmp;
         else
            rx_data_valid <=#TP 0;
    end
 
endmodule

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2	69	fisher5090	`//// ////`
3			`//// MODULE NAME: Data Path of Receive Module ////`
4			`//// ////`
5	39	fisher5090	`//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit ////`
6			`//// Ethernet MAC. Used to recognize every field of a ////`
7	69	fisher5090	`//// frame, including SOF, EOF, Length, Destination Addr ////`
8	39	fisher5090	`//// , Source Addr and Data field. ////`
9	69	fisher5090	`//// ////`
10	39	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
11	69	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
12			`//// ////`
13			`//// AUTHOR(S): ////`
14			`//// Zheng Cao ////`
15			`//// ////`
16	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
17	69	fisher5090	`//// ////`
18			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
19			`//// ////`
20	39	fisher5090	`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39	69	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS REVISION HISTORY:`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	69	fisher5090	`// Revision 1.5 2006/06/12 18:58:36 Zheng Cao`
47			`// no message`
48			`//`
49			`// Revision 1.4 2006/06/12 18:53:02 Zheng Cao`
50	64	fisher5090	`// remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation`
51			`//`
52	69	fisher5090	`// Revision 1.3 2006/06/12 04:11:19 Zheng Cao`
53	64	fisher5090	`// both inband fcs and no inband fcs are OK, no remove PAD function`
54			`//`
55	39	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
56			`//`
57			`//`
58			`//`
59			`//////////////////////////////////////////////////////////////////////`
60
61			`include "timescale.v"
62			`include "xgiga_define.v"
63
64			`module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,`
65			`get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,`
66	69	fisher5090	`rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);`
67			`// fcTxPauseData);`
68	39	fisher5090	`input rxclk;`
69			`input reset;`
70			`input [63:0] rxd64;`
71			`input [7:0] rxc8;`
72	69	fisher5090	`input inband_fcs;`
73			`input receiving;`
74			`input start_da;`
75			`input start_lt;`
76			`input wait_crc_check;`
77			`input get_terminator_d1;`
78			`input bad_frame_get;`
79			`input good_frame_get;`
80
81			`output get_sfd;`
82			`output get_terminator; //get T indicator`
83			`output get_error_code; //get Error indicator`
84	39	fisher5090	`output tagged_frame;`
85	69	fisher5090	`output pause_frame;`
86			`output[47:0] da_addr;`
87			`output[2:0] terminator_location;`
88	39	fisher5090	`output[63:0] CRC_DATA;`
89	69	fisher5090	`output[7:0] rx_data_valid;`
90			`output[63:0] rx_data;`
91			`output check_reset;`
92			`output rx_good_frame;`
93			`output rx_bad_frame;`
94			`// output [31:0]fcTxPauseData;`
95
96			`parameter TP = 1;`
97			`parameter IDLE = 0, READ = 2, WAIT_TMP = 3, WAIT = 1;`
98
99			`//////////////////////////////////////////////`
100			`// Pipe Line Stage`
101			`//////////////////////////////////////////////`
102			`reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;`
103			`reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;`
104			`reg receiving_d1, receiving_d2;`
105			`reg wait_crc_check_d1;`
106
107			`// assign fcTxPauseData = rxd64_d1[31:0];`
108			`// Data pipeline`
109			`always@(posedge rxclk or posedge reset) begin`
110			`if (reset) begin`
111			`rxd64_d1<=#TP 0;`
112			`rxd64_d2<=#TP 0;`
113			`rxd64_d3<=#TP 0;`
114			`CRC_DATA<=0;`
115			`end`
116			`else begin`
117			`rxd64_d1<=#TP rxd64;`
118			`rxd64_d2<=#TP rxd64_d1;`
119			`rxd64_d3<=#TP rxd64_d2;`
120			`CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],`
121			`rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],`
122			`rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],`
123			`rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],`
124			`rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],`
125			`rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],`
126			`rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],`
127			`rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};`
128			`end`
129			`end`
130			`//control pipeline`
131			`always@(posedge rxclk or posedge reset)begin`
132			`if (reset) begin`
133			`rxc8_d1<=#TP 0;`
134			`rxc8_d2<=#TP 0;`
135			`rxc8_d3<=#TP 0;`
136			`end`
137			`else begin`
138			`rxc8_d1<=#TP rxc8;`
139			`rxc8_d2<=#TP rxc8_d1;`
140			`rxc8_d3<=#TP rxc8_d2;`
141			`end`
142			`end`
143	39	fisher5090
144	69	fisher5090	`always @(posedge rxclk or posedge reset)begin`
145			`if (reset) begin`
146			`receiving_d1 <=#TP 0;`
147			`receiving_d2 <=#TP 0;`
148			`wait_crc_check_d1 <=#TP 0;`
149			`end`
150			`else begin`
151			`receiving_d1 <=#TP receiving;`
152			`receiving_d2 <=#TP receiving_d1;`
153			`wait_crc_check_d1 <=#TP wait_crc_check;`
154			`end`
155			`end`
156
157			`////////////////////////////////////////////`
158			`// Frame analysis`
159			`////////////////////////////////////////////`
160			`reg get_sfd; //get sfd indicator`
161			`reg get_terminator; //get T indicator`
162			`reg get_error_code; //get Error indicator`
163			`reg[7:0] get_e_chk;`
164			`reg[7:0] rxc_end_data; //seperate DATA with FCS`
165			`reg [2:0]terminator_location; //for n*8bits(n<8), get n`
166			`reg[47:0] da_addr; //get Desetination Address`
167			`reg tagged_frame; //Tagged frame indicator(type interpret)`
168			`reg pause_frame; //Pause frame indicator(type interpret)`
169
170			`//1. SFD`
171	39	fisher5090	`always@(posedge rxclk or posedge reset) begin`
172	69	fisher5090	`if (reset)`
173			`get_sfd <=#TP 0;`
174			`else`
175			get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
176			`end`
177
178			`//2. EFD`
179			`reg this_cycle;`
180			`// -----------------------------------------------`
181			`//\| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \|`
182			`// -----------------------------------------------`
183			`//\|<-------- EFD -------->\|<-------- EFD -------->\|`
184			`//\|<-- this_cycle = '1' ->\|<-- this_cycle = '0' ->\|`
185
186			`always@(posedge rxclk or posedge reset) begin`
187			`if (reset) begin`
188			`get_terminator <=#TP 0;`
189			`terminator_location <=#TP 0;`
190			`this_cycle <=#TP 1'b0;`
191			`rxc_end_data <=#TP 0;`
192			`end`
193			`else begin`
194			if (rxc8[0] & (rxd64[7:0] ==`TERMINATE)) begin
195			`get_terminator <=#TP 1'b1;`
196			`terminator_location <=#TP 0;`
197			`this_cycle <=#TP 1'b1;`
198			`rxc_end_data <=#TP 8'b00001111;`
199			`end`
200			else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
201			`get_terminator <=#TP 1'b1;`
202			`terminator_location <=#TP 1;`
203			`this_cycle <=#TP 1'b1;`
204			`rxc_end_data <=#TP 8'b00011111;`
205			`end`
206			else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
207			`get_terminator <=#TP 1'b1;`
208			`terminator_location <=#TP 2;`
209			`this_cycle <=#TP 1'b1;`
210			`rxc_end_data <=#TP 8'b00111111;`
211			`end`
212			else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
213			`get_terminator <=#TP 1'b1;`
214			`terminator_location <=#TP 3;`
215			`this_cycle <=#TP 1'b1;`
216			`rxc_end_data <=#TP 8'b01111111;`
217			`end`
218			else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
219			`get_terminator <=#TP 1'b1;`
220			`terminator_location <=#TP 4;`
221			`this_cycle <=#TP 1'b1;`
222			`rxc_end_data <=#TP 8'b11111111;`
223			`end`
224			else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
225			`get_terminator <=#TP 1'b1;`
226			`terminator_location <=#TP 5;`
227			`this_cycle <=#TP 1'b0;`
228			`rxc_end_data <=#TP 8'b00000001;`
229			`end`
230			else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
231			`get_terminator <=#TP 1'b1;`
232			`terminator_location <=#TP 6;`
233			`this_cycle <=#TP 1'b0;`
234			`rxc_end_data <=#TP 8'b00000011;`
235			`end`
236			else if (rxc8[7] & (rxd64[63:56]==`TERMINATE))begin
237			`get_terminator <=#TP 1'b1;`
238			`terminator_location <=#TP 7;`
239			`this_cycle <=#TP 1'b0;`
240			`rxc_end_data <=#TP 8'b00000111;`
241			`end`
242			`else begin`
243			`get_terminator <=#TP 1'b0;`
244			`terminator_location <=#TP terminator_location;`
245			`this_cycle <=#TP this_cycle;`
246			`rxc_end_data <=#TP rxc_end_data;`
247			`end`
248			`end`
249			`end`
250
251			`//3. Error Character`
252			`always@(posedge rxclk or posedge reset) begin`
253			`if (reset)`
254			`get_e_chk <=#TP 0;`
255			`else begin`
256			get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0] ==`ERROR);
257			get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
258	39	fisher5090	get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
259			get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
260	69	fisher5090	get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
261	39	fisher5090	get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
262			get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
263			get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
264	69	fisher5090	`end`
265			`end`
266
267			`always@(posedge rxclk or posedge reset) begin`
268			`if (reset)`
269			`get_error_code <=#TP 0;`
270	39	fisher5090	`else`
271	69	fisher5090	`get_error_code <=#TP receiving & (\| get_e_chk);`
272			`end`
273	39	fisher5090
274	69	fisher5090	`//////////////////////////////////////`
275			`// Get Destination Address`
276			`//////////////////////////////////////`
277
278			`always@(posedge rxclk or posedge reset)begin`
279			`if (reset)`
280			`da_addr <=#TP 0;`
281			`else if (start_da)`
282			`da_addr <=#TP rxd64_d1[47:0];`
283			`else`
284			`da_addr <=#TP da_addr;`
285	39	fisher5090	`end`
286
287	69	fisher5090	`//////////////////////////////////////`
288			`// Get Length/Type Field`
289			`//////////////////////////////////////`
290	39	fisher5090
291	69	fisher5090	`reg[15:0] lt_data;`
292			`always@(posedge rxclk or posedge reset)begin`
293			`if (reset)`
294			`lt_data <=#TP 0;`
295			`else if (start_lt)`
296			`lt_data <=#TP {rxd64_d1[39:32], rxd64_d1[47:40]};`
297			`else`
298			`lt_data <=#TP lt_data;`
299	52	fisher5090	`end`
300	69	fisher5090
301			`reg[5:0] pad_integer;`
302			`reg[5:0] pad_remain;`
303			`always@(posedge rxclk or posedge reset) begin`
304			`if (reset) begin`
305			`pad_integer <=#TP 0;`
306			`pad_remain <=#TP 0;`
307			`end`
308			`else begin`
309			`pad_integer <=#TP (lt_data[5:0] - 2)>>3;`
310			`pad_remain <=#TP lt_data[5:0] - 2;`
311			`end`
312			`end`
313			`//Remove PAD counter`
314			`reg[2:0] pad_cnt;`
315			`always@(posedge rxclk or posedge reset) begin`
316			`if (reset)`
317			`pad_cnt <=#TP 0;`
318			`else if(lt_data[5:0] == 1)`
319			`pad_cnt <=#TP 1;`
320			`else`
321			`pad_cnt <=#TP pad_integer[2:0] + 2;`
322			`end`
323	39	fisher5090
324	63	fisher5090	`reg [7:0] pad_last_rxc;`
325			`always@(posedge rxclk or posedge reset) begin`
326	69	fisher5090	`if (reset)`
327			`pad_last_rxc <=#TP 0;`
328			`else if(lt_data[5:0] == 1)`
329			`pad_last_rxc <=#TP 8'h7f;`
330			`else begin`
331			`case (pad_remain[2:0])`
332			`0: pad_last_rxc <=#TP 8'h00;`
333			`1: pad_last_rxc <=#TP 8'h01;`
334			`2: pad_last_rxc <=#TP 8'h03;`
335			`3: pad_last_rxc <=#TP 8'h07;`
336			`4: pad_last_rxc <=#TP 8'h0f;`
337			`5: pad_last_rxc <=#TP 8'h1f;`
338			`6: pad_last_rxc <=#TP 8'h3f;`
339			`7: pad_last_rxc <=#TP 8'h7f;`
340			`endcase`
341	63	fisher5090	`end`
342	69	fisher5090	`end`
343	63	fisher5090
344	69	fisher5090	`reg pad_frame;`
345	63	fisher5090	`always@(posedge rxclk or posedge reset) begin`
346	69	fisher5090	`if (reset)`
347			`pad_frame <=#TP 0;`
348			`else if(~(lt_data[0]\|lt_data[1]\|lt_data[2]\|lt_data[3]\|lt_data[4]\|lt_data[5]))`
349			`pad_frame <=#TP 1'b0;`
350			`else if(lt_data<46)`
351			`pad_frame <=#TP 1'b1;`
352			`else`
353			`pad_frame <=#TP 1'b0;`
354			`end`
355
356	39	fisher5090	`//tagged frame indicator`
357	69	fisher5090	`always@(posedge rxclk or posedge reset) begin`
358			`if (reset)`
359			`tagged_frame <=#TP 1'b0;`
360			`else if (start_lt)`
361			tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
362			`else`
363			`tagged_frame <=#TP tagged_frame;`
364			`end`
365			`//pause frame indicator`
366			`always@(posedge rxclk or posedge reset) begin`
367			`if (reset)`
368			`pause_frame <=#TP 1'b0;`
369			`else if (start_lt)`
370			pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
371			`else`
372			`pause_frame <=#TP 1'b0;`
373			`end`
374	39	fisher5090
375			`/////////////////////////////////////////////`
376			`// Generate proper rxc to FIFO`
377			`/////////////////////////////////////////////`
378
379	69	fisher5090	`reg [7:0]rxc_final;`
380			`wire [7:0]rxc_fifo; //rxc send to fifo`
381	39	fisher5090
382			`always@(posedge rxclk or posedge reset) begin`
383	69	fisher5090	`if (reset)`
384			`rxc_final <=#TP 0;`
385			`else if (get_terminator & this_cycle)`
386			`rxc_final <=#TP rxc_end_data;`
387			`else if (get_terminator_d1 & ~this_cycle)`
388			`rxc_final <=#TP rxc_end_data;`
389			`else if (get_error_code)`
390			`rxc_final <=#TP 0;`
391			`else if (receiving)`
392	57	fisher5090	rxc_final <=#TP `ALLONES8;
393	69	fisher5090	`else`
394			`rxc_final <=#TP 0;`
395			`end`
396	39	fisher5090
397	69	fisher5090	`assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;`
398	39	fisher5090
399			`////////////////////////////////////////////////////////////////`
400			`// FIFO management, to generate rx_good_frame/rx_bad_frame`
401			`// after a frame has been totally received.`
402			`////////////////////////////////////////////////////////////////`
403	69	fisher5090	`wire rxfifo_full;`
404			`wire rxfifo_empty;`
405			`wire fifo_wr_en;`
406	39	fisher5090	`wire [63:0] rx_data_tmp;`
407	69	fisher5090	`wire [7:0] rx_data_valid_tmp;`
408
409			`reg fifo_rd_en;`
410			`reg[1:0] fifo_state;`
411			`wire rx_good_frame;`
412			`wire rx_bad_frame;`
413			`reg check_reset;`
414			`always@(posedge rxclk or posedge reset) begin`
415			`if(reset) begin`
416			`fifo_rd_en <=#TP 1'b0;`
417			`fifo_state <=#TP IDLE;`
418			`check_reset <=#TP 1'b0;`
419			`end`
420			`else`
421			`case (fifo_state)`
422			`IDLE: begin`
423			`check_reset <=#TP 1'b0;`
424			`fifo_state <=#TP IDLE;`
425			`fifo_rd_en <=#TP 1'b0;`
426			`if(~rxfifo_empty) begin`
427			`fifo_rd_en <=#TP 1'b1;`
428			`fifo_state <=#TP WAIT_TMP;`
429			`end`
430			`end`
431			`READ: begin`
432			`check_reset <=#TP 1'b0;`
433			`fifo_rd_en <=#TP 1'b1;`
434			`fifo_state <=#TP READ;`
435			`if(rx_data_valid_tmp!=8'hff) begin`
436			`fifo_state <=#TP WAIT;`
437			`fifo_rd_en <=#TP 1'b0;`
438			`end`
439			`end`
440			`WAIT_TMP: begin`
441			`if(rx_data_valid_tmp == 8'hff)`
442			`fifo_state <=#TP READ;`
443			`else`
444			`fifo_state <=#TP WAIT_TMP;`
445			`end`
446			`WAIT: begin`
447			`fifo_state <=#TP WAIT;`
448			`check_reset <=#TP 1'b0;`
449			`fifo_rd_en <=#TP 1'b0;`
450			`if(bad_frame_get \| good_frame_get)begin`
451			`fifo_state <=#TP IDLE;`
452			`check_reset <=#TP 1'b1;`
453			`end`
454			`end`
455			`endcase`
456	39	fisher5090	`end`
457	69	fisher5090
458			`reg[2:0] pad_cnt_reg;`
459			`always@(posedge rxclk or posedge reset) begin`
460			`if(reset)`
461			`pad_cnt_reg <=#TP 0;`
462			`else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)`
463			`pad_cnt_reg <=#TP pad_cnt;`
464			`else if(pad_cnt_reg ==0)`
465			`pad_cnt_reg <=#TP 0;`
466			`else if(fifo_state[1])`
467			`pad_cnt_reg <=#TP pad_cnt_reg-1;`
468			`else`
469			`pad_cnt_reg <=#TP 0;`
470			`end`
471
472			`reg[7:0] pad_rxc_reg;`
473			`always@(posedge rxclk or posedge reset)begin`
474			`if(reset)`
475			`pad_rxc_reg <=#TP 0;`
476			`else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)`
477			`pad_rxc_reg <=#TP pad_last_rxc;`
478			`else`
479			`pad_rxc_reg <=#TP pad_rxc_reg;`
480			`end`
481
482			`reg pad_frame_d1;`
483			`always@(posedge rxclk or posedge reset) begin`
484			`if(reset)`
485			`pad_frame_d1<=#TP 1'b0;`
486			`else if((fifo_state == WAIT_TMP)& pad_frame & ~rxfifo_empty)`
487			`pad_frame_d1<=#TP 1'b1;`
488			`else if(fifo_state == WAIT)`
489			`pad_frame_d1 <=#TP 1'b0;`
490			`else`
491			`pad_frame_d1 <=#TP pad_frame_d1;`
492			`end`
493	52	fisher5090
494	69	fisher5090	`assign rx_good_frame = good_frame_get & (fifo_state == WAIT);`
495			`assign rx_bad_frame = bad_frame_get & (fifo_state == WAIT);`
496	52	fisher5090
497	69	fisher5090	`assign fifo_wr_en = receiving_d2;`
498
499			`rxdatafifo rxdatain(.clk(rxclk),`
500			`.sinit(reset),`

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