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fisher5090 |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// MODULE NAME: rxLinkFaultState ////
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//// ////
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//// DESCRIPTION: State machine for Link Fault Signalling. ////
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//// ////
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//// ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// ////
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//// AUTHOR(S): ////
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//// Zheng Cao ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS REVISION HISTORY:
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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//
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//
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//
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "xgiga_define.v"
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module rxLinkFaultState(rxclk, reset, local_fault, remote_fault, link_fault);
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input rxclk;
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input reset;
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input local_fault;
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input remote_fault;
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output[1:0] link_fault;
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parameter TP =1;
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parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;
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//------------------------------------------------
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// Link Fault Signalling Statemachine
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//------------------------------------------------
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wire fault_type;
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wire get_one_fault;
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wire no_new_type;
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reg[2:0] linkstate, linkstate_next;
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reg[5:0] col_cnt;
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reg seq_cnt;
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reg[1:0] seq_type;
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reg[1:0] last_seq_type;
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reg[1:0] link_fault;
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reg reset_col_cnt;
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wire seq_cnt_3;
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wire col_cnt_64;
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assign fault_type = {local_fault, remote_fault};
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assign get_one_fault = local_fault | remote_fault;
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assign no_new_type = (seq_type == last_seq_type);
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assign col_cnt_64 = & col_cnt;
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always@(posedge rxclk or posedge reset)begin
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if (reset) begin
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seq_type <=#TP 0;
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seq_cnt <=#TP 0;
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last_seq_type <=#TP 0;
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reset_col_cnt<= #TP 1;
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link_fault <=#TP 2'b00;
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linkstate<= #TP IDLE;
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end
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else begin
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seq_type <= #TP fault_type;
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last_seq_type <=#TP seq_type;
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case (linkstate)
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IDLE: begin
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linkstate <=#TP IDLE;
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reset_col_cnt <= #TP 1;
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seq_cnt <= #TP 0;
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link_fault <= #TP 2'b00;
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if (get_one_fault)
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linkstate<=#TP LinkFaultDetect;
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end
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LinkFaultDetect: begin
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linkstate <=#TP LinkFaultDetect;
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reset_col_cnt <=#TP 1;
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if (get_one_fault & no_new_type) begin
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if (seq_cnt) begin
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linkstate <=#TP IDLE;
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link_fault <=#TP seq_type; //final fault indeed(equals to GetFault status)
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end
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else
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seq_cnt <=#TP seq_cnt + 1;
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end
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else if(~get_one_fault) begin
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reset_col_cnt <=#TP 0;
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if (col_cnt_64)
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linkstate <=#TP IDLE;
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end
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else if(get_one_fault & ~no_new_type)
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linkstate <=#TP NewFaultType;
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end
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NewFaultType: begin
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seq_cnt <=#TP 0;
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linkstate <=#TP LinkFaultDetect;
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reset_col_cnt<=#TP 1;
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end
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// GetFault: begin
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// linkstate <=#TP IDLE;
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// reset_col_cnt <=#TP 1;
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// link_fault <=#TP seq_type;
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// if (get_one_fault & no_new_type)
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// link_fault <=#TP seq_type;
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// else if (~get_one_fault) begin
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// reset_col_cnt<=#TP 0;
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// if(col_cnt_128)
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// linkstate <=#TP IDLE;
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// end
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// else if (get_one_fault & ~no_new_type)
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// linkstate <=#TP NewFaultType;
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// end
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endcase
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end
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end
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always@(posedge rxclk or posedge reset) begin
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if (reset)
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col_cnt <=#TP 0;
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else if (reset_col_cnt)
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col_cnt <=#TP 0;
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else
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col_cnt <=#TP col_cnt + 1;
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end
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endmodule
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