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https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk
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39 |
fisher5090 |
#AREA_GROUP "AG_counters" RANGE = SLICE_X34Y37:SLICE_X41Y32
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#INST "counters" AREA_GROUP = "AG_counters"
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| 3 |
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#AREA_GROUP "AG_crcmodule" RANGE = SLICE_X32Y21:SLICE_X49Y4
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#INST "crcmodule" AREA_GROUP = "AG_crcmodule"
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#AREA_GROUP "AG_datapath_main" RANGE = SLICE_X14Y35:SLICE_X29Y20
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#INST "datapath_main" AREA_GROUP = "AG_datapath_main"
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#AREA_GROUP "AG_lenchecker" RANGE = SLICE_X44Y37:SLICE_X51Y30
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#INST "lenchecker" AREA_GROUP = "AG_lenchecker"
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#AREA_GROUP "AG_rx_rs" RANGE = SLICE_X0Y31:SLICE_X9Y20
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#INST "rx_rs" AREA_GROUP = "AG_rx_rs"
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#AREA_GROUP "AG_rx_stat" RANGE = SLICE_X46Y27:SLICE_X49Y24
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#INST "rx_stat" AREA_GROUP = "AG_rx_stat"
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#AREA_GROUP "AG_statemachine" RANGE = SLICE_X34Y27:SLICE_X41Y24
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#INST "statemachine" AREA_GROUP = "AG_statemachine"
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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| 17 |
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#PACE: Start of PACE Area Constraints
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| 18 |
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AREA_GROUP "AG_rxReceiveEngine" RANGE = SLICE_X2Y37:SLICE_X33Y2 ;
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INST "/" AREA_GROUP = "AG_rxReceiveEngine" ;
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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| 22 |
70 |
fisher5090 |
NET "xgmii_rxclk" TNM_NET = "xgmii_rxclk";
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| 23 |
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TIMESPEC "TS_xgmii_rxclk" = PERIOD "xgmii_rxclk" 6.5 ns HIGH 50 %;
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#OFFSET = IN 2 ns BEFORE "xgmii_rxclk" HIGH ;
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