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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.v] - Blame information for rev 56

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//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// MODULE NAME: receive engine                                                                                        ////
////                                                                                                                                                                    ////
//// DESCRIPTION: Receive Engine Top Level for the 10 Gigabit     ////
////     Ethernet MAC.                                                                                                                  ////
////                                                                                                                                                                    ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                                              ////
////                                                                                                                                                                    ////
//// AUTHOR(S):                                                                                                                                 ////
//// Zheng Cao                                                               ////
////                                                                                                    ////
//////////////////////////////////////////////////////////////////////
////                                                                                                                                                                    ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////
////                                                                                                                                                                    ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                                                   ////
////                                                                                                                                                                    ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// No flow control included
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxReceiveEngine(rxclk_in, reset_in, rxd_in, rxc_in, rxStatRegPlus,
                       cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
                       rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
    input rxclk_in; //Input clock of receive engine
    input reset_in; //Globle reset of receive engine
    input [31:0] rxd_in; //XGMII RXD
    input [3:0] rxc_in;  //XGMII RXC
    output [17:0] rxStatRegPlus; //Signals for statistics        
    input [64:0] cfgRxRegData_in; //Signals for configuration
    output [63:0] rx_data; //Received data sent to upper layer
    output [7:0] rx_data_valid; //Receive data valid indicator
    output rx_good_frame; //Indicate that a good frame has been received
    output rx_bad_frame; //Indicate that a bad frame has been received
         output[2:0] rxCfgofRS; //
    output [1:0] rxTxLinkFault;
         output rxclk_out;
//       output [31:0] fcTxPauseData;
//       output fcTxPauseValid;
 
         parameter TP =1;
 
    wire rxclk;
         wire rxclk_180;
         wire locked;
         wire reset_dcm;
         wire reset;
 
         reg [47:0]MAC_Addr;     //MAC Address used in receiving control frame.
    reg      vlan_enable; //VLAN Enable
         reg      recv_enable; //Receiver Enable
         reg      inband_fcs;   //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client
         reg      jumbo_enable;//Jumbo Frame Enable
         reg      recv_rst;             //Receiver reset
 
         wire start_da, start_lt;
         wire tagged_frame;
         wire pause_frame;
         wire [47:0] da_addr;
//       wire [15:0] lt_data;
         wire [`COUNTER_WIDTH-1:0] frame_cnt;
         wire [2:0]  terminator_location;
         wire get_sfd,get_error_code,get_terminator, get_terminator_d1;
         wire receiving;
         wire receiving_d1,receiving_d2;
 
 
         wire length_error;
         wire large_error;
         wire small_error;
         wire padded_frame;
         wire length_65_127;
         wire length_128_255;
         wire length_256_511;
         wire length_512_1023;
         wire length_1024_max;
         wire jumbo_frame;
 
         wire local_invalid;
         wire broad_valid;
         wire multi_valid;
 
         wire good_frame_get, bad_frame_get;
         wire wait_crc_check;
 
         wire crc_check_valid;
         wire crc_check_invalid;
         wire check_reset;
 
         wire [1:0]link_fault;
 
         //////////////////////////////////////////
         // Input Registers
         //////////////////////////////////////////
 
         wire [63:0] rxd64;
         wire [63:0] CRC_DATA;
         wire [7:0] rxc8;
 
         assign rxTxLinkFault = link_fault;
//       assign fcTxPauseValid = pause_frame;
 
 
         //////////////////////////////////////////
         // Read Receiver Configuration Word
         //////////////////////////////////////////
 
         reg[52:0] cfgRxRegData;
         always@(posedge rxclk or posedge reset)begin
                if(reset)
                             cfgRxRegData <=#TP 0;
                          else
                             cfgRxRegData<=#TP cfgRxRegData_in;
         end
 
         always@(posedge rxclk or posedge reset)begin
                if(reset) begin
                             MAC_Addr <= 0;
                   vlan_enable <= 0;
                   recv_enable <= 0;
                   inband_fcs  <= 0;
                   jumbo_enable <= 0;
                   recv_rst <= 0;
                          end
                          else begin
                             MAC_Addr <= cfgRxRegData[47:0];
                   vlan_enable <= cfgRxRegData[48];
                   recv_enable <= cfgRxRegData[49];
                   inband_fcs  <= cfgRxRegData[50];
                   jumbo_enable <= cfgRxRegData[51];
                   recv_rst <= cfgRxRegData[52];
                          end
    end
     //////////////////////////////////////////////////
         // Used to count number of received frames(G&B)
         //////////////////////////////////////////////////
         reg[7:0] cnt;
         reg cnt_en;
         always@(posedge rxclk or posedge reset) begin
               if (reset)
                            cnt_en <=0;
                         else if(get_sfd)
                  cnt_en <=1;
          else if(rx_bad_frame|rx_good_frame)
             cnt_en <=0;
          else
             cnt_en <=cnt_en;
    end
 
    always@(posedge rxclk or posedge reset) begin
          if (reset)
             cnt <=0;
          else if(cnt_en)
             cnt<=cnt + 1;
          else
             cnt <=0;
    end
 
         /////////////////////////////////////////
         // Reset signals
         /////////////////////////////////////////
         assign  reset_dcm = reset_in | recv_rst;
         assign  reset = ~locked;
 
         /////////////////////////////////////////
         // Write Configuration Words   of RS 
         /////////////////////////////////////////
 
         assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault
         assign rxCfgofRS[1] = link_fault[0] & link_fault[1];  //get remote fault
         assign rxCfgofRS[2] = locked;  //Receive DCM locked
 
         ////////////////////////////////////////
         // Signals for Pause Operation
         ////////////////////////////////////////
         assign fcTxPauseValid = pause_frame;
//       assign fcTxPauseData = {16{1'b0},rxd64[15:0]};
 
         ////////////////////////////////////////
         // Receive Clock Generator
         //////////////////////////////////////// 
    assign rxclk_out = rxclk;
         rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
                            .reset(reset_dcm),
                                                          .rxclk(rxclk),    // system clock
                                                          .rxclk_180(rxclk_180), //reversed clock
                                                          .locked(locked)
                                                          );
 
         //////////////////////////////////////
    // Rx Engine DataPath
         //////////////////////////////////////
         rxDataPath datapath_main(.rxclk(rxclk), .reset(reset), .rxd64(rxd64), .rxc8(rxc8), .inband_fcs(inband_fcs), .receiving(receiving),
                                  .start_da(start_da), .start_lt(start_lt), .wait_crc_check(wait_crc_check), .get_sfd(get_sfd),
                             .get_terminator(get_terminator), .get_error_code(get_error_code), .tagged_frame(tagged_frame), .pause_frame(pause_frame),
                                                                          .da_addr(da_addr), .terminator_location(terminator_location), .CRC_DATA(CRC_DATA), .rx_data_valid(rx_data_valid),
                                                                          .rx_data(rx_data), .get_terminator_d1(get_terminator_d1),.bad_frame_get(bad_frame_get),.good_frame_get(good_frame_get),
                                                                          .check_reset(check_reset),.rx_good_frame(rx_good_frame),.rx_bad_frame(rx_bad_frame));//,.fcTxPauseData(fcTxPauseData));
 
         //////////////////////////////////////
         // Destination Address Checker
         //////////////////////////////////////
 
         rxDAchecker  dachecker(.rxclk(rxclk), .reset(reset), .local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),
                                .da_addr(da_addr));
 
    /////////////////////////////////////
         // Length/Type field checker
         /////////////////////////////////////
 
         rxLenTypChecker lenchecker(.rxclk(rxclk), .reset(reset), .get_terminator(get_terminator), .terminator_location(terminator_location),
                                    .jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame), .frame_cnt(frame_cnt), .vlan_enable(vlan_enable),
                                                                                 .length_error(length_error), .large_error(large_error),.small_error(small_error), .padded_frame(padded_frame),
                                                        .length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),
                                                        .length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame)
                                                                                 );
 
         /////////////////////////////////////
         // Counters used in Receive Engine
         /////////////////////////////////////
 
    rxNumCounter counters(.rxclk(rxclk), .reset(reset), .receiving(receiving), .frame_cnt(frame_cnt));
 
         /////////////////////////////////////
         // State Machine in Receive Process
         /////////////////////////////////////
 
    rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid),
                                     .length_error(length_error), .crc_check_valid(crc_check_valid), .crc_check_invalid(crc_check_invalid),
                                .start_da(start_da), .start_lt(start_lt), .receiving(receiving),.good_frame_get(good_frame_get),
                                                                                  .bad_frame_get(bad_frame_get), .get_error_code(get_error_code), .wait_crc_check(wait_crc_check), .get_terminator(get_terminator),
                                                                                  .receiving_d1(receiving_d1),.check_reset(check_reset));
 
         /////////////////////////////////////
         // CRC Check module
         /////////////////////////////////////
         rxCRC crcmodule(.rxclk(rxclk), .reset(reset), .CRC_DATA(CRC_DATA), .get_terminator(get_terminator), .terminator_location(terminator_location),
                         .crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
                                                  .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
    /////////////////////////////////////
         // RS Layer
         /////////////////////////////////////
    rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(rxd_in), .rxc_in(rxc_in));
 
         /////////////////////////////////////
         // Statistic module
         /////////////////////////////////////
         rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),
                 .receiving(receiving), .padded_frame(padded_frame), .pause_frame(pause_frame), .broad_valid(broad_valid), .multi_valid(multi_valid),
                                          .length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),
                                          .length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame),.get_error_code(get_error_code), .rxStatRegPlus(rxStatRegPlus));
endmodule

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.v] - Blame information for rev 56

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MODULE NAME: receive engine ////`
4			`//// ////`
5			`//// DESCRIPTION: Receive Engine Top Level for the 10 Gigabit ////`
6			`//// Ethernet MAC. ////`
7			`//// ////`
8			`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
9			`//// http://www.opencores.org/projects/ethmac10g/ ////`
10			`//// ////`
11			`//// AUTHOR(S): ////`
12			`//// Zheng Cao ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS REVISION HISTORY:`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
45			`// No flow control included`
46			`//`
47			`//`
48			`//////////////////////////////////////////////////////////////////////`
49
50			`include "timescale.v"
51			`include "xgiga_define.v"
52
53			`module rxReceiveEngine(rxclk_in, reset_in, rxd_in, rxc_in, rxStatRegPlus,`
54	56	fisher5090	`cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,`
55	39	fisher5090	`rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);`
56			`input rxclk_in; //Input clock of receive engine`
57			`input reset_in; //Globle reset of receive engine`
58			`input [31:0] rxd_in; //XGMII RXD`
59			`input [3:0] rxc_in; //XGMII RXC`
60	56	fisher5090	`output [17:0] rxStatRegPlus; //Signals for statistics`
61	39	fisher5090	`input [64:0] cfgRxRegData_in; //Signals for configuration`
62			`output [63:0] rx_data; //Received data sent to upper layer`
63			`output [7:0] rx_data_valid; //Receive data valid indicator`
64			`output rx_good_frame; //Indicate that a good frame has been received`
65			`output rx_bad_frame; //Indicate that a bad frame has been received`
66			`output[2:0] rxCfgofRS; //`
67			`output [1:0] rxTxLinkFault;`
68	56	fisher5090	`output rxclk_out;`
69	39	fisher5090	`// output [31:0] fcTxPauseData;`
70			`// output fcTxPauseValid;`
71
72			`parameter TP =1;`
73
74			`wire rxclk;`
75			`wire rxclk_180;`
76			`wire locked;`
77			`wire reset_dcm;`
78			`wire reset;`
79
80			`reg [47:0]MAC_Addr; //MAC Address used in receiving control frame.`
81			`reg vlan_enable; //VLAN Enable`
82			`reg recv_enable; //Receiver Enable`
83			`reg inband_fcs; //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client`
84			`reg jumbo_enable;//Jumbo Frame Enable`
85			`reg recv_rst; //Receiver reset`
86
87			`wire start_da, start_lt;`
88			`wire tagged_frame;`
89			`wire pause_frame;`
90			`wire [47:0] da_addr;`
91			`// wire [15:0] lt_data;`
92			wire [`COUNTER_WIDTH-1:0] frame_cnt;
93			`wire [2:0] terminator_location;`
94			`wire get_sfd,get_error_code,get_terminator, get_terminator_d1;`
95			`wire receiving;`
96			`wire receiving_d1,receiving_d2;`
97
98
99			`wire length_error;`
100			`wire large_error;`
101			`wire small_error;`
102			`wire padded_frame;`
103			`wire length_65_127;`
104			`wire length_128_255;`
105			`wire length_256_511;`
106			`wire length_512_1023;`
107			`wire length_1024_max;`
108			`wire jumbo_frame;`
109
110			`wire local_invalid;`
111			`wire broad_valid;`
112			`wire multi_valid;`
113
114			`wire good_frame_get, bad_frame_get;`
115			`wire wait_crc_check;`
116
117			`wire crc_check_valid;`
118			`wire crc_check_invalid;`
119			`wire check_reset;`
120
121			`wire [1:0]link_fault;`
122
123			`//////////////////////////////////////////`
124			`// Input Registers`
125			`//////////////////////////////////////////`
126
127			`wire [63:0] rxd64;`
128			`wire [63:0] CRC_DATA;`
129			`wire [7:0] rxc8;`
130
131			`assign rxTxLinkFault = link_fault;`
132			`// assign fcTxPauseValid = pause_frame;`
133
134
135			`//////////////////////////////////////////`
136			`// Read Receiver Configuration Word`
137			`//////////////////////////////////////////`
138
139			`reg[52:0] cfgRxRegData;`
140			`always@(posedge rxclk or posedge reset)begin`
141			`if(reset)`
142			`cfgRxRegData <=#TP 0;`
143			`else`
144			`cfgRxRegData<=#TP cfgRxRegData_in;`
145			`end`
146
147			`always@(posedge rxclk or posedge reset)begin`
148			`if(reset) begin`
149			`MAC_Addr <= 0;`
150			`vlan_enable <= 0;`
151			`recv_enable <= 0;`
152			`inband_fcs <= 0;`
153			`jumbo_enable <= 0;`
154			`recv_rst <= 0;`
155			`end`
156			`else begin`
157			`MAC_Addr <= cfgRxRegData[47:0];`
158			`vlan_enable <= cfgRxRegData[48];`
159			`recv_enable <= cfgRxRegData[49];`
160			`inband_fcs <= cfgRxRegData[50];`
161			`jumbo_enable <= cfgRxRegData[51];`
162			`recv_rst <= cfgRxRegData[52];`
163			`end`
164			`end`
165			`//////////////////////////////////////////////////`
166			`// Used to count number of received frames(G&B)`
167			`//////////////////////////////////////////////////`
168			`reg[7:0] cnt;`
169			`reg cnt_en;`
170			`always@(posedge rxclk or posedge reset) begin`
171			`if (reset)`
172			`cnt_en <=0;`
173			`else if(get_sfd)`
174			`cnt_en <=1;`
175			`else if(rx_bad_frame\|rx_good_frame)`
176			`cnt_en <=0;`
177			`else`
178			`cnt_en <=cnt_en;`
179			`end`
180
181			`always@(posedge rxclk or posedge reset) begin`
182			`if (reset)`
183			`cnt <=0;`
184			`else if(cnt_en)`
185			`cnt<=cnt + 1;`
186			`else`
187			`cnt <=0;`
188			`end`
189
190			`/////////////////////////////////////////`
191			`// Reset signals`
192			`/////////////////////////////////////////`
193			`assign reset_dcm = reset_in \| recv_rst;`
194			`assign reset = ~locked;`
195
196			`/////////////////////////////////////////`
197			`// Write Configuration Words of RS`
198			`/////////////////////////////////////////`
199
200			`assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault`
201			`assign rxCfgofRS[1] = link_fault[0] & link_fault[1]; //get remote fault`
202			`assign rxCfgofRS[2] = locked; //Receive DCM locked`
203
204			`////////////////////////////////////////`
205			`// Signals for Pause Operation`
206			`////////////////////////////////////////`
207			`assign fcTxPauseValid = pause_frame;`
208			`// assign fcTxPauseData = {16{1'b0},rxd64[15:0]};`
209
210			`////////////////////////////////////////`
211			`// Receive Clock Generator`
212			`////////////////////////////////////////`
213	56	fisher5090	`assign rxclk_out = rxclk;`
214	39	fisher5090	`rxClkgen rxclk_gen(.rxclk_in(rxclk_in),`
215			`.reset(reset_dcm),`
216			`.rxclk(rxclk), // system clock`
217			`.rxclk_180(rxclk_180), //reversed clock`
218			`.locked(locked)`
219			`);`
220
221			`//////////////////////////////////////`
222			`// Rx Engine DataPath`
223			`//////////////////////////////////////`
224			`rxDataPath datapath_main(.rxclk(rxclk), .reset(reset), .rxd64(rxd64), .rxc8(rxc8), .inband_fcs(inband_fcs), .receiving(receiving),`
225			`.start_da(start_da), .start_lt(start_lt), .wait_crc_check(wait_crc_check), .get_sfd(get_sfd),`
226			`.get_terminator(get_terminator), .get_error_code(get_error_code), .tagged_frame(tagged_frame), .pause_frame(pause_frame),`
227			`.da_addr(da_addr), .terminator_location(terminator_location), .CRC_DATA(CRC_DATA), .rx_data_valid(rx_data_valid),`
228			`.rx_data(rx_data), .get_terminator_d1(get_terminator_d1),.bad_frame_get(bad_frame_get),.good_frame_get(good_frame_get),`
229			`.check_reset(check_reset),.rx_good_frame(rx_good_frame),.rx_bad_frame(rx_bad_frame));//,.fcTxPauseData(fcTxPauseData));`
230
231			`//////////////////////////////////////`
232			`// Destination Address Checker`
233			`//////////////////////////////////////`
234
235			`rxDAchecker dachecker(.rxclk(rxclk), .reset(reset), .local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),`
236			`.da_addr(da_addr));`
237
238			`/////////////////////////////////////`
239			`// Length/Type field checker`
240			`/////////////////////////////////////`
241
242			`rxLenTypChecker lenchecker(.rxclk(rxclk), .reset(reset), .get_terminator(get_terminator), .terminator_location(terminator_location),`
243			`.jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame), .frame_cnt(frame_cnt), .vlan_enable(vlan_enable),`
244			`.length_error(length_error), .large_error(large_error),.small_error(small_error), .padded_frame(padded_frame),`
245			`.length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),`
246			`.length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame)`
247			`);`
248
249			`/////////////////////////////////////`
250			`// Counters used in Receive Engine`
251			`/////////////////////////////////////`
252
253			`rxNumCounter counters(.rxclk(rxclk), .reset(reset), .receiving(receiving), .frame_cnt(frame_cnt));`
254
255			`/////////////////////////////////////`
256			`// State Machine in Receive Process`
257			`/////////////////////////////////////`
258
259			`rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid),`
260			`.length_error(length_error), .crc_check_valid(crc_check_valid), .crc_check_invalid(crc_check_invalid),`
261			`.start_da(start_da), .start_lt(start_lt), .receiving(receiving),.good_frame_get(good_frame_get),`
262			`.bad_frame_get(bad_frame_get), .get_error_code(get_error_code), .wait_crc_check(wait_crc_check), .get_terminator(get_terminator),`
263			`.receiving_d1(receiving_d1),.check_reset(check_reset));`
264
265			`/////////////////////////////////////`
266			`// CRC Check module`
267			`/////////////////////////////////////`
268			`rxCRC crcmodule(.rxclk(rxclk), .reset(reset), .CRC_DATA(CRC_DATA), .get_terminator(get_terminator), .terminator_location(terminator_location),`
269			`.crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),`
270			`.get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));`
271			`/////////////////////////////////////`
272			`// RS Layer`
273			`/////////////////////////////////////`
274			`rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(rxd_in), .rxc_in(rxc_in));`
275
276			`/////////////////////////////////////`
277			`// Statistic module`
278			`/////////////////////////////////////`
279			`rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),`
280			`.receiving(receiving), .padded_frame(padded_frame), .pause_frame(pause_frame), .broad_valid(broad_valid), .multi_valid(multi_valid),`
281			`.length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),`
282			`.length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame),.get_error_code(get_error_code), .rxStatRegPlus(rxStatRegPlus));`
283			`endmodule`