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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.v] - Blame information for rev 72

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: receive engine                                  ////
////                                                              ////
//// DESCRIPTION: Receive Engine Top Level for the 10 Gigabit     ////
////     Ethernet MAC.                                            ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2006/06/16 06:39:59  fisher5090
// no message
//
// Revision 1.5  2006/06/16 06:36:28  Zheng Cao
// no message
//
// Revision 1.4  2006/06/12 10:02:19  Zheng Cao
// change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk
//
// Revision 1.3  2006/06/11 12:15:11  Zheng Cao
// no message
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// No flow control included
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxReceiveEngine(xgmii_rxclk, rxclk_2x, reset_in, xgmii_rxd, xgmii_rxc, rxStatRegPlus,
                       cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
                       rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
    input xgmii_rxclk; //Input clock of receive engine
    input rxclk_2x;
    input reset_in; //Globle reset of receive engine
    input [31:0] xgmii_rxd; //XGMII RXD
    input [3:0] xgmii_rxc;  //XGMII RXC
    output [17:0] rxStatRegPlus; //Signals for statistics        
    input [64:0] cfgRxRegData_in; //Signals for configuration
    output [63:0] rx_data; //Received data sent to upper layer
    output [7:0] rx_data_valid; //Receive data valid indicator
    output rx_good_frame; //Indicate that a good frame has been received
    output rx_bad_frame; //Indicate that a bad frame has been received
    output[2:0] rxCfgofRS; //
    output [1:0] rxTxLinkFault;
    output rxclk_out;
//  output [31:0] fcTxPauseData;
//  output fcTxPauseValid;
 
    parameter TP =1;
 
    wire rxclk;
    wire rxclk_180;
    wire locked;
    wire reset_dcm;
    wire reset;
 
    reg [47:0]MAC_Addr;  //MAC Address used in receiving control frame.
    reg      vlan_enable; //VLAN Enable
    reg      recv_enable; //Receiver Enable
    reg      inband_fcs;        //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client
    reg      jumbo_enable;//Jumbo Frame Enable
    reg      recv_rst;          //Receiver reset
 
    wire start_da, start_lt;
    wire tagged_frame;
    wire pause_frame;
    wire [47:0] da_addr;
//  wire [15:0] lt_data;
    wire [`COUNTER_WIDTH-1:0] frame_cnt;
    wire [2:0]  terminator_location;
    wire get_sfd,get_error_code,get_terminator, get_terminator_d1;
    wire receiving;
    wire receiving_d1,receiving_d2;
 
 
    wire length_error;
    wire large_error;
    wire small_error;
    wire padded_frame;
    wire length_65_127;
    wire length_128_255;
    wire length_256_511;
    wire length_512_1023;
    wire length_1024_max;
    wire jumbo_frame;
 
    wire local_invalid;
    wire broad_valid;
    wire multi_valid;
 
    wire good_frame_get, bad_frame_get;
    wire wait_crc_check;
 
    wire crc_check_valid;
    wire crc_check_invalid;
    wire check_reset;
 
    wire [1:0]link_fault;
 
    //////////////////////////////////////////
    // Input Registers
    //////////////////////////////////////////
 
    wire [63:0] rxd64;
    wire [63:0] CRC_DATA;
    wire [7:0] rxc8;
 
    assign rxTxLinkFault = link_fault;
    // assign fcTxPauseValid = pause_frame;
 
 
    //////////////////////////////////////////
    // Read Receiver Configuration Word
    //////////////////////////////////////////
 
    reg[52:0] cfgRxRegData;
    always@(posedge rxclk or posedge reset)begin
          if(reset)
            cfgRxRegData <=#TP 0;
          else
            cfgRxRegData<=#TP cfgRxRegData_in;
    end
 
    always@(posedge rxclk or posedge reset)begin
          if(reset) begin
            MAC_Addr <= 0;
            vlan_enable <= 0;
            recv_enable <= 0;
            inband_fcs  <= 0;
            jumbo_enable <= 0;
            recv_rst <= 0;
          end
          else begin
            MAC_Addr <= cfgRxRegData[47:0];
            vlan_enable <= cfgRxRegData[48];
            recv_enable <= cfgRxRegData[49];
            inband_fcs  <= cfgRxRegData[50];
            jumbo_enable <= cfgRxRegData[51];
            recv_rst <= cfgRxRegData[52];
          end
    end
    //////////////////////////////////////////////////
    // Used to count number of received frames(G&B)
    //////////////////////////////////////////////////
    reg[7:0] cnt;
    reg cnt_en;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           cnt_en <=0;
         else if(get_sfd)
           cnt_en <=1;
         else if(rx_bad_frame|rx_good_frame)
           cnt_en <=0;
         else
           cnt_en <=cnt_en;
    end
 
    always@(posedge rxclk or posedge reset) begin
          if (reset)
             cnt <=0;
          else if(cnt_en)
             cnt<=cnt + 1;
          else
             cnt <=0;
    end
 
   /////////////////////////////////////////
   // Reset signals
   /////////////////////////////////////////
   assign  reset_dcm = reset_in | recv_rst;
   assign  reset = ~locked;
 
   /////////////////////////////////////////
   // Write Configuration Words of RS 
   /////////////////////////////////////////
 
   assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault
   assign rxCfgofRS[1] = link_fault[0] & link_fault[1];  //get remote fault
   assign rxCfgofRS[2] = locked;  //Receive DCM locked
 
   ////////////////////////////////////////
   // Signals for Pause Operation
   ////////////////////////////////////////
   assign fcTxPauseValid = pause_frame;
// assign fcTxPauseData = {16{1'b0},rxd64[15:0]};
 
   ////////////////////////////////////////
   // Receive Clock Generator
   //////////////////////////////////////// 
   assign rxclk_out = rxclk;
   rxClkgen rxclk_gen(.rxclk_in(xgmii_rxclk),
                .reset(reset_dcm),
                .rxclk(rxclk),    // system clock
                .rxclk_180(rxclk_180), //reversed clock
                .locked(locked)
                 );
 
   //////////////////////////////////////
   // Rx Engine DataPath
   //////////////////////////////////////
   rxDataPath datapath_main(.rxclk(rxclk), .reset(reset), .rxd64(rxd64), .rxc8(rxc8), .inband_fcs(inband_fcs), .receiving(receiving),
                            .start_da(start_da), .start_lt(start_lt), .wait_crc_check(wait_crc_check), .get_sfd(get_sfd),
                             .get_terminator(get_terminator), .get_error_code(get_error_code), .tagged_frame(tagged_frame), .pause_frame(pause_frame),
                    .da_addr(da_addr), .terminator_location(terminator_location), .CRC_DATA(CRC_DATA), .rx_data_valid(rx_data_valid),
                    .rx_data(rx_data), .get_terminator_d1(get_terminator_d1),.bad_frame_get(bad_frame_get),.good_frame_get(good_frame_get),
                    .check_reset(check_reset),.rx_good_frame(rx_good_frame),.rx_bad_frame(rx_bad_frame));//,.fcTxPauseData(fcTxPauseData));
 
   //////////////////////////////////////
   // Destination Address Checker
   //////////////////////////////////////
 
   rxDAchecker  dachecker(.rxclk(rxclk), .reset(reset), .local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),
                          .da_addr(da_addr));
 
   /////////////////////////////////////
   // Length/Type field checker
   /////////////////////////////////////
 
   rxLenTypChecker lenchecker(.rxclk(rxclk), .reset(reset), .get_terminator(get_terminator), .terminator_location(terminator_location),
                     .jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame), .frame_cnt(frame_cnt), .vlan_enable(vlan_enable),
                     .length_error(length_error), .large_error(large_error),.small_error(small_error), .padded_frame(padded_frame),
                     .length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),
                          .length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame)
 );
 
   /////////////////////////////////////
   // Counters used in Receive Engine
   /////////////////////////////////////
 
    rxNumCounter counters(.rxclk(rxclk), .reset(reset), .receiving(receiving), .frame_cnt(frame_cnt));
 
   /////////////////////////////////////
   // State Machine in Receive Process
   /////////////////////////////////////
 
    rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid),
                                .length_error(length_error), .crc_check_valid(crc_check_valid), .crc_check_invalid(crc_check_invalid),
                               .start_da(start_da), .start_lt(start_lt), .receiving(receiving),.good_frame_get(good_frame_get),
                               .bad_frame_get(bad_frame_get), .get_error_code(get_error_code), .wait_crc_check(wait_crc_check), .get_terminator(get_terminator),
                               .receiving_d1(receiving_d1),.check_reset(check_reset));
 
   /////////////////////////////////////
   // CRC Check module
   /////////////////////////////////////
   rxCRC crcmodule(.rxclk(rxclk), .reset(reset), .CRC_DATA(CRC_DATA), .get_terminator(get_terminator), .terminator_location(terminator_location),
                   .crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
                   .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
   /////////////////////////////////////
   // RS Layer
   /////////////////////////////////////
    rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .rxclk_2x(rxclk_2x), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(xgmii_rxd), .rxc_in(xgmii_rxc));
 
   /////////////////////////////////////
   // Statistic module
   /////////////////////////////////////
   rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),
                 .receiving(receiving), .padded_frame(padded_frame), .pause_frame(pause_frame), .broad_valid(broad_valid), .multi_valid(multi_valid),
                 .length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),
                 .length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame),.get_error_code(get_error_code), .rxStatRegPlus(rxStatRegPlus));
endmodule

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2	70	fisher5090	`//// ////`
3			`//// MODULE NAME: receive engine ////`
4			`//// ////`
5	39	fisher5090	`//// DESCRIPTION: Receive Engine Top Level for the 10 Gigabit ////`
6	70	fisher5090	`//// Ethernet MAC. ////`
7			`//// ////`
8	39	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
9	70	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
10			`//// ////`
11			`//// AUTHOR(S): ////`
12			`//// Zheng Cao ////`
13			`//// ////`
14	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
15	70	fisher5090	`//// ////`
16			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
17			`//// ////`
18	39	fisher5090	`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37	70	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS REVISION HISTORY:`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	71	fisher5090	`// Revision 1.6 2006/06/16 06:39:59 fisher5090`
45			`// no message`
46			`//`
47	70	fisher5090	`// Revision 1.5 2006/06/16 06:36:28 Zheng Cao`
48			`// no message`
49			`//`
50			`// Revision 1.4 2006/06/12 10:02:19 Zheng Cao`
51	69	fisher5090	`// change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk`
52			`//`
53	70	fisher5090	`// Revision 1.3 2006/06/11 12:15:11 Zheng Cao`
54	60	fisher5090	`// no message`
55			`//`
56	39	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
57			`// No flow control included`
58			`//`
59			`//`
60			`//////////////////////////////////////////////////////////////////////`
61
62			`include "timescale.v"
63			`include "xgiga_define.v"
64
65	71	fisher5090	`module rxReceiveEngine(xgmii_rxclk, rxclk_2x, reset_in, xgmii_rxd, xgmii_rxc, rxStatRegPlus,`
66	56	fisher5090	`cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,`
67	39	fisher5090	`rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);`
68	60	fisher5090	`input xgmii_rxclk; //Input clock of receive engine`
69	71	fisher5090	`input rxclk_2x;`
70	39	fisher5090	`input reset_in; //Globle reset of receive engine`
71	60	fisher5090	`input [31:0] xgmii_rxd; //XGMII RXD`
72			`input [3:0] xgmii_rxc; //XGMII RXC`
73	56	fisher5090	`output [17:0] rxStatRegPlus; //Signals for statistics`
74	39	fisher5090	`input [64:0] cfgRxRegData_in; //Signals for configuration`
75			`output [63:0] rx_data; //Received data sent to upper layer`
76			`output [7:0] rx_data_valid; //Receive data valid indicator`
77			`output rx_good_frame; //Indicate that a good frame has been received`
78			`output rx_bad_frame; //Indicate that a bad frame has been received`
79	69	fisher5090	`output[2:0] rxCfgofRS; //`
80	39	fisher5090	`output [1:0] rxTxLinkFault;`
81	69	fisher5090	`output rxclk_out;`
82			`// output [31:0] fcTxPauseData;`
83			`// output fcTxPauseValid;`
84	39	fisher5090
85	69	fisher5090	`parameter TP =1;`
86	39	fisher5090
87			`wire rxclk;`
88	69	fisher5090	`wire rxclk_180;`
89			`wire locked;`
90			`wire reset_dcm;`
91			`wire reset;`
92	39	fisher5090
93	69	fisher5090	`reg [47:0]MAC_Addr; //MAC Address used in receiving control frame.`
94	39	fisher5090	`reg vlan_enable; //VLAN Enable`
95	69	fisher5090	`reg recv_enable; //Receiver Enable`
96			`reg inband_fcs; //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client`
97			`reg jumbo_enable;//Jumbo Frame Enable`
98			`reg recv_rst; //Receiver reset`
99	39	fisher5090
100	69	fisher5090	`wire start_da, start_lt;`
101			`wire tagged_frame;`
102			`wire pause_frame;`
103			`wire [47:0] da_addr;`
104			`// wire [15:0] lt_data;`
105			wire [`COUNTER_WIDTH-1:0] frame_cnt;
106			`wire [2:0] terminator_location;`
107			`wire get_sfd,get_error_code,get_terminator, get_terminator_d1;`
108			`wire receiving;`
109			`wire receiving_d1,receiving_d2;`
110	39	fisher5090
111	69	fisher5090
112			`wire length_error;`
113			`wire large_error;`
114			`wire small_error;`
115			`wire padded_frame;`
116			`wire length_65_127;`
117			`wire length_128_255;`
118			`wire length_256_511;`
119			`wire length_512_1023;`
120			`wire length_1024_max;`
121			`wire jumbo_frame;`
122	39	fisher5090
123	69	fisher5090	`wire local_invalid;`
124			`wire broad_valid;`
125			`wire multi_valid;`
126	39	fisher5090
127	69	fisher5090	`wire good_frame_get, bad_frame_get;`
128			`wire wait_crc_check;`
129	39	fisher5090
130	69	fisher5090	`wire crc_check_valid;`
131			`wire crc_check_invalid;`
132			`wire check_reset;`
133	39	fisher5090
134	69	fisher5090	`wire [1:0]link_fault;`
135	39	fisher5090
136	69	fisher5090	`//////////////////////////////////////////`
137			`// Input Registers`
138			`//////////////////////////////////////////`
139
140			`wire [63:0] rxd64;`
141			`wire [63:0] CRC_DATA;`
142			`wire [7:0] rxc8;`
143	39	fisher5090
144	69	fisher5090	`assign rxTxLinkFault = link_fault;`
145			`// assign fcTxPauseValid = pause_frame;`
146
147
148			`//////////////////////////////////////////`
149			`// Read Receiver Configuration Word`
150			`//////////////////////////////////////////`
151
152			`reg[52:0] cfgRxRegData;`
153			`always@(posedge rxclk or posedge reset)begin`
154			`if(reset)`
155			`cfgRxRegData <=#TP 0;`
156	39	fisher5090	`else`
157	69	fisher5090	`cfgRxRegData<=#TP cfgRxRegData_in;`
158	39	fisher5090	`end`
159	69	fisher5090
160			`always@(posedge rxclk or posedge reset)begin`
161			`if(reset) begin`
162			`MAC_Addr <= 0;`
163			`vlan_enable <= 0;`
164			`recv_enable <= 0;`
165			`inband_fcs <= 0;`
166			`jumbo_enable <= 0;`
167			`recv_rst <= 0;`
168			`end`
169			`else begin`
170			`MAC_Addr <= cfgRxRegData[47:0];`
171			`vlan_enable <= cfgRxRegData[48];`
172			`recv_enable <= cfgRxRegData[49];`
173			`inband_fcs <= cfgRxRegData[50];`
174			`jumbo_enable <= cfgRxRegData[51];`
175			`recv_rst <= cfgRxRegData[52];`
176			`end`
177			`end`
178			`//////////////////////////////////////////////////`
179			`// Used to count number of received frames(G&B)`
180			`//////////////////////////////////////////////////`
181			`reg[7:0] cnt;`
182			`reg cnt_en;`
183			`always@(posedge rxclk or posedge reset) begin`
184			`if (reset)`
185			`cnt_en <=0;`
186			`else if(get_sfd)`
187			`cnt_en <=1;`
188			`else if(rx_bad_frame\|rx_good_frame)`
189			`cnt_en <=0;`
190			`else`
191			`cnt_en <=cnt_en;`
192			`end`
193	39	fisher5090
194			`always@(posedge rxclk or posedge reset) begin`
195			`if (reset)`
196			`cnt <=0;`
197			`else if(cnt_en)`
198			`cnt<=cnt + 1;`
199			`else`
200			`cnt <=0;`
201	69	fisher5090	`end`
202
203			`/////////////////////////////////////////`
204			`// Reset signals`
205			`/////////////////////////////////////////`
206			`assign reset_dcm = reset_in \| recv_rst;`
207			`assign reset = ~locked;`
208
209			`/////////////////////////////////////////`
210			`// Write Configuration Words of RS`
211			`/////////////////////////////////////////`
212	39	fisher5090
213	69	fisher5090	`assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault`
214			`assign rxCfgofRS[1] = link_fault[0] & link_fault[1]; //get remote fault`
215			`assign rxCfgofRS[2] = locked; //Receive DCM locked`
216
217			`////////////////////////////////////////`
218			`// Signals for Pause Operation`
219			`////////////////////////////////////////`
220			`assign fcTxPauseValid = pause_frame;`
221			`// assign fcTxPauseData = {16{1'b0},rxd64[15:0]};`
222	39	fisher5090
223	69	fisher5090	`////////////////////////////////////////`
224			`// Receive Clock Generator`
225			`////////////////////////////////////////`
226			`assign rxclk_out = rxclk;`
227			`rxClkgen rxclk_gen(.rxclk_in(xgmii_rxclk),`
228			`.reset(reset_dcm),`
229			`.rxclk(rxclk), // system clock`
230			`.rxclk_180(rxclk_180), //reversed clock`
231			`.locked(locked)`
232			`);`
233
234			`//////////////////////////////////////`
235			`// Rx Engine DataPath`
236			`//////////////////////////////////////`
237			`rxDataPath datapath_main(.rxclk(rxclk), .reset(reset), .rxd64(rxd64), .rxc8(rxc8), .inband_fcs(inband_fcs), .receiving(receiving),`
238			`.start_da(start_da), .start_lt(start_lt), .wait_crc_check(wait_crc_check), .get_sfd(get_sfd),`
239	39	fisher5090	`.get_terminator(get_terminator), .get_error_code(get_error_code), .tagged_frame(tagged_frame), .pause_frame(pause_frame),`
240	69	fisher5090	`.da_addr(da_addr), .terminator_location(terminator_location), .CRC_DATA(CRC_DATA), .rx_data_valid(rx_data_valid),`
241			`.rx_data(rx_data), .get_terminator_d1(get_terminator_d1),.bad_frame_get(bad_frame_get),.good_frame_get(good_frame_get),`
242			`.check_reset(check_reset),.rx_good_frame(rx_good_frame),.rx_bad_frame(rx_bad_frame));//,.fcTxPauseData(fcTxPauseData));`
243
244			`//////////////////////////////////////`
245			`// Destination Address Checker`
246			`//////////////////////////////////////`
247	39	fisher5090
248	69	fisher5090	`rxDAchecker dachecker(.rxclk(rxclk), .reset(reset), .local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),`
249			`.da_addr(da_addr));`
250	39	fisher5090
251	69	fisher5090	`/////////////////////////////////////`
252			`// Length/Type field checker`
253			`/////////////////////////////////////`
254	39	fisher5090
255	69	fisher5090	`rxLenTypChecker lenchecker(.rxclk(rxclk), .reset(reset), .get_terminator(get_terminator), .terminator_location(terminator_location),`
256			`.jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame), .frame_cnt(frame_cnt), .vlan_enable(vlan_enable),`
257			`.length_error(length_error), .large_error(large_error),.small_error(small_error), .padded_frame(padded_frame),`
258			`.length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),`
259			`.length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame)`
260			`);`
261	39	fisher5090
262	69	fisher5090	`/////////////////////////////////////`
263			`// Counters used in Receive Engine`
264			`/////////////////////////////////////`
265	39	fisher5090
266			`rxNumCounter counters(.rxclk(rxclk), .reset(reset), .receiving(receiving), .frame_cnt(frame_cnt));`
267
268	69	fisher5090	`/////////////////////////////////////`
269			`// State Machine in Receive Process`
270			`/////////////////////////////////////`
271	39	fisher5090
272			`rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid),`
273	69	fisher5090	`.length_error(length_error), .crc_check_valid(crc_check_valid), .crc_check_invalid(crc_check_invalid),`
274			`.start_da(start_da), .start_lt(start_lt), .receiving(receiving),.good_frame_get(good_frame_get),`
275			`.bad_frame_get(bad_frame_get), .get_error_code(get_error_code), .wait_crc_check(wait_crc_check), .get_terminator(get_terminator),`
276			`.receiving_d1(receiving_d1),.check_reset(check_reset));`
277	39	fisher5090
278	69	fisher5090	`/////////////////////////////////////`
279			`// CRC Check module`
280			`/////////////////////////////////////`
281			`rxCRC crcmodule(.rxclk(rxclk), .reset(reset), .CRC_DATA(CRC_DATA), .get_terminator(get_terminator), .terminator_location(terminator_location),`
282			`.crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),`
283			`.get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));`
284			`/////////////////////////////////////`
285			`// RS Layer`
286			`/////////////////////////////////////`
287	71	fisher5090	`rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .rxclk_2x(rxclk_2x), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(xgmii_rxd), .rxc_in(xgmii_rxc));`
288	39	fisher5090
289	69	fisher5090	`/////////////////////////////////////`
290			`// Statistic module`
291			`/////////////////////////////////////`
292			`rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),`
293	39	fisher5090	`.receiving(receiving), .padded_frame(padded_frame), .pause_frame(pause_frame), .broad_valid(broad_valid), .multi_valid(multi_valid),`
294	69	fisher5090	`.length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),`
295			`.length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame),.get_error_code(get_error_code), .rxStatRegPlus(rxStatRegPlus));`
296	39	fisher5090	`endmodule`

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.v] - Blame information for rev 72