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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxStateMachine.v] - Blame information for rev 72

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: rxStateMachine                                  ////
////                                                              ////
//// DESCRIPTION: State Machine of Receive Engine.                ////
////                                                              ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2006/05/31 05:59:43  Zheng Cao
// first version
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, length_error, crc_check_valid, crc_check_invalid,
       start_da, start_lt, receiving, receiving_d1, good_frame_get, bad_frame_get, get_error_code, wait_crc_check,
       get_terminator,check_reset);
 
    input rxclk;
    input reset;
 
    input recv_enable;
 
    //PRE & SFD
    input get_sfd; // SFD has been received;
 
    //DA field 
    input local_invalid;// The Frame's DA field is not Local MAC;
 
    //Length/Type field
    input length_error;//
 
    //FCS field
   input get_terminator;//Indicate end of receiving FCS field;
   input crc_check_valid;//Indicate the frame passed CRC Check;
   input crc_check_invalid;//Indicate the frame failed in CRC Check;
   input get_error_code;
 
   input check_reset;
 
   //DA field
   output start_da;// Start to receive Destination Address;
 
   //Length/Type field
   output start_lt;// Start to receive Length/Type field;
 
    //Receive process control
   output receiving; //Rx Engine is working, not in IDLE state and Check state.
   output receiving_d1;
   output good_frame_get;// A good frame has been received;
   output bad_frame_get; // A bad frame has been received; 
   output wait_crc_check;// 
 
   parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 4;
   parameter rxGetError = 8,    rxIFGWait = 16;
   parameter TP =1;
 
   wire    start_da;
   wire    start_lt;
   wire    receiving;
   reg     good_frame_get;
   reg     bad_frame_get;
 
   reg[4:0] rxstate, rxstate_next;
 
   always@(rxstate, get_sfd, local_invalid, recv_enable,
           get_error_code, length_error, get_terminator, reset)begin
         if (reset) begin
            rxstate_next <=#TP IDLE;
         end
         else begin
             case (rxstate)
                 IDLE: begin //5'b00000;
                     if (get_sfd && recv_enable)
                       rxstate_next <=#TP rxReceiveDA;
                     else
                       rxstate_next <=#TP IDLE;
                 end
                 rxReceiveDA: begin //5'b00001  
                     rxstate_next <=#TP rxReceiveLT;
                 end
                 rxReceiveLT: begin //5'b00010
                     rxstate_next <=#TP rxReceiveData;
                 end
                 rxReceiveData: begin //5'b00100
                     if (local_invalid |length_error| get_error_code)
                       rxstate_next <=#TP rxGetError;
                     else if (get_terminator)
                       rxstate_next <=#TP rxIFGWait;
                     else
                       rxstate_next <=#TP rxReceiveData;
                 end
                 rxGetError: begin //5'b01000
                     if (get_sfd && recv_enable)
                       rxstate_next <=#TP rxReceiveDA;
                     else
                       rxstate_next <=#TP IDLE;
                 end
                 rxIFGWait : begin //5'b10000;
                     if (get_sfd && recv_enable)
                       rxstate_next <=#TP rxReceiveDA;
                     else
                       rxstate_next <=#TP IDLE;
                 end
             endcase
         end
    end
 
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           rxstate <=#TP IDLE;
         else
           rxstate <=#TP rxstate_next;
    end
 
    assign start_da = rxstate[0];
    assign start_lt = rxstate[1];
    assign receiving = rxstate[2] | rxstate[1] | rxstate[0]; // in DA,LT,DATA status
 
    reg receiving_d1;
    always@(posedge rxclk or posedge reset) begin
         if (reset) begin
           receiving_d1<=#TP 0;
         end
         else begin
           receiving_d1<=#TP receiving;
         end
    end
 
    reg  wait_crc_check;
    always@(posedge rxclk or posedge reset) begin
         if (reset)
           wait_crc_check <=#TP 0;
         else if (rxstate[4])
           wait_crc_check <=#TP 1'b1;
         else if (crc_check_valid || crc_check_invalid||length_error)
           wait_crc_check <=#TP 1'b0;
         else
           wait_crc_check <=#TP wait_crc_check;
    end
 
    always@(posedge rxclk or posedge reset)begin
         if (reset)     begin
           bad_frame_get <=#TP 0;
           good_frame_get <=#TP 0;
         end
         else if(rxstate[3] || crc_check_invalid || length_error)begin
           bad_frame_get <=#TP 1'b1;
           good_frame_get <=#TP 1'b0;
         end
         else if (crc_check_valid)begin
           good_frame_get <=#TP 1'b1;
           bad_frame_get <=#TP 1'b0;
         end
         else if (check_reset)begin
           good_frame_get <=#TP 1'b0;
           bad_frame_get <=#TP 1'b0;
         end
    end
endmodule

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	70	fisher5090	`//// MODULE NAME: rxStateMachine ////`
4			`//// ////`
5			`//// DESCRIPTION: State Machine of Receive Engine. ////`
6			`//// ////`
7			`//// ////`
8	39	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
9	70	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
10			`//// ////`
11			`//// AUTHOR(S): ////`
12			`//// Zheng Cao ////`
13			`//// ////`
14	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
15	70	fisher5090	`//// ////`
16			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
17			`//// ////`
18	39	fisher5090	`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37	70	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS REVISION HISTORY:`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	70	fisher5090	`// Revision 1.1.1.1 2006/05/31 05:59:43 Zheng Cao`
45			`// first version`
46			`//`
47	39	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
48			`//`
49			`//`
50			`//`
51			`//////////////////////////////////////////////////////////////////////`
52
53			`include "timescale.v"
54			`include "xgiga_define.v"
55
56			`module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, length_error, crc_check_valid, crc_check_invalid,`
57			`start_da, start_lt, receiving, receiving_d1, good_frame_get, bad_frame_get, get_error_code, wait_crc_check,`
58	70	fisher5090	`get_terminator,check_reset);`
59	39	fisher5090
60	70	fisher5090	`input rxclk;`
61	39	fisher5090	`input reset;`
62
63	70	fisher5090	`input recv_enable;`
64
65			`//PRE & SFD`
66			`input get_sfd; // SFD has been received;`
67
68			`//DA field`
69			`input local_invalid;// The Frame's DA field is not Local MAC;`
70
71			`//Length/Type field`
72			`input length_error;//`
73
74			`//FCS field`
75			`input get_terminator;//Indicate end of receiving FCS field;`
76			`input crc_check_valid;//Indicate the frame passed CRC Check;`
77			`input crc_check_invalid;//Indicate the frame failed in CRC Check;`
78			`input get_error_code;`
79	39	fisher5090
80	70	fisher5090	`input check_reset;`
81
82			`//DA field`
83			`output start_da;// Start to receive Destination Address;`
84
85			`//Length/Type field`
86			`output start_lt;// Start to receive Length/Type field;`
87
88	39	fisher5090	`//Receive process control`
89	70	fisher5090	`output receiving; //Rx Engine is working, not in IDLE state and Check state.`
90			`output receiving_d1;`
91			`output good_frame_get;// A good frame has been received;`
92			`output bad_frame_get; // A bad frame has been received;`
93			`output wait_crc_check;//`
94
95			`parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 4;`
96			`parameter rxGetError = 8, rxIFGWait = 16;`
97			`parameter TP =1;`
98	39	fisher5090
99	70	fisher5090	`wire start_da;`
100			`wire start_lt;`
101			`wire receiving;`
102			`reg good_frame_get;`
103			`reg bad_frame_get;`
104
105			`reg[4:0] rxstate, rxstate_next;`
106	39	fisher5090
107	70	fisher5090	`always@(rxstate, get_sfd, local_invalid, recv_enable,`
108			`get_error_code, length_error, get_terminator, reset)begin`
109			`if (reset) begin`
110			`rxstate_next <=#TP IDLE;`
111			`end`
112			`else begin`
113			`case (rxstate)`
114			`IDLE: begin //5'b00000;`
115			`if (get_sfd && recv_enable)`
116			`rxstate_next <=#TP rxReceiveDA;`
117			`else`
118			`rxstate_next <=#TP IDLE;`
119			`end`
120			`rxReceiveDA: begin //5'b00001`
121			`rxstate_next <=#TP rxReceiveLT;`
122			`end`
123			`rxReceiveLT: begin //5'b00010`
124			`rxstate_next <=#TP rxReceiveData;`
125			`end`
126			`rxReceiveData: begin //5'b00100`
127			`if (local_invalid \|length_error\| get_error_code)`
128			`rxstate_next <=#TP rxGetError;`
129			`else if (get_terminator)`
130			`rxstate_next <=#TP rxIFGWait;`
131			`else`
132			`rxstate_next <=#TP rxReceiveData;`
133			`end`
134			`rxGetError: begin //5'b01000`
135			`if (get_sfd && recv_enable)`
136			`rxstate_next <=#TP rxReceiveDA;`
137			`else`
138			`rxstate_next <=#TP IDLE;`
139			`end`
140			`rxIFGWait : begin //5'b10000;`
141			`if (get_sfd && recv_enable)`
142			`rxstate_next <=#TP rxReceiveDA;`
143			`else`
144			`rxstate_next <=#TP IDLE;`
145			`end`
146			`endcase`
147			`end`
148			`end`
149	39	fisher5090
150	70	fisher5090	`always@(posedge rxclk or posedge reset) begin`
151			`if (reset)`
152			`rxstate <=#TP IDLE;`
153			`else`
154			`rxstate <=#TP rxstate_next;`
155			`end`
156	39	fisher5090
157	70	fisher5090	`assign start_da = rxstate[0];`
158			`assign start_lt = rxstate[1];`
159			`assign receiving = rxstate[2] \| rxstate[1] \| rxstate[0]; // in DA,LT,DATA status`
160
161			`reg receiving_d1;`
162			`always@(posedge rxclk or posedge reset) begin`
163			`if (reset) begin`
164			`receiving_d1<=#TP 0;`
165	39	fisher5090	`end`
166			`else begin`
167	70	fisher5090	`receiving_d1<=#TP receiving;`
168			`end`
169	39	fisher5090	`end`
170	70	fisher5090
171			`reg wait_crc_check;`
172			`always@(posedge rxclk or posedge reset) begin`
173			`if (reset)`
174			`wait_crc_check <=#TP 0;`
175			`else if (rxstate[4])`
176			`wait_crc_check <=#TP 1'b1;`
177			`else if (crc_check_valid \|\| crc_check_invalid\|\|length_error)`
178			`wait_crc_check <=#TP 1'b0;`
179			`else`
180			`wait_crc_check <=#TP wait_crc_check;`
181			`end`
182	39	fisher5090
183	70	fisher5090	`always@(posedge rxclk or posedge reset)begin`
184			`if (reset) begin`
185			`bad_frame_get <=#TP 0;`
186			`good_frame_get <=#TP 0;`
187			`end`
188			`else if(rxstate[3] \|\| crc_check_invalid \|\| length_error)begin`
189			`bad_frame_get <=#TP 1'b1;`
190			`good_frame_get <=#TP 1'b0;`
191			`end`
192			`else if (crc_check_valid)begin`
193			`good_frame_get <=#TP 1'b1;`
194			`bad_frame_get <=#TP 1'b0;`
195			`end`
196			`else if (check_reset)begin`
197			`good_frame_get <=#TP 1'b0;`
198			`bad_frame_get <=#TP 1'b0;`
199			`end`
200			`end`
201	39	fisher5090	`endmodule`

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxStateMachine.v] - Blame information for rev 72