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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [timescale.v] - Blame information for rev 72

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: timescale.v                                     ////
////                                                              ////
//// DESCRIPTION:                                                 ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2006/05/31 05:59:43  Zheng Cao
// first version
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
`timescale 100ps / 10ps

Line No.	Rev	Author	Line
1	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
2	70	fisher5090	`//// ////`
3			`//// MODULE NAME: timescale.v ////`
4			`//// ////`
5	39	fisher5090	`//// DESCRIPTION: ////`
6	70	fisher5090	`//// ////`
7	39	fisher5090	`//// This file is part of the 10 Gigabit Ethernet IP core project ////`
8	70	fisher5090	`//// http://www.opencores.org/projects/ethmac10g/ ////`
9			`//// ////`
10			`//// AUTHOR(S): ////`
11			`//// Zheng Cao ////`
12			`//// ////`
13	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
14	70	fisher5090	`//// ////`
15			`//// Copyright (c) 2005 AUTHORS. All rights reserved. ////`
16			`//// ////`
17	39	fisher5090	`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36	70	fisher5090	`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38	39	fisher5090	`//////////////////////////////////////////////////////////////////////`
39			`//`
40			`// CVS REVISION HISTORY:`
41			`//`
42			`// $Log: not supported by cvs2svn $`
43	70	fisher5090	`// Revision 1.1.1.1 2006/05/31 05:59:43 Zheng Cao`
44			`// first version`
45			`//`
46	39	fisher5090	`// Revision 1.1 2005/12/25 16:43:10 Zheng Cao`
47			`//`
48			`//`
49			`//`
50			`//////////////////////////////////////////////////////////////////////`
51			`timescale 100ps / 10ps

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [timescale.v] - Blame information for rev 72