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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [tx_engine/] [byte_counter.v] - Blame information for rev 72

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module byte_count_module(CLK, RESET, START, BYTE_COUNTER);
 
// Ports declaration
input CLK;
input RESET;
input START;
 
 
 
output [15:0] BYTE_COUNTER;
 
reg [15:0] BYTE_COUNTER;
reg [15:0] counter;
 
always @(posedge CLK or posedge RESET)
begin
   if (RESET == 1) begin
           counter = 16'h0000;
   end
   // the ack is delayed which starts the counter
   else if (START == 1) begin
       counter = counter + 8;
   end
end
 
always @(posedge CLK)
begin
   BYTE_COUNTER = counter;
end
 
endmodule // End of Module 
 

Line No.	Rev	Author	Line
1	39	fisher5090	`module byte_count_module(CLK, RESET, START, BYTE_COUNTER);`
2
3			`// Ports declaration`
4			`input CLK;`
5			`input RESET;`
6			`input START;`
7
8
9
10			`output [15:0] BYTE_COUNTER;`
11
12			`reg [15:0] BYTE_COUNTER;`
13			`reg [15:0] counter;`
14
15			`always @(posedge CLK or posedge RESET)`
16			`begin`
17			`if (RESET == 1) begin`
18	50	fisher5090	`counter = 16'h0000;`
19	39	fisher5090	`end`
20			`// the ack is delayed which starts the counter`
21			`else if (START == 1) begin`
22			`counter = counter + 8;`
23			`end`
24	50	fisher5090	`end`
25	39	fisher5090
26	50	fisher5090	`always @(posedge CLK)`
27			`begin`
28	39	fisher5090	`BYTE_COUNTER = counter;`
29			`end`
30
31			`endmodule // End of Module`
32

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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [tx_engine/] [byte_counter.v] - Blame information for rev 72