URL https://opencores.org/ocsvn/eus100lx/eus100lx/trunk

Subversion Repositories eus100lx

[/] [eus100lx/] [tags/] [sources1/] [fpga/] [distram_be/] [distram_be.ise] - Blame information for rev 8

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PK
 
 
__OBJSTORE__/ProjectNavigator/PK

__REGISTRY__/PK
 
��6..__REGISTRY__/bitgen/regkeysClientMessageOutputFile
_xmsgs/bitgen.xmsgs
s
 
__REGISTRY__/common/PK
�|�,""__REGISTRY__/common/regkeysMessageFilterFile
filter.filter
 
PK
__REGISTRY__/cpldfit/PK
��S�//__REGISTRY__/cpldfit/regkeysClientMessageOutputFile
 
s
PK
__REGISTRY__/dumpngdio/PK
 
_xmsgs/dumpngdio.xmsgs
s
PK
 
!6�,,__REGISTRY__/fuse/regkeysClientMessageOutputFile
_xmsgs/fuse.xmsgs
s
 
__REGISTRY__/hprep6/PK
��a�..__REGISTRY__/hprep6/regkeysClientMessageOutputFile
_xmsgs/hprep6.xmsgs
 
PK
__REGISTRY__/idem/PK
���,,__REGISTRY__/idem/regkeysClientMessageOutputFile
 
s
PK
__REGISTRY__/map/PK
 
_xmsgs/map.xmsgs
s
PK
 
e�6~..__REGISTRY__/netgen/regkeysClientMessageOutputFile
_xmsgs/netgen.xmsgs
s
 
__REGISTRY__/ngc2edif/PK
OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
_xmsgs/ngc2edif.xmsgs
 
PK
__REGISTRY__/ngcbuild/PK
�E��00__REGISTRY__/ngcbuild/regkeysClientMessageOutputFile
_xmsgs/ngcbuild.xmsgs
s
PK
__REGISTRY__/ngdbuild/PK
�J�x00__REGISTRY__/ngdbuild/regkeysClientMessageOutputFile
_xmsgs/ngdbuild.xmsgs
s
PK
__REGISTRY__/par/PK
��++__REGISTRY__/par/regkeysClientMessageOutputFile
_xmsgs/par.xmsgs
s
PK
__REGISTRY__/ProjectNavigator/PK
%__REGISTRY__/ProjectNavigator/NORMAL/PK
�S0H��,__REGISTRY__/ProjectNavigator/NORMAL/regkeysp_AutoGenFile
xstvhd, spartan3, VHDL.t_genImpactFile, 1133516384, True
s
p_ChainDescFile
xstvhd, spartan3, VHDL.t_genImpactFile, 1133629106, distram_be.ipf, D:\Projekty\EUS\FPGA\FPGA_tmps\distram_be\distram_be.ipf
s
 
xstvhd, spartan3, Implementation.t_bitFile, 1133518697, True
s
xilxBitgCfg_GenOpt_DRC
 
s
xilxBitgCfg_Unused
xstvhd, spartan3, Implementation.t_bitFile, 1133516453, Float
s
xilxBitgStart_Clk_DriveDone
xstvhd, spartan3, Implementation.t_bitFile, 1133516466, True
s
xilxNgdbld_AUL
xstvhd, spartan3, Implementation.t_placeAndRouteDes, 1133481053, True
s
xilxSynthRegBalancing
xstvhd, spartan3, Schematic.t_synthesize, 1133482596, Yes
s
PK
)__REGISTRY__/ProjectNavigator/STATUS-ALL/PK
N��&&0__REGISTRY__/ProjectNavigator/STATUS-ALL/regkeyseus_100lx.bitgenGroup
OK,1133629289
s
PK
pdg'YY%__REGISTRY__/ProjectNavigator/regkeys0
JDF H
s
1
// Created by Project Navigator ver 1.0
s
10
DEVTOPLEVELMODULETYPE HDL
s
11
TOPLEVELMODULETYPETIME 0
s
12
DEVSYNTHESISTOOL XST (VHDL/Verilog)
s
13
SYNTHESISTOOLTIME 0
s
14
DEVSIMULATOR Modelsim
s
15
SIMULATORTIME 0
s
16
DEVGENERATEDSIMULATIONMODEL VHDL
s
17
GENERATEDSIMULATIONMODELTIME 0
s
18
SOURCE ../src/vhdl/clocks.vhd
s
19
SOURCE distram_be.vhd
s
2
DEVFAM spartan3
s
20
DEPASSOC eus_100lx ..\src\const\eus_100lx.ucf
s
3
 
s
4
DEVICE xc3s400
 
5
DEVICETIME 1133477379
s
 
DEVPKG fg456
s
7
 
s
8
DEVSPEED -4
 
9
DEVSPEEDTIME 1133477379
s
 
21
s
PK
 
�p7..__REGISTRY__/runner/regkeysClientMessageOutputFile
_xmsgs/runner.xmsgs
s
 
__REGISTRY__/taengine/PK
����00__REGISTRY__/taengine/regkeysClientMessageOutputFile
_xmsgs/taengine.xmsgs
 
PK
__REGISTRY__/trce/PK

Line No.	Rev	Author	Line
1	4	freza	`PK`
2
3
4			`__OBJSTORE__/ProjectNavigator/PK`
5			`__REGISTRY__/PK`
6
7			`��6..__REGISTRY__/bitgen/regkeysClientMessageOutputFile`
8			`_xmsgs/bitgen.xmsgs`
9			`s`
10
11			`__REGISTRY__/common/PK`
12			`�\|�,""__REGISTRY__/common/regkeysMessageFilterFile`
13			`filter.filter`
14
15			`PK`
16			`__REGISTRY__/cpldfit/PK`
17			`��S�//__REGISTRY__/cpldfit/regkeysClientMessageOutputFile`
18
19			`s`
20			`PK`
21			`__REGISTRY__/dumpngdio/PK`
22
23			`_xmsgs/dumpngdio.xmsgs`
24			`s`
25			`PK`
26
27			`!6�,,__REGISTRY__/fuse/regkeysClientMessageOutputFile`
28			`_xmsgs/fuse.xmsgs`
29			`s`
30
31			`__REGISTRY__/hprep6/PK`
32			`��a�..__REGISTRY__/hprep6/regkeysClientMessageOutputFile`
33			`_xmsgs/hprep6.xmsgs`
34
35			`PK`
36			`__REGISTRY__/idem/PK`
37			`��,,__REGISTRY__/idem/regkeysClientMessageOutputFile`
38
39			`s`
40			`PK`
41			`__REGISTRY__/map/PK`
42
43			`_xmsgs/map.xmsgs`
44			`s`
45			`PK`
46
47			`e�6~..__REGISTRY__/netgen/regkeysClientMessageOutputFile`
48			`_xmsgs/netgen.xmsgs`
49			`s`
50
51			`__REGISTRY__/ngc2edif/PK`
52			`OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile`
53			`_xmsgs/ngc2edif.xmsgs`
54
55			`PK`
56			`__REGISTRY__/ngcbuild/PK`
57			`�E��00__REGISTRY__/ngcbuild/regkeysClientMessageOutputFile`
58			`_xmsgs/ngcbuild.xmsgs`
59			`s`
60			`PK`
61			`__REGISTRY__/ngdbuild/PK`
62			`�J�x00__REGISTRY__/ngdbuild/regkeysClientMessageOutputFile`
63			`_xmsgs/ngdbuild.xmsgs`
64			`s`
65			`PK`
66			`__REGISTRY__/par/PK`
67			`��++__REGISTRY__/par/regkeysClientMessageOutputFile`
68			`_xmsgs/par.xmsgs`
69			`s`
70			`PK`
71			`__REGISTRY__/ProjectNavigator/PK`
72			`%__REGISTRY__/ProjectNavigator/NORMAL/PK`
73			`�S0H��,__REGISTRY__/ProjectNavigator/NORMAL/regkeysp_AutoGenFile`
74			`xstvhd, spartan3, VHDL.t_genImpactFile, 1133516384, True`
75			`s`
76			`p_ChainDescFile`
77			`xstvhd, spartan3, VHDL.t_genImpactFile, 1133629106, distram_be.ipf, D:\Projekty\EUS\FPGA\FPGA_tmps\distram_be\distram_be.ipf`
78			`s`
79
80			`xstvhd, spartan3, Implementation.t_bitFile, 1133518697, True`
81			`s`
82			`xilxBitgCfg_GenOpt_DRC`
83
84			`s`
85			`xilxBitgCfg_Unused`
86			`xstvhd, spartan3, Implementation.t_bitFile, 1133516453, Float`
87			`s`
88			`xilxBitgStart_Clk_DriveDone`
89			`xstvhd, spartan3, Implementation.t_bitFile, 1133516466, True`
90			`s`
91			`xilxNgdbld_AUL`
92			`xstvhd, spartan3, Implementation.t_placeAndRouteDes, 1133481053, True`
93			`s`
94			`xilxSynthRegBalancing`
95			`xstvhd, spartan3, Schematic.t_synthesize, 1133482596, Yes`
96			`s`
97			`PK`
98			`)__REGISTRY__/ProjectNavigator/STATUS-ALL/PK`
99			`N��&&0__REGISTRY__/ProjectNavigator/STATUS-ALL/regkeyseus_100lx.bitgenGroup`
100			`OK,1133629289`
101			`s`
102			`PK`
103			`pdg'YY%__REGISTRY__/ProjectNavigator/regkeys0`
104			`JDF H`
105			`s`
106			`1`
107			`// Created by Project Navigator ver 1.0`
108			`s`
109			`10`
110			`DEVTOPLEVELMODULETYPE HDL`
111			`s`
112			`11`
113			`TOPLEVELMODULETYPETIME 0`
114			`s`
115			`12`
116			`DEVSYNTHESISTOOL XST (VHDL/Verilog)`
117			`s`
118			`13`
119			`SYNTHESISTOOLTIME 0`
120			`s`
121			`14`
122			`DEVSIMULATOR Modelsim`
123			`s`
124			`15`
125			`SIMULATORTIME 0`
126			`s`
127			`16`
128			`DEVGENERATEDSIMULATIONMODEL VHDL`
129			`s`
130			`17`
131			`GENERATEDSIMULATIONMODELTIME 0`
132			`s`
133			`18`
134			`SOURCE ../src/vhdl/clocks.vhd`
135			`s`
136			`19`
137			`SOURCE distram_be.vhd`
138			`s`
139			`2`
140			`DEVFAM spartan3`
141			`s`
142			`20`
143			`DEPASSOC eus_100lx ..\src\const\eus_100lx.ucf`
144			`s`
145			`3`
146
147			`s`
148			`4`
149			`DEVICE xc3s400`
150
151			`5`
152			`DEVICETIME 1133477379`
153			`s`
154
155			`DEVPKG fg456`
156			`s`
157			`7`
158
159			`s`
160			`8`
161			`DEVSPEED -4`
162
163			`9`
164			`DEVSPEEDTIME 1133477379`
165			`s`
166
167			`21`
168			`s`
169			`PK`
170
171			`�p7..__REGISTRY__/runner/regkeysClientMessageOutputFile`
172			`_xmsgs/runner.xmsgs`
173			`s`
174
175			`__REGISTRY__/taengine/PK`
176			`��00__REGISTRY__/taengine/regkeysClientMessageOutputFile`
177			`_xmsgs/taengine.xmsgs`
178
179			`PK`
180			`__REGISTRY__/trce/PK`

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Subversion Repositories eus100lx

[/] [eus100lx/] [tags/] [sources1/] [fpga/] [distram_be/] [distram_be.ise] - Blame information for rev 8