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freza |
-- Copyright (C) 2004 DSP&FPGA
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-- Author: SaVa <s.valach@dspfpga.com>
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--
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the OpenIPCore Hardware General Public
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-- License as published by the OpenIPCore Organization; either version
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-- 0.20-15092000 of the License, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- OpenIPCore Hardware General Public License for more details.
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--
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-- You should have received a copy of the OpenIPCore Hardware Public
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-- License along with this program; if not, download it from
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-- OpenCores.org (http://www.opencores.org/OIPC/OHGPL.shtml).
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- synthesis translate_off
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library unisim;
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use unisim.vcomponents.all;
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-- synthesis translate_on
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Entity eus_100lx is
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Generic(
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E_DATA_WIDTH : integer := 32);
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Port(
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SDRCLKF : in std_logic; -- Etrax clocks (50MHz)
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RESET : in std_logic; -- Global reset
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-- ETRAX Bus
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DREQ0 : out std_logic; -- DMA Request (Active high)
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DACK0 : in std_logic; -- DMA ACK (Active high)
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IRQ : out std_logic; -- Active low
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--- Bus signals
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D : inout std_logic_vector(E_DATA_WIDTH - 1 downto 0);
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A : in std_logic_vector(22 downto 2);
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CSR0 : in std_logic; -- FPGA Programming
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CSR1 : in std_logic; -- LCD Data channel
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CSP0 : in std_logic; -- Internal Registers, control and status
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CSP4 : in std_logic; -- Reserved
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RD : in std_logic; -- Etrax reads
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WR : in std_logic_vector(3 downto 0); -- Etrax writes
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-- USERIOs
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LEDX : out std_logic_vector(1 downto 0); -- Leds
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X : inout std_logic_vector(87 downto 0); -- Generic IOs
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ISAEN : out std_logic; --
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-- LCD Outputs / Generic In/Out
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Y : out std_logic_vector(28 downto 0);
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-- Dedicated SDRAM
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SD : inout std_logic_vector(15 downto 0); -- Data Bus
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SA : out std_logic_vector(0 to 14); -- Address and BA signals
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SRAS : out std_logic; -- SDRAM ras
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SCAS : out std_logic; -- SDRAM cas
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SCS : out std_logic;
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SCLK : out std_logic;
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SCKE : out std_logic;
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SDQMH : out std_logic;
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SDQML : out std_logic;
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SWE : out std_logic);
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end eus_100lx;
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architecture behav of eus_100lx is
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-- Components Declarations
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-- Clocks distribution
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Component CLK_GEN
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Generic (
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ACTIVE_RST : std_logic := '1';
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CLK_M_RATIO : integer := 2;
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CLK_D_RATIO : integer := 2;
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CLK_DIV_RATIO : real := 10.0; -- LCD divider
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POWER_UP_T : integer := 20 -- Clk numbers - should be 200ms, for sim is shorter
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);
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Port (
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-- Clocks & Resets
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CLK_IN : in std_logic;
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CLK_FB : in std_logic;
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RESET_IN : in std_logic;
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RESET_OUT : out std_logic;
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CLK : out std_logic; -- System Clock
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SD_CLK_I : out std_logic; -- Internal SDRAM Clock
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SD_CLK : out std_logic; -- SDRAM Clock
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LCD_CLK_I : out std_logic; -- Internal Clock for LCD controller, usually CLK divided by 16 - see M/D ratio
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POWER_UP : out std_logic -- SDRAM Initial time after stable CLK
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);
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End Component;
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component RAM64X1S
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-- User can add initialization values
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port (
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D : in std_logic;
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WE : in std_logic;
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WCLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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A4 : in std_logic;
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A5 : in std_logic;
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O : out std_logic
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);
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end component;
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constant dist_ram_wd : integer := E_DATA_WIDTH;
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constant num_be : integer := 4; -- Number of BE
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-- LOW/HIGH definition
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signal low : std_logic := '0';
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signal high : std_logic := '1';
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-- SDRCLKF_internal
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signal sdrclkf_i : std_logic;
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signal lcd_clk_i : std_logic;
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signal rst : std_logic;
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signal dreq0_i : std_logic;
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-- Sampled signals by SDRCLKF
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signal d_in : std_logic_vector(E_DATA_WIDTH - 1 downto 0);
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signal a_i : std_logic_vector(22 downto 2);
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signal csr0_i : std_logic := '0';
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signal csr1_i : std_logic := '0';
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signal csp0_i : std_logic := '0';
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signal csp4_i : std_logic := '0';
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signal rd_i : std_logic := '0';
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signal wr_i : std_logic_vector(3 downto 0) := "0000";
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signal dack0_i : std_logic := '0';
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-- Access control - active high
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signal sel_wr_0 : std_logic;
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signal sel_wr_1 : std_logic;
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signal sel_wr_2 : std_logic;
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signal csp0_rd : std_logic;
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signal sel_rd_0 : std_logic;
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signal sel_rd_1 : std_logic;
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signal sel_rd_2 : std_logic;
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-- Control Section
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signal reg_0 : std_logic_vector(31 downto 0) := x"11111111"; -- Defaul values
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signal reg_1 : std_logic_vector(31 downto 0) := x"22222222";
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signal reg_2 : std_logic_vector(31 downto 0) := x"33333333";
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signal sys_cnt : std_logic_vector(31 downto 0) := (Others => '0');
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signal d_out : std_logic_vector(31 downto 0);
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signal dist_d_out : std_logic_vector(31 downto 0);
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signal led_blink_cnt : std_logic_vector(22 downto 0);
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signal dist_ram_we : std_logic_vector(num_be - 1 downto 0);
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BEGIN
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-- XX_OFUB workaround ISE7.1
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DREQ0 <= 'Z';
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IRQ <= 'Z';
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X <= (Others => 'Z');
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Y <= (Others => 'Z');
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SD <= (Others => 'Z');
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SA <= (Others => 'Z');
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SRAS <= 'Z';
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SCAS <= 'Z';
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SCS <= 'Z';
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SCLK <= 'Z';
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SCKE <= 'Z';
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SDQMH <= 'Z';
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SDQML <= 'Z';
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SWE <= 'Z';
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-- Windows size for write are 64kB
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sel_wr_0 <= '1' When (csp0_i = '0') And (a_i(22 downto 16) = "0000000") Else '0'; -- Base Address = CSP0 + 0x00000
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sel_wr_1 <= '1' When (csp0_i = '0') And (a_i(22 downto 16) = "0000001") Else '0'; -- Base Address = CSP0 + 0x10000
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sel_wr_2 <= '1' When (csp0_i = '0') And (a_i(22 downto 16) = "0000010") Else '0'; -- Base Address = CSP0 + 0x20000
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-- Selectors without resample - used for dir control read/write
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csp0_rd <= '1' When (CSP0 = '0') And (RD = '0') Else '0'; -- Read selector for CSP0
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--Windows size for read are 64kB
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sel_rd_0 <= '1' When (csp0_rd = '1') And (A(22 downto 16) = "0000000") Else '0'; -- Base Address = CSP0 + 0x00000
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sel_rd_1 <= '1' When (csp0_rd = '1') And (A(22 downto 16) = "0000001") Else '0'; -- Base Address = CSP0 + 0x10000
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sel_rd_2 <= '1' When (csp0_rd = '1') And (A(22 downto 16) = "0000010") Else '0'; -- Base Address = CSP0 + 0x20000
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-- Components mapping
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CLK_GENERATION : CLK_GEN
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Port map(
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CLK_IN => SDRCLKF, -- Etrax's Clock (50MHz)
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CLK_FB => low, -- SDRAM Feadback
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RESET_IN => low, -- Global reset
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RESET_OUT => rst,
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CLK => sdrclkf_i, -- Internal system Clock
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SD_CLK_I => open, -- Internal SDRAM Clock
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SD_CLK => open, -- SDRAM Clock
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LCD_CLK_I => lcd_clk_i, -- Internal Clock for LCD controller, usually CLK divided by 8 see divide ratio
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POWER_UP => open -- SDRAM Initial time after stable CLK
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);
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-- write enables
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dist_ram_we(num_be - 1 downto 0) <= Not WR(num_be - 1 downto 0) When (CSP0 = '0') And (A(22 downto 16) = "0000010") Else (Others => '0'); -- Base Address = CSP0 + 0x20000
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MY_RAM: for i in 0 to dist_ram_wd - 1 generate
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MY_RAM_EL: RAM64X1S
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port map (
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D => D(i), -- insert input signal
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WE => dist_ram_we(i/8),-- insert Write Enable signal
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WCLK => sdrclkf_i, -- insert Write Clock signal
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A0 => A(2), -- insert Address 0 signal
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A1 => A(3), -- insert Address 1 signal
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A2 => A(4), -- insert Address 2 signal
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A3 => A(5), -- insert Address 3 signal
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A4 => A(7), -- insert Address 4 signal
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A5 => A(8), -- insert Address 5 signal
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O => dist_d_out(i) -- insert output signal
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);
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end generate; -- MY_RAM
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RESAMPLE_IN : PROCESS(sdrclkf_i, D, A, CSR0, CSR1, CSP0, CSP4, RD, WR, DACK0)
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BEGIN
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If sdrclkf_i'event And sdrclkf_i = '1' Then
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d_in <= D;
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a_i <= A;
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csr0_i <= CSR0;
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csr1_i <= CSR1;
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csp0_i <= CSP0;
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csp4_i <= CSP4;
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rd_i <= RD;
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wr_i <= WR;
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dack0_i <= DACK0;
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End If;
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END PROCESS;
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PROCESS(sdrclkf_i)
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BEGIN
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If sdrclkf_i'event And sdrclkf_i = '1' Then
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If (sel_wr_0 = '1') And (wr_i(3) = '0') Then
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Case a_i(15 downto 2) is
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When "00000000000000" =>
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reg_0 <= d_in;
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When "00000000000001" =>
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reg_1 <= d_in;
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When "00000000000010" =>
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reg_2 <= d_in;
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When Others => NULL;
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End Case;
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End If;
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End If;
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END PROCESS;
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d_out <= reg_0 When A(15 downto 2) = "00000000000000" Else
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reg_1 When A(15 downto 2) = "00000000000001" Else
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reg_2;
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D <= d_out When sel_rd_0 = '1' Else
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sys_cnt When sel_rd_1 = '1' Else
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dist_d_out When sel_rd_2 = '1' Else
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(Others => 'Z');
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ISAEN <= '1'; -- Enable "ISA ios"
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LED_BLINK: PROCESS(sdrclkf_i, led_blink_cnt)
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BEGIN
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If sdrclkf_i'event And sdrclkf_i = '1' Then
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led_blink_cnt <= led_blink_cnt + 1;
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End If;
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END PROCESS;
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PROCESS(sdrclkf_i)
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BEGIN
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If sdrclkf_i'event And sdrclkf_i = '1' Then
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sys_cnt <= sys_cnt + 1;
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End If;
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END PROCESS;
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LEDX <= Not (led_blink_cnt(led_blink_cnt'high) & reg_0(0));
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end behav;
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