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[/] [ezusb_io/] [trunk/] [ezusb_io.v] - Blame information for rev 2

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1 2 ZTEX
/*!
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   memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13
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   Copyright (C) 2009-2014 ZTEX GmbH.
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   http://www.ztex.de
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License version 3 as
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   published by the Free Software Foundation.
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   This program is distributed in the hope that it will be useful, but
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   WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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   General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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/*
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   Implements the EZ-USB Slave FIFO interface for both
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   directions. It also includes an scheduler (required if both
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   directions are used at the same time) and short packets (PKTEND).
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*/
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module ezusb_io #(
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        parameter CLKBUF_TYPE = "",     // selects the clock preparation method (buffering, filtering, ...)
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                                        // "SPARTAN6" for Xilinx Spartan 6, 
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                                        // "SERIES7" for Xilinx Series 7, 
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                                        // all other values: no clock preparation
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        parameter OUTEP = 2,            // EP for FPGA -> EZ-USB transfers
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        parameter INEP = 6              // EP for EZ-USB -> FPGA transfers 
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    ) (
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        output ifclk,                   // buffered output of the interface clock
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                                        // this is the clock for the user logic
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        input reset,                    // asynchronous reset input
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        output reset_out,               // synchronous reset output
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        // FPGA pins that are connected directly to EZ-USB.
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        input ifclk_in,                 // interface clock IFCLK
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        inout [15:0] fd,                // 16 bit data bus
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        output reg SLWR, PKTEND,        // SLWR (slave write) and PKTEND (packet end) flags
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        output SLRD, SLOE,              // SLRD (slave read) and SLOE (slave output enable) flags
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        output [1:0] FIFOADDR,          // FIFOADDR pins select the endpoint
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        input EMPTY_FLAG, FULL_FLAG,    // EMPTY and FULL flag of the slave FIFO interface
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        // Signals for FPGA -> EZ-USB transfer. The are controlled by user logic.
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        input [15:0] DI,                // data written to EZ-USB
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        input DI_valid,                 // 1 indicates valid data; DI and DI_valid must be hold if DI_ready is 0
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        output DI_ready,                // 1 if new data are accepted
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        input DI_enable,                // setting to 0 disables FPGA -> EZ-USB transfers
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        input [15:0] pktend_timeout,     // timeout in multiples of 65536 clocks before a short packet committed
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                                        // setting to 0 disables this feature
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        // Signals for EZ-USB -> FPGA transfer. They are controlled by user logic.
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        output reg [15:0] DO,           // data read from EZ-USB
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        output reg DO_valid,            // 1 indicates valid data
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        input DO_ready,                 // setting to 1 enables writing new data to DO in next clock
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                                        // DO and DO_valid are hold if DO_ready is 0
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                                        // set to 0 to disable data reads 
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        // debug output
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        output [3:0] status
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    );
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    wire locked;
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    generate
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        if ( CLKBUF_TYPE == "SPARTAN6")
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        begin
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            IBUFG ifclkin_buf (
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                .I(ifclk_in),
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                .O(ifclk)
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            );
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            assign locked = 1'b1;
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        end else if ( CLKBUF_TYPE == "SERIES7")
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        begin
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            wire ifclk_inbuf, ifclk_fbin, ifclk_fbout, ifclk_out;
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            IBUFG ifclkin_buf (
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                .I(ifclk_in),
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                .O(ifclk_inbuf)
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            );
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            BUFG ifclk_fb_buf (
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                .I(ifclk_fbout),
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                .O(ifclk_fbin)
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             );
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            BUFG ifclk_out_buf (
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                .I(ifclk_out),
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                .O(ifclk)
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             );
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            MMCME2_BASE #(
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               .BANDWIDTH("OPTIMIZED"),
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               .CLKFBOUT_MULT_F(20.0),
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               .CLKFBOUT_PHASE(0.0),
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               .CLKIN1_PERIOD(0.0),
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               .CLKOUT0_DIVIDE_F(20.0),
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               .CLKOUT1_DIVIDE(1),
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               .CLKOUT2_DIVIDE(1),
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               .CLKOUT3_DIVIDE(1),
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               .CLKOUT4_DIVIDE(1),
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               .CLKOUT5_DIVIDE(1),
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               .CLKOUT0_DUTY_CYCLE(0.5),
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               .CLKOUT1_DUTY_CYCLE(0.5),
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               .CLKOUT2_DUTY_CYCLE(0.5),
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               .CLKOUT3_DUTY_CYCLE(0.5),
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               .CLKOUT4_DUTY_CYCLE(0.5),
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               .CLKOUT5_DUTY_CYCLE(0.5),
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               .CLKOUT0_PHASE(0.0),
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               .CLKOUT1_PHASE(0.0),
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               .CLKOUT2_PHASE(0.0),
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               .CLKOUT3_PHASE(0.0),
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               .CLKOUT4_PHASE(0.0),
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               .CLKOUT5_PHASE(0.0),
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               .CLKOUT4_CASCADE("FALSE"),
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               .DIVCLK_DIVIDE(1),
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               .REF_JITTER1(0.0),
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               .STARTUP_WAIT("FALSE")
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            )  isclk_mmcm_inst (
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               .CLKOUT0(ifclk_out),
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               .CLKFBOUT(ifclk_fbout),
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               .CLKIN1(ifclk_inbuf),
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               .PWRDWN(1'b0),
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               .RST(reset),
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               .CLKFBIN(ifclk_fbin),
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               .LOCKED(locked)
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            );
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        end else
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        begin
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            assign ifclk = ifclk_in;
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            assign locked = 1'b1;
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        end
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     endgenerate
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    reg reset_ifclk = 1;
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    reg if_out, if_in;
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    reg [4:0] if_out_buf;
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    reg [15:0] fd_buf;
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    reg resend;
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    reg SLRD_buf, pktend_req, pktend_en;
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    reg [31:0] pktend_cnt;
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    // FPGA <-> EZ-USB signals
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    assign SLOE = if_out;
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//    assign FIFOADDR[0] = 1'b0;
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//    assign FIFOADDR[1] = !if_out;
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    assign FIFOADDR = if_out ? OUTEP/2-1 : INEP/2-1;
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    assign fd = if_out ? fd_buf : {16{1'bz}};
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    assign SLRD = SLRD_buf || !DO_ready;
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    assign status = { !SLRD_buf, !SLWR, resend, if_out };
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    assign DI_ready = !reset_ifclk && FULL_FLAG && if_out & if_out_buf[4] && !resend;
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    assign reset_out = reset || reset_ifclk;
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    always @ (posedge ifclk)
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    begin
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        reset_ifclk <= reset || !locked;
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        // FPGA -> EZ-USB
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        if ( reset_ifclk )
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        begin
162
            SLWR <= 1'b1;
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            if_out <= DI_enable;  // direction of EZ-USB interface: 1 means FPGA writes / EZ_USB reads
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            resend <= 1'b0;
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            SLRD_buf <= 1'b1;
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        end else if ( FULL_FLAG && if_out && if_out_buf[4] && ( resend || DI_valid) )   // FPGA -> EZ-USB
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        begin
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            SLWR <= 1'b0;
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            SLRD_buf <= 1'b1;
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            resend <= 1'b0;
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            if ( !resend ) fd_buf <= DI;
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        end else if ( EMPTY_FLAG && !if_out && !if_out_buf[4] && DO_ready )             // EZ-USB -> FPGA
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        begin
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            SLWR <= 1'b1;
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            DO <= fd;
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            SLRD_buf <= 1'b0;
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        end else if (if_out == if_out_buf[4])
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        begin
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            if ( !SLWR && !FULL_FLAG ) resend <= 1'b1;  // FLAGS are received two clocks after data. If FULL_FLAG was asserted last data was ignored and has to be re-sent.
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            SLRD_buf <= 1'b1;
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            SLWR <= 1'b1;
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            if_out <= DI_enable && (!DO_ready || !EMPTY_FLAG);
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        end
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        if_out_buf <= reset_ifclk ? {5{!DI_enable}} : { if_out_buf[3:0], if_out };
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        if ( DO_ready ) DO_valid <= !if_out && !if_out_buf[4] && EMPTY_FLAG && !SLRD_buf;  // assertion of SLRD_buf takes two clocks to take effect
186
 
187
        // PKTEND processing
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        if ( reset_ifclk || DI_valid )
189
        begin
190
            pktend_req <= 1'b0;
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            pktend_en <= !reset_ifclk;
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            pktend_cnt <= 32'd0;
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            PKTEND <= 1'b1;
194
        end else
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        begin
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            pktend_req <= pktend_req || ( pktend_en && (pktend_timeout != 16'd0) && (pktend_timeout == pktend_cnt[31:16]) );
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            pktend_cnt <= pktend_cnt + 1;
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            if ( pktend_req && if_out && if_out_buf[4] )
199
            begin
200
                PKTEND <= 1'b0;
201
                pktend_req <= 1'b0;
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                pktend_en <= 1'b0;
203
            end else
204
            begin
205
                PKTEND <= 1'b1;
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                pktend_req <= pktend_req || ( pktend_en && (pktend_timeout != 16'd0) && (pktend_timeout == pktend_cnt[31:16]) );
207
            end
208
        end
209
 
210
    end
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212
endmodule
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