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#@ NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10
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| 2 |
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#@ NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10
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| 3 |
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#@ NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10
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| 4 |
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NET "GPIO_LED<0>" LOC = "U18"; ## 2 on DS11 LED
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| 5 |
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NET "GPIO_LED<1>" LOC = "M14"; ## 2 on DS12 LED
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| 6 |
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NET "GPIO_LED<2>" LOC = "N14"; ## 2 on DS13 LED
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| 7 |
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NET "GPIO_LED<3>" LOC = "L14"; ## 2 on DS14 LED
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| 8 |
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NET "GPIO_LED<4>" LOC = "M13"; ## 2 on DS11 LED
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| 9 |
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NET "GPIO_LED<5>" LOC = "D4"; ## 2 on DS12 LED
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| 10 |
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NET "GPIO_LED<6>" LOC = "P16"; ## 2 on DS13 LED
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| 11 |
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NET "GPIO_LED<7>" LOC = "N12"; ## 2 on DS14 LED
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| 12 |
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| 13 |
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NET "SWITCHES<0>" LOC = "A10";
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| 14 |
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NET "SWITCHES<1>" LOC = "D14";
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| 15 |
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NET "SWITCHES<2>" LOC = "C14";
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| 16 |
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NET "SWITCHES<3>" LOC = "P15";
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| 17 |
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NET "SWITCHES<4>" LOC = "P12";
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| 18 |
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NET "SWITCHES<5>" LOC = "R5";
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| 19 |
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NET "SWITCHES<6>" LOC = "T5";
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| 20 |
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NET "SWITCHES<7>" LOC = "E4";
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| 21 |
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| 22 |
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##
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| 23 |
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NET "CPU_RESET" LOC = "T15"; ## 2 on SW9 pushbutton
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| 24 |
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##
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| 25 |
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NET "PHY_COL" LOC = "C17"; ## 114 on U3
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| 26 |
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NET "PHY_CRS" LOC = "C18"; ## 115 on U3
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| 27 |
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NET "PHY_INT" LOC = "L16"; ## 32 on U3
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| 28 |
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NET "PHY_MDC" LOC = "F16"; ## 35 on U3
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| 29 |
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NET "PHY_MDIO" LOC = "N17"; ## 33 on U3
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| 30 |
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NET "PHY_RESET" LOC = "G13"; ## 36 on U3
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| 31 |
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NET "PHY_RXCLK" LOC = "K15"; ## 7 on U3
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| 32 |
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NET "PHY_RXCTL_RXDV" LOC = "F17"; ## 4 on U3
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| 33 |
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NET "PHY_RXD<0>" LOC = "G16"; ## 3 on U3
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| 34 |
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NET "PHY_RXD<1>" LOC = "H14"; ## 128 on U3
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| 35 |
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NET "PHY_RXD<2>" LOC = "E16"; ## 126 on U3
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| 36 |
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NET "PHY_RXD<3>" LOC = "F15"; ## 125 on U3
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| 37 |
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NET "PHY_RXD<4>" LOC = "F14"; ## 124 on U3
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| 38 |
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NET "PHY_RXD<5>" LOC = "E18"; ## 123 on U3
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| 39 |
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NET "PHY_RXD<6>" LOC = "D18"; ## 121 on U3
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| 40 |
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NET "PHY_RXD<7>" LOC = "D17"; ## 120 on U3
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| 41 |
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NET "PHY_RXER" LOC = "F18"; ## 8 on U3
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| 42 |
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NET "PHY_TXCLK" LOC = "K16"; ## 10 on U3
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| 43 |
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NET "PHY_TXCTL_TXEN" LOC = "H15"; ## 16 on U3
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| 44 |
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NET "PHY_TXC_GTXCLK" LOC = "L12"; ## 14 on U3
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| 45 |
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NET "PHY_TXD<0>" LOC = "H16"; ## 18 on U3
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| 46 |
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NET "PHY_TXD<1>" LOC = "H13"; ## 19 on U3
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| 47 |
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NET "PHY_TXD<2>" LOC = "K14"; ## 20 on U3
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| 48 |
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NET "PHY_TXD<3>" LOC = "K13"; ## 24 on U3
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| 49 |
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NET "PHY_TXD<4>" LOC = "J13"; ## 25 on U3
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| 50 |
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NET "PHY_TXD<5>" LOC = "G14"; ## 26 on U3
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| 51 |
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NET "PHY_TXD<6>" LOC = "H12"; ## 28 on U3
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| 52 |
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NET "PHY_TXD<7>" LOC = "K12"; ## 29 on U3
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| 53 |
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NET "PHY_TXER" LOC = "G18"; ## 13 on U3
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| 54 |
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##
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| 55 |
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NET "SYSCLK" LOC = "L15";
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| 56 |
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##
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| 57 |
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#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
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| 58 |
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#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
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| 59 |
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#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
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| 60 |
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#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
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| 61 |
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#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
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| 62 |
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#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
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| 63 |
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#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
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| 64 |
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#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
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| 65 |
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#
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| 66 |
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#@ NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
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| 67 |
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#@ NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
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| 68 |
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#@ NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
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| 69 |
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#@ NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
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| 70 |
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#@ NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
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| 71 |
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#@ NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
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| 72 |
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#@ NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
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| 73 |
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#@ NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm)
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| 74 |
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#
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| 75 |
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#@ NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16
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| 76 |
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#@ NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16
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| 77 |
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#
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| 78 |
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#@ PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
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| 79 |
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PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
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| 80 |
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| 81 |
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#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04
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| 82 |
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NET "sysclk" TNM_NET = sysclk;
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| 83 |
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TIMESPEC TS_sysclk = PERIOD "sysclk" 10 ns HIGH 50%;
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| 84 |
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#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30
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NET "phy_rxclk" TNM_NET = phy_rxclk;
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TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%;
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| 87 |
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NET "phy_txclk" TNM_NET = phy_txclk;
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TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 40 ns HIGH 50%;
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| 89 |
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NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk;
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| 90 |
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TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%;
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| 91 |
3 |
wzab |
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| 92 |
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INST "phy_col" TNM = phy_inputs;
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| 93 |
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INST "phy_crs" TNM = phy_inputs;
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| 94 |
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INST "phy_int" TNM = phy_inputs;
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| 95 |
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INST "phy_mdio" TNM = phy_inputs;
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| 96 |
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INST "phy_rxctl_rxdv" TNM = phy_inputs;
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| 97 |
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INST "phy_rxd<0>" TNM = phy_inputs;
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| 98 |
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INST "phy_rxd<1>" TNM = phy_inputs;
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| 99 |
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INST "phy_rxd<2>" TNM = phy_inputs;
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| 100 |
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INST "phy_rxd<3>" TNM = phy_inputs;
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| 101 |
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INST "phy_rxd<4>" TNM = phy_inputs;
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| 102 |
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INST "phy_rxd<5>" TNM = phy_inputs;
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| 103 |
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INST "phy_rxd<6>" TNM = phy_inputs;
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| 104 |
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INST "phy_rxd<7>" TNM = phy_inputs;
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| 105 |
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INST "phy_rxer" TNM = phy_inputs;
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TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_rxclk";
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| 107 |
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TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_txclk";
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| 108 |
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INST "phy_txctl_txen" TNM = phy_outputs;
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| 109 |
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INST "phy_txd<0>" TNM = phy_outputs;
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| 110 |
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INST "phy_txd<1>" TNM = phy_outputs;
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| 111 |
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INST "phy_txd<2>" TNM = phy_outputs;
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| 112 |
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INST "phy_txd<3>" TNM = phy_outputs;
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| 113 |
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INST "phy_txd<4>" TNM = phy_outputs;
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| 114 |
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INST "phy_txd<5>" TNM = phy_outputs;
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| 115 |
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INST "phy_txd<6>" TNM = phy_outputs;
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| 116 |
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INST "phy_txd<7>" TNM = phy_outputs;
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| 117 |
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INST "phy_txer" TNM = phy_outputs;
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| 118 |
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TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_rxclk";
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| 119 |
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TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_txclk";
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