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[/] [fade_ether_protocol/] [trunk/] [old_stable_version/] [FPGA_no_MAC/] [sk3e/] [spartan3e.ucf] - Blame information for rev 2

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1 2 wzab 
#####################################################
2 
### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
3 
#####################################################
4 
# ==== Analog-to-Digital Converter (ADC) ====
5 
# some connections shared with SPI Flash, DAC, ADC, and AMP
6 
#NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
7 
# ==== Programmable Gain Amplifier (AMP) ====
8 
# some connections shared with SPI Flash, DAC, ADC, and AMP
9 
#NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
10 
#NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
11 
#NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
12 
# ==== Pushbuttons (BTN) ====
13 
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
14 
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
15 
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
16 
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
17 
# ==== Clock inputs (CLK) ====
18 
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
19 
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
20 
#NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;
21 
NET "CLK_50MHZ" PERIOD = 20 ns HIGH 50 %;
22 
#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
23 
#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
24 
# ==== Digital-to-Analog Converter (DAC) ====
25 
# some connections shared with SPI Flash, DAC, ADC, and AMP
26 
#NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
27 
#NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
28 
# ==== 1-Wire Secure EEPROM (DS)
29 
#NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
30 
# ==== Ethernet PHY (E) ====
31 
NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
32 
NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
33 
NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
34 
NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
35 
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
36 
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
37 
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
38 
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
39 
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
40 
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
41 
NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
42 
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
43 
NET "E_TX_CLK" PERIOD = 30 ns HIGH 50 %;
44 
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
45 
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
46 
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
47 
NET "E_TXD<2>" LOC = "R5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
48 
NET "E_TXD<3>" LOC = "T5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
49 
NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
50 
# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
51 
#NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
52 
#NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
53 
#NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
54 
#NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
55 
#NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
56 
#NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
57 
# ==== FX2 Connector (FX2) ====
58 
#NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
59 
#NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
60 
#NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
61 
# These four connections are shared with the J1 6-pin accessory header
62 
#NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
63 
#NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
64 
#NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
65 
#NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
66 
# These four connections are shared with the J2 6-pin accessory header
67 
#NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
68 
#NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
69 
#NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
70 
#NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
71 
# These four connections are shared with the J4 6-pin accessory header
72 
#NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
73 
#NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
74 
#NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
75 
#NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
76 
# The discrete LEDs are shared with the following 8 FX2 connections
77 
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
78 
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
79 
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
80 
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
81 
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
82 
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
83 
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
84 
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
85 
#NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
86 
#NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
87 
#NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
88 
#NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
89 
#NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
90 
#NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
91 
#NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
92 
#NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
93 
#NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
94 
#NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
95 
#NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
96 
#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
97 
#NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
98 
#NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
99 
#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
100 
#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
101 
#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
102 
#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
103 
#NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
104 
#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
105 
 
106 
NET "CDC_MCK" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
107 
NET "CDC_CSn" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
108 
NET "CDC_SDIN" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
109 
NET "CDC_SCLK" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
110 
NET "CDC_DIN" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
111 
NET "CDC_BCLK" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
112 
NET "CDC_DOUT" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
113 
NET "CDC_LRC_IN_OUT" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
114 
 
115 
# ==== 6-pin header J1 ====
116 
# These are shared connections with the FX2 connector
117 
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
118 
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
119 
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
120 
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
121 
# ==== 6-pin header J2 ====
122 
# These are shared connections with the FX2 connector
123 
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
124 
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
125 
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
126 
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
127 
# ==== 6-pin header J4 ====
128 
# These are shared connections with the FX2 connector
129 
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
130 
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
131 
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
132 
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
133 
# ==== Character LCD (LCD) ====
134 
#NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
135 
#NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
136 
#NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
137 
# LCD data connections are shared with StrataFlash connections SF_D<11:8>
138 
#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
139 
#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
140 
#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
141 
#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
142 
# ==== Discrete LEDs (LED) ====
143 
# These are shared connections with the FX2 connector
144 
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
145 
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
146 
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
147 
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
148 
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
149 
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
150 
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
151 
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
152 
# ==== PS/2 Mouse/Keyboard Port (PS2) ====
153 
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 ;
154 
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
155 
# ==== Rotary Pushbutton Switch (ROT) ====
156 
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
157 
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
158 
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
159 
# ==== RS-232 Serial Ports (RS232) ====
160 
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
161 
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
162 
#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
163 
#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
164 
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
165 
NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
166 
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
167 
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
168 
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
169 
NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
170 
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
171 
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
172 
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
173 
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
174 
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
175 
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
176 
NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
177 
NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
178 
NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
179 
NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
180 
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
181 
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
182 
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
183 
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
184 
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
185 
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
186 
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
187 
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
188 
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
189 
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
190 
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
191 
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
192 
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
193 
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
194 
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
195 
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
196 
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
197 
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
198 
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
199 
NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
200 
NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
201 
NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
202 
NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
203 
NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
204 
NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
205 
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
206 
NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
207 
# Path to allow connection to top DCM connection
208 
#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
209 
# Prohibit VREF pins
210 
CONFIG PROHIBIT = D2;
211 
CONFIG PROHIBIT = G4;
212 
CONFIG PROHIBIT = J6;
213 
CONFIG PROHIBIT = L5;
214 
CONFIG PROHIBIT = R4;
215 
# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
216 
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
217 
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
218 
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
219 
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
220 
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
221 
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
222 
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
223 
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
224 
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
225 
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
226 
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
227 
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
228 
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
229 
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
230 
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
231 
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
232 
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
233 
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
234 
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
235 
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
236 
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
237 
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
238 
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
239 
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
240 
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
241 
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
242 
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
243 
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
244 
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
245 
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
246 
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
247 
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
248 
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
249 
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
250 
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
251 
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
252 
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
253 
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
254 
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
255 
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
256 
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
257 
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
258 
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
259 
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
260 
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
261 
# ==== STMicro SPI serial Flash (SPI) ====
262 
# some connections shared with SPI Flash, DAC, ADC, and AMP
263 
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
264 
#NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
265 
#NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
266 
#NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
267 
#NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
268 
# ==== Slide Switches (SW) ====
269 
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
270 
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
271 
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
272 
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
273 
# ==== VGA Port (VGA) ====
274 
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
275 
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
276 
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
277 
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
278 
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
279 
# ==== Xilinx CPLD (XC) ====
280 
#NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
281 
#NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
282 
#NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
283 
#NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
284 
#NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
285 
#NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
286 
#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
287 
#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
288 
#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
289 
NET "CLK_50MHZ" TNM_NET = "CLK_50MHZ";
290 
#NET "clk_reg1" TNM_NET = "clk_reg1";
291 
#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;
292 
NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
293 
 
294 
TIMEGRP "E_TX_OUTS" OFFSET=OUT 20 ns BEFORE E_TX_CLK;
295 
INST "E_TXD<0>" TNM="E_TX_OUTS";
296 
INST "E_TXD<1>" TNM="E_TX_OUTS";
297 
INST "E_TXD<2>" TNM="E_TX_OUTS";
298 
INST "E_TXD<3>" TNM="E_TX_OUTS";
299 
INST "E_TX_EN" TNM="E_TX_OUTS";
300 
 
301 
TIMEGRP "CDC_INS" OFFSET=IN 5 ns BEFORE "clk_50MHz";
302 
INST "CDC_DOUT" TNM="CDC_INS";
303 
 
304 
TIMEGRP "CDC_SPI" OFFSET= OUT 10 ns BEFORE "clk_50MHz";
305 
INST "CDC_CSn" TNM="CDC_SPI";
306 
INST "CDC_SDIN" TNM="CDC_SPI";
307 
INST "CDC_SCLK" TNM="CDC_SPI";
308 
 
309 
TIMEGRP "CDC_CLK" OFFSET= OUT 10 ns BEFORE "clk_50MHz";
310 
INST "CDC_BCLK" TNM="CDC_CLK";
311 
INST "CDC_MCK" TNM="CDC_CLK";
312 
 
313 
TIMEGRP "CDC_OUTS" OFFSET= OUT 10 ns BEFORE "clk_50MHz";
314 
#TIMEGRP "CDC_OUTS" OFFSET= OUT 0 ns BEFORE "clk_50MHz";
315 
INST "CDC_DIN" TNM="CDC_OUTS";
316 
INST "CDC_LRC_IN_OUT" TNM="CDC_OUTS";
317 
 
318 
NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
319 
 
320 
#NET "CLK_50MHZ" CLOCK_DEDICATED_ROUTE = FALSE;
321 
#PIN "dcm2_1/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
322 
#PIN "dcm1_1/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;

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