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wzab |
-------------------------------------------------------------------------------
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-- Title : FPGA Ethernet interface - block sending packets via MII Phy
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-- Project :
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-------------------------------------------------------------------------------
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-- File : desc_manager.vhd
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-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl)
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-- License : BSD License
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-- Company :
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-- Created : 2012-03-30
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wzab |
-- Last update: 2013-06-16
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wzab |
-- Platform :
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description: This file implements the state machine, which manages the
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-- table of packet descriptors, used to resend only not confirmed packets
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-------------------------------------------------------------------------------
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-- Copyright (c) 2012
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2012-03-30 1.0 WZab Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.PCK_CRC32_D8.all;
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entity eth_sender is
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port (
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-- Configuration
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peer_mac : in std_logic_vector(47 downto 0);
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my_mac : in std_logic_vector(47 downto 0);
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my_ether_type : in std_logic_vector(15 downto 0);
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set_number : in unsigned(15 downto 0);
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pkt_number : in unsigned(15 downto 0);
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retry_number : in unsigned(15 downto 0);
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transm_delay : in unsigned(31 downto 0);
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-- System interface
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clk : in std_logic;
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rst_n : in std_logic;
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-- Control interface
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ready : out std_logic;
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start : in std_logic;
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-- Data memory interface
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tx_mem_addr : out std_logic_vector(13 downto 0);
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tx_mem_data : in std_logic_vector(31 downto 0);
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-- TX Phy interface
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Tx_Clk : in std_logic;
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Tx_En : out std_logic;
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TxD : out std_logic_vector(7 downto 0)
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);
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end eth_sender;
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architecture beh1 of eth_sender is
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type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_PREAMB, WST_SEND_SOF,
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WST_SEND_HEADER, WST_SEND_DATA, WST_SEND_CRC,
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WST_SEND_COMPLETED);
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type T_ETH_SENDER_REGS is record
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state : T_ETH_SENDER_STATE;
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ready : std_logic;
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count : integer;
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byte : integer;
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mem_addr : unsigned (7 downto 0);
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crc32 : std_logic_vector(31 downto 0);
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end record;
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constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := (
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state => WST_IDLE,
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ready => '1',
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count => 0,
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byte => 0,
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mem_addr => (others => '0'),
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crc32 => (others => '0')
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) ;
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signal r, r_n : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI;
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type T_ETH_SENDER_COMB is record
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TxD : std_logic_vector(7 downto 0);
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Tx_En : std_logic;
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mem_addr : unsigned(7 downto 0);
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end record;
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constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := (
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TxD => (others => '0'),
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Tx_En => '0',
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mem_addr => (others => '0')
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);
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signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT;
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signal s_header : std_logic_vector(6*32-1 downto 0) := (others => '0');
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constant HEADER_LEN : integer := 6*4; -- 6 words,
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-- 4 bytes each
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function select_byte (
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constant vec : std_logic_vector;
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constant byte_num : integer)
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return std_logic_vector is
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variable v_byte : std_logic_vector(7 downto 0);
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begin
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-- first select byte
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v_byte := vec(vec'left-byte_num*8 downto vec'left-byte_num*8-7);
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return v_byte;
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end select_byte;
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function rev(a : in std_logic_vector)
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return std_logic_vector is
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variable result : std_logic_vector(a'range);
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alias aa : std_logic_vector(a'reverse_range) is a;
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begin
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for i in aa'range loop
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result(i) := aa(i);
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end loop;
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return result;
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end; -- function reverse_any_bus
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signal tx_rst_n, tx_rst_n_0, tx_rst_n_1 : std_logic := '0';
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signal update_flag_0, update_flag_1, update_flag : std_logic := '0';
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signal start_0, tx_start, tx_start_1, tx_start_0 : std_logic := '0';
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signal tx_ready, ready_0, ready_1 : std_logic := '0';
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type T_STATE1 is (ST1_IDLE, ST1_WAIT_NOT_READY, ST1_WAIT_NOT_START,
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ST1_WAIT_READY);
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signal state1 : T_STATE1;
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type T_STATE2 is (ST2_IDLE, ST2_WAIT_NOT_READY, ST2_WAIT_READY);
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signal state2 : T_STATE2;
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begin -- beh1
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-- Packet header
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s_header <= peer_mac & my_mac & my_ether_type & x"a5a5" &
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std_logic_vector(set_number(15 downto 0)) &
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std_logic_vector(pkt_number(5 downto 0)) &
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std_logic_vector(retry_number(9 downto 0)) &
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std_logic_vector(transm_delay);
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-- Connection of the signals
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-- The memory address is built from the packet number (6 bits) and word
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-- number (8 bits)
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tx_mem_addr <= std_logic_vector(pkt_number(5 downto 0)) & std_logic_vector(c.mem_addr);
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-- Main state machine used to send the packet
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-- W calej maszynie trzeba jeszcze dodac obsluge kolizji!!!
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-- Oprocz tego trzeba przeanalizowac poprawnosc przejsc miedzy domenami zegara
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snd1 : process (Tx_Clk, tx_rst_n)
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begin
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if tx_rst_n = '0' then -- asynchronous reset (active low)
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r <= ETH_SENDER_REGS_INI;
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TxD <= (others => '0');
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Tx_En <= '0';
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elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge
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r <= r_n;
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-- To minimize glitches and propagation delay, let's add pipeline register
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Tx_En <= c.Tx_En;
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TxD <= c.TxD;
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end if;
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end process snd1; -- snd1
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snd2 : process (r, s_header, tx_mem_data, tx_start)
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variable v_TxD : std_logic_vector(7 downto 0);
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begin -- process snd1
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-- default values
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c <= ETH_SENDER_COMB_DEFAULT;
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r_n <= r;
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case r.state is
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when WST_IDLE =>
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r_n.ready <= '1';
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if tx_start = '1' then
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r_n.ready <= '0';
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r_n.state <= WST_SEND_PREAMB;
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r_n.count <= 7;
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end if;
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when WST_SEND_PREAMB =>
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-- Trzeba dodac wykrywanie kolizji!
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c.TxD <= x"55";
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c.Tx_En <= '1';
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r_n.count <= r.count - 1;
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if r.count = 1 then
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r_n.state <= WST_SEND_SOF;
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end if;
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when WST_SEND_SOF =>
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c.TxD <= x"D5";
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c.Tx_En <= '1';
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-- Prepare for sending of header
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r_n.crc32 <= (others => '1');
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r_n.state <= WST_SEND_HEADER;
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r_n.count <= 0;
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when WST_SEND_HEADER =>
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v_TxD := select_byte(s_header, r.count);
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c.TxD <= v_TxD;
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c.Tx_En <= '1';
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r_n.crc32 <= nextCRC32_D8(rev(v_TxD), r.crc32);
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if r.count < HEADER_LEN-1 then
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r_n.count <= r.count + 1;
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else
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r_n.count <= 0;
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r_n.byte <= 0;
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r_n.mem_addr <= (others => '0');
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c.mem_addr <= (others => '0');
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r_n.state <= WST_SEND_DATA;
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end if;
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when WST_SEND_DATA =>
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-- send the data byte by byte
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v_TxD := select_byte(tx_mem_data, r.byte);
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c.TxD <= v_TxD;
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c.Tx_En <= '1';
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r_n.crc32 <= nextCRC32_D8(rev(v_TxD), r.crc32);
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if r.byte < 3 then
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r_n.byte <= r.byte + 1;
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c.mem_addr <= r.mem_addr;
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else
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r_n.byte <= 0;
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-- Check, if we have sent all the data
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if r.mem_addr < 255 then
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r_n.mem_addr <= r.mem_addr + 1;
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c.mem_addr <= r.mem_addr + 1;
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else
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-- We send the CRC
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r_n.state <= WST_SEND_CRC;
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end if;
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end if;
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when WST_SEND_CRC =>
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wzab |
v_TxD := r.crc32(31-r.byte*8 downto 24-r.byte*8);
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wzab |
c.TxD <= not rev(v_TxD);
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c.Tx_En <= '1';
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if r.byte < 3 then
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r_n.byte <= r.byte + 1;
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else
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wzab |
r_n.count <= 12; -- generate the IFG - 12 bytes = 96
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wzab |
-- bits
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r_n.state <= WST_SEND_COMPLETED;
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end if;
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when WST_SEND_COMPLETED =>
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if r.count > 0 then
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r_n.count <= r.count - 1;
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else
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r_n.ready <= '1';
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r_n.state <= WST_IDLE;
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end if;
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end case;
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end process snd2;
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-- Synchronization of the reset signal for the Tx_Clk domain
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process (Tx_Clk, rst_n)
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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tx_rst_n_0 <= '0';
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tx_rst_n_1 <= '0';
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tx_rst_n <= '0';
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elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge
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tx_rst_n_0 <= rst_n;
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tx_rst_n_1 <= tx_rst_n_0;
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tx_rst_n <= tx_rst_n_1;
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end if;
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end process;
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-- Synchronization of signals passing clock domains
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-- Signal start is sent from the Clk domain.
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-- When it is asserted, we must immediately deassert signal ready,
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-- then generate the synchronized start and after internal ready
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-- is asserted, we can output it again...
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-- Ustawienie na 1 takt zegara "clk" sygnalu start powinno zainicjowac wysylanie
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-- w tym bloku musimy zadbac o stosowne wydluzenie sygnalu start i jego synchronizacje
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-- miedzy domenami zegara...
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process (clk, rst_n)
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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ready <= '0';
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ready_1 <= '0';
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ready_0 <= '0';
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state2 <= ST2_IDLE;
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elsif clk'event and clk = '1' then -- rising clock edge
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ready_1 <= tx_ready;
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ready_0 <= ready_1;
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case state2 is
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when ST2_IDLE =>
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if start = '1' and ready_0 = '1' then
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start_0 <= '1';
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ready <= '0';
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state2 <= ST2_WAIT_NOT_READY;
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else
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ready <= ready_0; -- Needed to provide correct start!
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end if;
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when ST2_WAIT_NOT_READY =>
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if ready_0 = '0' then
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start_0 <= '0';
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state2 <= ST2_WAIT_READY;
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end if;
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when ST2_WAIT_READY =>
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if ready_0 = '1' then
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ready <= '1';
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state2 <= ST2_IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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311 |
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312 |
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process (Tx_Clk, tx_rst_n)
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313 |
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begin -- process
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314 |
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if tx_rst_n = '0' then -- asynchronous reset (active low)
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315 |
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tx_start <= '0';
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tx_start_0 <= '0';
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state1 <= ST1_IDLE;
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tx_ready <= '1';
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elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge
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320 |
7 |
wzab |
tx_start_0 <= start_0;
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321 |
3 |
wzab |
tx_start <= tx_start_0;
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322 |
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case state1 is
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323 |
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when ST1_IDLE =>
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324 |
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if tx_start = '1' then
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tx_ready <= '0'; -- this should cause tx_start to go low
|
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state1 <= ST1_WAIT_NOT_READY;
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end if;
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328 |
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when ST1_WAIT_NOT_READY =>
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329 |
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if r.ready = '0' then
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state1 <= ST1_WAIT_NOT_START;
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331 |
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end if;
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332 |
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when ST1_WAIT_NOT_START =>
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333 |
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if tx_start = '0' then
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334 |
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state1 <= ST1_WAIT_READY;
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335 |
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end if;
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336 |
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when ST1_WAIT_READY =>
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337 |
|
|
if r.ready = '1' then
|
338 |
|
|
tx_ready <= '1';
|
339 |
|
|
state1 <= ST1_IDLE;
|
340 |
|
|
end if;
|
341 |
|
|
when others => null;
|
342 |
|
|
end case;
|
343 |
|
|
end if;
|
344 |
|
|
end process;
|
345 |
|
|
|
346 |
|
|
end beh1;
|