1 |
15 |
wzab |
-------------------------------------------------------------------------------
|
2 |
|
|
-- Title : L3 FADE protocol demo for Digilent Atlys board
|
3 |
|
|
-- Project :
|
4 |
|
|
-------------------------------------------------------------------------------
|
5 |
|
|
-- File : atlys_eth_top.vhd
|
6 |
|
|
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
|
7 |
|
|
-- License : BSD License
|
8 |
|
|
-- Company :
|
9 |
|
|
-- Created : 2010-08-03
|
10 |
|
|
-- Last update: 2014-10-05
|
11 |
|
|
-- Platform :
|
12 |
|
|
-- Standard : VHDL
|
13 |
|
|
-------------------------------------------------------------------------------
|
14 |
|
|
-- Description:
|
15 |
|
|
-- This file implements the top entity, integrating all component
|
16 |
|
|
-------------------------------------------------------------------------------
|
17 |
|
|
-- Copyright (c) 2012
|
18 |
|
|
-- This is public domain code!!!
|
19 |
|
|
-------------------------------------------------------------------------------
|
20 |
|
|
-- Revisions :
|
21 |
|
|
-- Date Version Author Description
|
22 |
|
|
-- 2010-08-03 1.0 wzab Created
|
23 |
|
|
-------------------------------------------------------------------------------
|
24 |
|
|
|
25 |
|
|
|
26 |
|
|
library ieee;
|
27 |
|
|
use ieee.std_logic_1164.all;
|
28 |
|
|
use ieee.numeric_std.all;
|
29 |
|
|
library work;
|
30 |
|
|
use work.pkt_ack_pkg.all;
|
31 |
|
|
use work.desc_mgr_pkg.all;
|
32 |
|
|
|
33 |
|
|
entity atlys_eth is
|
34 |
|
|
|
35 |
|
|
port (
|
36 |
|
|
cpu_reset : in std_logic;
|
37 |
|
|
-- -- DDR2 interface
|
38 |
|
|
-- ddr2_a : out std_logic_vector(12 downto 0);
|
39 |
|
|
-- ddr2_ba : out std_logic_vector(2 downto 0);
|
40 |
|
|
-- ddr2_cas_b : out std_logic;
|
41 |
|
|
-- ddr2_cke : out std_logic;
|
42 |
|
|
-- ddr2_clk_n : out std_logic;
|
43 |
|
|
-- ddr2_clk_p : out std_logic;
|
44 |
|
|
-- ddr2_dq : inout std_logic_vector(15 downto 0);
|
45 |
|
|
-- ddr2_ldm : out std_logic;
|
46 |
|
|
-- ddr2_ldqs_n : out std_logic;
|
47 |
|
|
-- ddr2_ldqs_p : out std_logic;
|
48 |
|
|
-- ddr2_odt : out std_logic;
|
49 |
|
|
-- ddr2_ras_b : out std_logic;
|
50 |
|
|
-- ddr2_udm : out std_logic;
|
51 |
|
|
-- ddr2_udqs_n : out std_logic;
|
52 |
|
|
-- ddr2_udqs_p : out std_logic;
|
53 |
|
|
-- ddr2_we_b : out std_logic;
|
54 |
|
|
-- -- FLASH interface
|
55 |
|
|
-- flash_a : out std_logic_vector(24 downto 0);
|
56 |
|
|
-- flash_ce_b : out std_logic;
|
57 |
|
|
-- flash_d : inout std_logic_vector(7 downto 0);
|
58 |
|
|
-- flash_oe_b : out std_logic;
|
59 |
|
|
-- flash_we_b : out std_logic;
|
60 |
|
|
-- -- FMC interface
|
61 |
|
|
-- fmc_la28_n : out std_logic;
|
62 |
|
|
-- fmc_la28_p : out std_logic;
|
63 |
|
|
-- fmc_la29_n : out std_logic;
|
64 |
|
|
-- fmc_la29_p : out std_logic;
|
65 |
|
|
-- fmc_la30_n : out std_logic;
|
66 |
|
|
-- fmc_la30_p : out std_logic;
|
67 |
|
|
-- fmc_la31_n : out std_logic;
|
68 |
|
|
-- fmc_la31_p : out std_logic;
|
69 |
|
|
-- iic_scl_main : out std_logic;
|
70 |
|
|
-- iic_sda_main : out std_logic;
|
71 |
|
|
|
72 |
|
|
--gpio_hdr : in std_logic_vector(7 downto 0);
|
73 |
|
|
|
74 |
|
|
-- fmc_clk0_m2c_n : out std_logic;
|
75 |
|
|
-- fmc_clk0_m2c_p : out std_logic;
|
76 |
|
|
-- fmc_clk1_m2c_n : out std_logic;
|
77 |
|
|
-- fmc_clk1_m2c_p : out std_logic;
|
78 |
|
|
-- fmc_la00_cc_n : out std_logic;
|
79 |
|
|
-- fmc_la00_cc_p : out std_logic;
|
80 |
|
|
-- fmc_la01_cc_n : out std_logic;
|
81 |
|
|
-- fmc_la01_cc_p : out std_logic;
|
82 |
|
|
-- fmc_la02_n : out std_logic;
|
83 |
|
|
-- fmc_la02_p : out std_logic;
|
84 |
|
|
-- fmc_la03_n : out std_logic;
|
85 |
|
|
-- fmc_la03_p : out std_logic;
|
86 |
|
|
-- fmc_la04_n : out std_logic;
|
87 |
|
|
-- fmc_la04_p : out std_logic;
|
88 |
|
|
-- led : out std_logic_vector(3 downto 0);
|
89 |
|
|
switches : in std_logic_vector(7 downto 0);
|
90 |
|
|
-- flash_oen : out std_logic;
|
91 |
|
|
-- flash_wen : out std_logic;
|
92 |
|
|
-- flash_cen : out std_logic;
|
93 |
|
|
gpio_led : out std_logic_vector(7 downto 0);
|
94 |
|
|
-- PHY interface
|
95 |
|
|
phy_col : in std_logic;
|
96 |
|
|
phy_crs : in std_logic;
|
97 |
|
|
phy_int : in std_logic;
|
98 |
|
|
phy_mdc : out std_logic;
|
99 |
|
|
phy_mdio : inout std_logic;
|
100 |
|
|
phy_reset : out std_logic;
|
101 |
|
|
phy_rxclk : in std_logic;
|
102 |
|
|
phy_rxctl_rxdv : in std_logic;
|
103 |
|
|
phy_rxd : in std_logic_vector(7 downto 0);
|
104 |
|
|
phy_rxer : in std_logic;
|
105 |
|
|
phy_txclk : in std_logic;
|
106 |
|
|
phy_txctl_txen : out std_logic;
|
107 |
|
|
phy_txc_gtxclk : out std_logic;
|
108 |
|
|
phy_txd : out std_logic_vector(7 downto 0);
|
109 |
|
|
phy_txer : out std_logic;
|
110 |
|
|
sysclk : in std_logic
|
111 |
|
|
);
|
112 |
|
|
|
113 |
|
|
end atlys_eth;
|
114 |
|
|
|
115 |
|
|
architecture beh of atlys_eth is
|
116 |
|
|
|
117 |
|
|
component dp_ram_scl
|
118 |
|
|
generic (
|
119 |
|
|
DATA_WIDTH : integer;
|
120 |
|
|
ADDR_WIDTH : integer);
|
121 |
|
|
port (
|
122 |
|
|
clk_a : in std_logic;
|
123 |
|
|
we_a : in std_logic;
|
124 |
|
|
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
|
125 |
|
|
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
126 |
|
|
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
127 |
|
|
clk_b : in std_logic;
|
128 |
|
|
we_b : in std_logic;
|
129 |
|
|
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
|
130 |
|
|
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
131 |
|
|
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
132 |
|
|
end component;
|
133 |
|
|
|
134 |
|
|
component ack_fifo
|
135 |
|
|
port (
|
136 |
|
|
rst : in std_logic;
|
137 |
|
|
wr_clk : in std_logic;
|
138 |
|
|
rd_clk : in std_logic;
|
139 |
|
|
din : in std_logic_vector(pkt_ack_width-1 downto 0);
|
140 |
|
|
wr_en : in std_logic;
|
141 |
|
|
rd_en : in std_logic;
|
142 |
|
|
dout : out std_logic_vector(pkt_ack_width-1 downto 0);
|
143 |
|
|
full : out std_logic;
|
144 |
|
|
empty : out std_logic);
|
145 |
|
|
end component;
|
146 |
|
|
|
147 |
|
|
component dcm1
|
148 |
|
|
port (
|
149 |
|
|
CLK_IN1 : in std_logic;
|
150 |
|
|
CLK_OUT1 : out std_logic;
|
151 |
|
|
CLK_OUT2 : out std_logic;
|
152 |
|
|
CLK_OUT3 : out std_logic;
|
153 |
|
|
RESET : in std_logic;
|
154 |
|
|
LOCKED : out std_logic);
|
155 |
|
|
end component;
|
156 |
|
|
|
157 |
|
|
component desc_manager is
|
158 |
|
|
generic (
|
159 |
|
|
LOG2_N_OF_PKTS : integer;
|
160 |
|
|
N_OF_PKTS : integer);
|
161 |
|
|
port (
|
162 |
|
|
dta : in std_logic_vector(63 downto 0);
|
163 |
|
|
dta_we : in std_logic;
|
164 |
|
|
dta_ready : out std_logic;
|
165 |
|
|
pkt_number : out unsigned(31 downto 0);
|
166 |
|
|
seq_number : out unsigned(15 downto 0);
|
167 |
|
|
cmd_response_out : out std_logic_vector(12*8-1 downto 0);
|
168 |
|
|
snd_cmd_start : out std_logic;
|
169 |
|
|
snd_start : out std_logic;
|
170 |
|
|
snd_ready : in std_logic;
|
171 |
|
|
dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0);
|
172 |
|
|
dmem_dta : out std_logic_vector(63 downto 0);
|
173 |
|
|
dmem_we : out std_logic;
|
174 |
|
|
ack_fifo_empty : in std_logic;
|
175 |
|
|
ack_fifo_rd_en : out std_logic;
|
176 |
|
|
ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0);
|
177 |
|
|
cmd_code : out std_logic_vector(15 downto 0);
|
178 |
|
|
cmd_seq : out std_logic_vector(15 downto 0);
|
179 |
|
|
cmd_arg : out std_logic_vector(31 downto 0);
|
180 |
|
|
cmd_run : out std_logic;
|
181 |
|
|
cmd_retr_s : out std_logic;
|
182 |
|
|
cmd_ack : in std_logic;
|
183 |
|
|
cmd_response_in : in std_logic_vector(8*12-1 downto 0);
|
184 |
|
|
transmit_data : in std_logic;
|
185 |
|
|
transm_delay : out unsigned(31 downto 0);
|
186 |
|
|
dbg : out std_logic_vector(3 downto 0);
|
187 |
|
|
clk : in std_logic;
|
188 |
|
|
rst_n : in std_logic);
|
189 |
|
|
end component desc_manager;
|
190 |
|
|
|
191 |
|
|
component cmd_proc is
|
192 |
|
|
port (
|
193 |
|
|
cmd_code : in std_logic_vector(15 downto 0);
|
194 |
|
|
cmd_seq : in std_logic_vector(15 downto 0);
|
195 |
|
|
cmd_arg : in std_logic_vector(31 downto 0);
|
196 |
|
|
cmd_run : in std_logic;
|
197 |
|
|
cmd_ack : out std_logic;
|
198 |
|
|
cmd_response : out std_logic_vector(8*12-1 downto 0);
|
199 |
|
|
clk : in std_logic;
|
200 |
|
|
rst_p : in std_logic);
|
201 |
|
|
end component cmd_proc;
|
202 |
|
|
|
203 |
|
|
component eth_sender
|
204 |
|
|
port (
|
205 |
|
|
peer_mac : in std_logic_vector(47 downto 0);
|
206 |
|
|
my_mac : in std_logic_vector(47 downto 0);
|
207 |
|
|
my_ether_type : in std_logic_vector(15 downto 0);
|
208 |
|
|
pkt_number : in unsigned(31 downto 0);
|
209 |
|
|
seq_number : in unsigned(15 downto 0);
|
210 |
|
|
transm_delay : in unsigned(31 downto 0);
|
211 |
|
|
clk : in std_logic;
|
212 |
|
|
rst_n : in std_logic;
|
213 |
|
|
ready : out std_logic;
|
214 |
|
|
start : in std_logic;
|
215 |
|
|
cmd_start : in std_logic;
|
216 |
|
|
tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0);
|
217 |
|
|
tx_mem_data : in std_logic_vector(63 downto 0);
|
218 |
|
|
cmd_response : in std_logic_vector(12*8-1 downto 0);
|
219 |
|
|
Tx_Clk : in std_logic;
|
220 |
|
|
Tx_En : out std_logic;
|
221 |
|
|
TxD : out std_logic_vector(7 downto 0));
|
222 |
|
|
end component;
|
223 |
|
|
|
224 |
|
|
component eth_receiver
|
225 |
|
|
port (
|
226 |
|
|
peer_mac : out std_logic_vector(47 downto 0);
|
227 |
|
|
my_mac : in std_logic_vector(47 downto 0);
|
228 |
|
|
my_ether_type : in std_logic_vector(15 downto 0);
|
229 |
|
|
transmit_data : out std_logic;
|
230 |
|
|
restart : out std_logic;
|
231 |
|
|
ack_fifo_full : in std_logic;
|
232 |
|
|
ack_fifo_wr_en : out std_logic;
|
233 |
|
|
ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0);
|
234 |
|
|
clk : in std_logic;
|
235 |
|
|
rst_n : in std_logic;
|
236 |
|
|
dbg : out std_logic_vector(3 downto 0);
|
237 |
|
|
Rx_Clk : in std_logic;
|
238 |
|
|
Rx_Er : in std_logic;
|
239 |
|
|
Rx_Dv : in std_logic;
|
240 |
|
|
RxD : in std_logic_vector(7 downto 0));
|
241 |
|
|
end component;
|
242 |
|
|
|
243 |
|
|
component jtag_bus_ctl
|
244 |
|
|
generic (
|
245 |
|
|
d_width : integer;
|
246 |
|
|
a_width : integer);
|
247 |
|
|
port (
|
248 |
|
|
din : in std_logic_vector((d_width-1) downto 0);
|
249 |
|
|
dout : out std_logic_vector((d_width-1) downto 0);
|
250 |
|
|
addr : out std_logic_vector((a_width-1) downto 0);
|
251 |
|
|
nwr : out std_logic;
|
252 |
|
|
nrd : out std_logic);
|
253 |
|
|
end component;
|
254 |
|
|
|
255 |
|
|
|
256 |
|
|
signal my_mac : std_logic_vector(47 downto 0);
|
257 |
|
|
constant my_ether_type : std_logic_vector(15 downto 0) := x"fade";
|
258 |
|
|
signal transm_delay : unsigned(31 downto 0);
|
259 |
|
|
signal restart : std_logic;
|
260 |
|
|
signal dta : std_logic_vector(63 downto 0);
|
261 |
|
|
signal dta_we : std_logic := '0';
|
262 |
|
|
signal dta_ready : std_logic;
|
263 |
|
|
signal snd_start : std_logic;
|
264 |
|
|
signal snd_ready : std_logic;
|
265 |
|
|
signal dmem_addr : std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0);
|
266 |
|
|
signal dmem_dta : std_logic_vector(63 downto 0);
|
267 |
|
|
signal dmem_we : std_logic;
|
268 |
|
|
signal addr_a, addr_b : integer;
|
269 |
|
|
signal test_dta : unsigned(63 downto 0);
|
270 |
|
|
signal tx_mem_addr : std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0);
|
271 |
|
|
signal tx_mem_data : std_logic_vector(63 downto 0);
|
272 |
|
|
|
273 |
|
|
signal arg1, arg2, res1 : unsigned(7 downto 0);
|
274 |
|
|
signal res2 : unsigned(15 downto 0);
|
275 |
|
|
signal sender : std_logic_vector(47 downto 0);
|
276 |
|
|
signal peer_mac : std_logic_vector(47 downto 0);
|
277 |
|
|
signal inputs, din, dout : std_logic_vector(7 downto 0);
|
278 |
|
|
signal addr, leds : std_logic_vector(3 downto 0);
|
279 |
|
|
signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic;
|
280 |
|
|
signal not_cpu_reset, rst_del : std_logic;
|
281 |
|
|
|
282 |
|
|
signal set_number : unsigned(15 downto 0);
|
283 |
|
|
signal pkt_number : unsigned(31 downto 0);
|
284 |
|
|
signal seq_number : unsigned(15 downto 0) := (others => '0');
|
285 |
|
|
signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0');
|
286 |
|
|
|
287 |
|
|
|
288 |
|
|
signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0);
|
289 |
|
|
signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic;
|
290 |
|
|
signal transmit_data : std_logic := '0';
|
291 |
|
|
|
292 |
|
|
signal read_addr : std_logic_vector(15 downto 0);
|
293 |
|
|
signal read_data : std_logic_vector(15 downto 0);
|
294 |
|
|
signal read_done, read_in_progress : std_logic;
|
295 |
|
|
|
296 |
|
|
signal dbg : std_logic_vector(3 downto 0);
|
297 |
|
|
|
298 |
|
|
signal led_counter : integer := 0;
|
299 |
|
|
signal tx_counter : integer := 10000;
|
300 |
|
|
signal Reset : std_logic;
|
301 |
|
|
signal Clk_125M : std_logic;
|
302 |
|
|
signal Clk_user : std_logic;
|
303 |
|
|
signal Clk_reg : std_logic;
|
304 |
|
|
signal Speed : std_logic_vector(2 downto 0);
|
305 |
|
|
signal Rx_mac_ra : std_logic;
|
306 |
|
|
signal Rx_mac_rd : std_logic;
|
307 |
|
|
signal Rx_mac_data : std_logic_vector(31 downto 0);
|
308 |
|
|
signal Rx_mac_BE : std_logic_vector(1 downto 0);
|
309 |
|
|
signal Rx_mac_pa : std_logic;
|
310 |
|
|
signal Rx_mac_sop : std_logic;
|
311 |
|
|
signal Rx_mac_eop : std_logic;
|
312 |
|
|
signal Tx_mac_wa : std_logic;
|
313 |
|
|
signal Tx_mac_wr : std_logic;
|
314 |
|
|
signal Tx_mac_data : std_logic_vector(31 downto 0);
|
315 |
|
|
signal Tx_mac_BE : std_logic_vector(1 downto 0);
|
316 |
|
|
signal Tx_mac_sop : std_logic;
|
317 |
|
|
signal Tx_mac_eop : std_logic;
|
318 |
|
|
signal Pkg_lgth_fifo_rd : std_logic;
|
319 |
|
|
signal Pkg_lgth_fifo_ra : std_logic;
|
320 |
|
|
signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0);
|
321 |
|
|
signal Gtx_clk : std_logic;
|
322 |
|
|
signal Rx_clk : std_logic;
|
323 |
|
|
signal Tx_clk : std_logic;
|
324 |
|
|
signal Tx_er : std_logic;
|
325 |
|
|
signal Tx_en : std_logic;
|
326 |
|
|
signal Txd : std_logic_vector(7 downto 0);
|
327 |
|
|
signal Rx_er : std_logic;
|
328 |
|
|
signal Rx_dv : std_logic;
|
329 |
|
|
signal Rxd : std_logic_vector(7 downto 0);
|
330 |
|
|
signal Crs : std_logic;
|
331 |
|
|
signal Col : std_logic;
|
332 |
|
|
signal CSB : std_logic := '1';
|
333 |
|
|
signal WRB : std_logic := '1';
|
334 |
|
|
signal CD_in : std_logic_vector(15 downto 0) := (others => '0');
|
335 |
|
|
signal CD_out : std_logic_vector(15 downto 0) := (others => '0');
|
336 |
|
|
signal CA : std_logic_vector(7 downto 0) := (others => '0');
|
337 |
|
|
signal s_Mdo : std_logic;
|
338 |
|
|
signal s_MdoEn : std_logic;
|
339 |
|
|
signal s_Mdi : std_logic;
|
340 |
|
|
|
341 |
|
|
signal s_dta_we : std_logic;
|
342 |
|
|
|
343 |
|
|
-- signals related to user commands handling
|
344 |
|
|
signal cmd_response_in, cmd_response_out : std_logic_vector(12*8-1 downto 0) := (others => '0');
|
345 |
|
|
signal cmd_start : std_logic := '0';
|
346 |
|
|
signal cmd_run : std_logic := '0';
|
347 |
|
|
signal cmd_retr_s : std_logic := '0';
|
348 |
|
|
signal cmd_ack : std_logic := '0';
|
349 |
|
|
signal cmd_code : std_logic_vector(15 downto 0) := (others => '0');
|
350 |
|
|
signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0');
|
351 |
|
|
signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0');
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
begin -- beh
|
355 |
|
|
|
356 |
|
|
-- Allow selection of MAC with the DIP switch to allow testing
|
357 |
|
|
-- with multiple boards!
|
358 |
|
|
with switches(1 downto 0) select
|
359 |
|
|
my_mac <=
|
360 |
|
|
x"de_ad_ba_be_be_ef" when "00",
|
361 |
|
|
x"de_ad_ba_be_be_e1" when "01",
|
362 |
|
|
x"de_ad_ba_be_be_e2" when "10",
|
363 |
|
|
x"de_ad_ba_be_be_e3" when "11";
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
-- iic_sda_main <= 'Z';
|
367 |
|
|
-- iic_scl_main <= 'Z';
|
368 |
|
|
|
369 |
|
|
not_cpu_reset <= not cpu_reset;
|
370 |
|
|
rst_p <= not rst_n;
|
371 |
|
|
|
372 |
|
|
-- flash_oe_b <= '1';
|
373 |
|
|
-- flash_we_b <= '1';
|
374 |
|
|
-- flash_ce_b <= '1';
|
375 |
|
|
|
376 |
|
|
tx_clk <= Clk_125M;
|
377 |
|
|
rx_clk <= phy_rxclk;
|
378 |
|
|
|
379 |
|
|
Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra;
|
380 |
|
|
|
381 |
|
|
addr_a <= to_integer(unsigned(dmem_addr));
|
382 |
|
|
addr_b <= to_integer(unsigned(tx_mem_addr));
|
383 |
|
|
|
384 |
|
|
dp_ram_scl_1 : dp_ram_scl
|
385 |
|
|
generic map (
|
386 |
|
|
DATA_WIDTH => 64,
|
387 |
|
|
ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT)
|
388 |
|
|
port map (
|
389 |
|
|
clk_a => clk_user,
|
390 |
|
|
we_a => dmem_we,
|
391 |
|
|
addr_a => dmem_addr,
|
392 |
|
|
data_a => dmem_dta,
|
393 |
|
|
q_a => open,
|
394 |
|
|
clk_b => Tx_clk,
|
395 |
|
|
we_b => '0',
|
396 |
|
|
addr_b => tx_mem_addr,
|
397 |
|
|
data_b => (others => '0'),
|
398 |
|
|
q_b => tx_mem_data);
|
399 |
|
|
|
400 |
|
|
desc_manager_1 : desc_manager
|
401 |
|
|
generic map (
|
402 |
|
|
LOG2_N_OF_PKTS => LOG2_N_OF_PKTS,
|
403 |
|
|
N_OF_PKTS => N_OF_PKTS)
|
404 |
|
|
port map (
|
405 |
|
|
dta => dta,
|
406 |
|
|
dta_we => dta_we,
|
407 |
|
|
dta_ready => dta_ready,
|
408 |
|
|
pkt_number => pkt_number,
|
409 |
|
|
seq_number => seq_number,
|
410 |
|
|
cmd_response_out => cmd_response_out,
|
411 |
|
|
snd_start => snd_start,
|
412 |
|
|
snd_cmd_start => cmd_start,
|
413 |
|
|
snd_ready => snd_ready,
|
414 |
|
|
dmem_addr => dmem_addr,
|
415 |
|
|
dmem_dta => dmem_dta,
|
416 |
|
|
dmem_we => dmem_we,
|
417 |
|
|
ack_fifo_empty => ack_fifo_empty,
|
418 |
|
|
ack_fifo_rd_en => ack_fifo_rd_en,
|
419 |
|
|
ack_fifo_dout => ack_fifo_dout,
|
420 |
|
|
cmd_code => cmd_code,
|
421 |
|
|
cmd_seq => cmd_seq,
|
422 |
|
|
cmd_arg => cmd_arg,
|
423 |
|
|
cmd_run => cmd_run,
|
424 |
|
|
cmd_retr_s => cmd_retr_s,
|
425 |
|
|
cmd_ack => cmd_ack,
|
426 |
|
|
cmd_response_in => cmd_response_in,
|
427 |
|
|
transmit_data => transmit_data,
|
428 |
|
|
transm_delay => transm_delay,
|
429 |
|
|
dbg => dbg,
|
430 |
|
|
clk => clk_user,
|
431 |
|
|
rst_n => rst_n);
|
432 |
|
|
|
433 |
|
|
cmd_proc_1 : cmd_proc
|
434 |
|
|
port map (
|
435 |
|
|
cmd_code => cmd_code,
|
436 |
|
|
cmd_seq => cmd_seq,
|
437 |
|
|
cmd_arg => cmd_arg,
|
438 |
|
|
cmd_run => cmd_run,
|
439 |
|
|
cmd_ack => cmd_ack,
|
440 |
|
|
cmd_response => cmd_response_in,
|
441 |
|
|
clk => clk_user,
|
442 |
|
|
rst_p => rst_p);
|
443 |
|
|
|
444 |
|
|
eth_sender_1 : eth_sender
|
445 |
|
|
port map (
|
446 |
|
|
peer_mac => peer_mac,
|
447 |
|
|
my_mac => my_mac,
|
448 |
|
|
my_ether_type => my_ether_type,
|
449 |
|
|
pkt_number => pkt_number,
|
450 |
|
|
seq_number => seq_number,
|
451 |
|
|
transm_delay => transm_delay,
|
452 |
|
|
clk => clk_user,
|
453 |
|
|
rst_n => rst_n,
|
454 |
|
|
ready => snd_ready,
|
455 |
|
|
start => snd_start,
|
456 |
|
|
cmd_start => cmd_start,
|
457 |
|
|
tx_mem_addr => tx_mem_addr,
|
458 |
|
|
tx_mem_data => tx_mem_data,
|
459 |
|
|
cmd_response => cmd_response_out,
|
460 |
|
|
Tx_Clk => tx_clk,
|
461 |
|
|
Tx_En => phy_txctl_txen,
|
462 |
|
|
TxD => PHY_Txd);
|
463 |
|
|
|
464 |
|
|
eth_receiver_2 : eth_receiver
|
465 |
|
|
port map (
|
466 |
|
|
peer_mac => peer_mac,
|
467 |
|
|
my_mac => my_mac,
|
468 |
|
|
my_ether_type => my_ether_type,
|
469 |
|
|
transmit_data => transmit_data,
|
470 |
|
|
restart => restart,
|
471 |
|
|
ack_fifo_full => ack_fifo_full,
|
472 |
|
|
ack_fifo_wr_en => ack_fifo_wr_en,
|
473 |
|
|
ack_fifo_din => ack_fifo_din,
|
474 |
|
|
clk => clk_user,
|
475 |
|
|
rst_n => rst_n,
|
476 |
|
|
dbg => open, --dbg,
|
477 |
|
|
Rx_Clk => rx_clk,
|
478 |
|
|
Rx_Er => PHY_Rxer,
|
479 |
|
|
Rx_Dv => phy_rxctl_rxdv,
|
480 |
|
|
RxD => PHY_Rxd);
|
481 |
|
|
|
482 |
|
|
dcm1_1 : dcm1
|
483 |
|
|
port map (
|
484 |
|
|
CLK_IN1 => sysclk,
|
485 |
|
|
CLK_OUT1 => Clk_125M,
|
486 |
|
|
CLK_OUT2 => Clk_user,
|
487 |
|
|
CLK_OUT3 => Clk_reg,
|
488 |
|
|
RESET => not_cpu_reset,
|
489 |
|
|
LOCKED => dcm_locked);
|
490 |
|
|
|
491 |
|
|
process (Clk_user, not_cpu_reset)
|
492 |
|
|
begin -- process
|
493 |
|
|
if not_cpu_reset = '1' then -- asynchronous reset (active low)
|
494 |
|
|
rst_n <= '0';
|
495 |
|
|
rst_del <= '0';
|
496 |
|
|
elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
|
497 |
|
|
if restart = '1' then
|
498 |
|
|
rst_n <= '0';
|
499 |
|
|
rst_del <= '0';
|
500 |
|
|
else
|
501 |
|
|
if dcm_locked = '1' then
|
502 |
|
|
rst_del <= '1';
|
503 |
|
|
rst_n <= rst_del;
|
504 |
|
|
end if;
|
505 |
|
|
end if;
|
506 |
|
|
end if;
|
507 |
|
|
end process;
|
508 |
|
|
|
509 |
|
|
-- reset
|
510 |
|
|
|
511 |
|
|
phy_reset <= rst_n;
|
512 |
|
|
|
513 |
|
|
-- Connection of MDI
|
514 |
|
|
--s_Mdi <= PHY_MDIO;
|
515 |
|
|
--PHY_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo;
|
516 |
|
|
|
517 |
|
|
phy_txer <= '0';
|
518 |
|
|
phy_mdio <= 'Z';
|
519 |
|
|
phy_mdc <= '0';
|
520 |
|
|
|
521 |
|
|
phy_txc_gtxclk <= tx_clk;
|
522 |
|
|
|
523 |
|
|
ack_fifo_1 : ack_fifo
|
524 |
|
|
port map (
|
525 |
|
|
rst => rst_p,
|
526 |
|
|
wr_clk => rx_clk,
|
527 |
|
|
rd_clk => Clk_user,
|
528 |
|
|
din => ack_fifo_din,
|
529 |
|
|
wr_en => ack_fifo_wr_en,
|
530 |
|
|
rd_en => ack_fifo_rd_en,
|
531 |
|
|
dout => ack_fifo_dout,
|
532 |
|
|
full => ack_fifo_full,
|
533 |
|
|
empty => ack_fifo_empty);
|
534 |
|
|
|
535 |
|
|
--E_TXD <= s_Txd(3 downto 0);
|
536 |
|
|
--s_Rxd <= "0000" & E_RXD;
|
537 |
|
|
|
538 |
|
|
-- signal generator
|
539 |
|
|
|
540 |
|
|
dta <= std_logic_vector(test_dta);
|
541 |
|
|
s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0';
|
542 |
|
|
dta_we <= s_dta_we;
|
543 |
|
|
|
544 |
|
|
process (Clk_user, rst_n)
|
545 |
|
|
begin -- process
|
546 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
547 |
|
|
test_dta <= (others => '0');
|
548 |
|
|
elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
|
549 |
|
|
if s_dta_we = '1' then
|
550 |
|
|
test_dta <= test_dta + x"1234567809abcdef";
|
551 |
|
|
end if;
|
552 |
|
|
end if;
|
553 |
|
|
end process;
|
554 |
|
|
|
555 |
|
|
-- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2));
|
556 |
|
|
gpio_led(0) <= snd_ready;
|
557 |
|
|
gpio_led(1) <= transmit_data;
|
558 |
|
|
gpio_led(2) <= not_cpu_reset;
|
559 |
|
|
gpio_led(3) <= Tx_mac_wa;
|
560 |
|
|
gpio_led(7 downto 4) <= dbg;
|
561 |
|
|
--gpio_led(6) <= ack_fifo_full;
|
562 |
|
|
--gpio_led(7) <= not ack_fifo_empty;
|
563 |
|
|
end beh;
|