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[/] [fast-crc/] [trunk/] [syn/] [.synopsys_dc.setup] - Blame information for rev 2

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designer = "tde"
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company = "TdE LUND"
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cache_read  = ./;
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cache_write = ./;
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search_path = { /usr/local-tde/cad1/amslibs/v3.20/synopsys/csx_3.3V } + search_path
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link_library = { csx_HRDLIB.db csx_IOLIB_3M.db standard.sldb dw01.sldb dw02.sldb}
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target_library = { csx_HRDLIB.db csx_IOLIB_3M.db }
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symbol_library = { csxs.sdb };
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synthetic_library = { standard.sldb dw01.sldb dw02.sldb }
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verilogout_no_tri = true
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bus_naming_style = "%s_%d"
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bus_dimension_separator_style = "_"
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define_name_rules opus -reserved_words {"disable", "abs", "access", "after", \
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  "alias", "all", "and", "architecture", "array", "assert", "attribute", \
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  "begin", "block", "body", "buffer", "bus", "case", "component", \
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  "configuration", "constant", "disconnect", "downto", "else", "elsif", \
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  "end", "entity", "exit", "file", "for", "function", "generate", "generic", \
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  "guarded", "if", "in", "inout", "is", "label", "library", "linkage", \
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  "loop", "map", "mod", "nand", "new", "next", "nor", "not", "null",  "of", \
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  "on", "open", "or", "others", "out", "overflow", "package", "port", "procedure", \
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  "process", "range", "record", "register", "rem", "report", "return", \
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  "select", "severity", "sign", "signal", "subtype", "then", "to", "transport", \
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  "type", "units", "until", "use", "variable", "wait", "when", "while", \
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  "with", "xor"} \
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  -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_" \
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  -case_insensitive -collapse_name_space -replacement_char "X"
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vhdlout_bit_type = "std_logic"
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vhdlout_bit_vector_type = "std_logic_vector"
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vhdlout_single_bit = "VECTOR"
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vhdlout_preserve_hierarchical_types = "VECTOR"
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vhdlout_dont_write_types = true
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vhdlout_write_components = true
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vhdlout_use_packages = { \
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                         "IEEE.std_logic_1164", \
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                         "IEEE.std_logic_arith", \
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                         "csx_HRDLIB.Vcomponents", \
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                         "csx_IOLIB_3M.Vcomponents" \
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                        }
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