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-------------------------------------------------------------------------------
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity CRC_top is
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port (
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phi1 : in std_logic;
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-- We will use the two phase discipline
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-- which we don't generate.
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phi2 : in std_logic;
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reset : in std_logic; -- #RESET
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input : in std_logic_vector(15 downto 0);
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-- The serial/parallel conversion has
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-- been made somewhere else
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fcs_out : out std_logic_vector(31 downto 0));
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-- "inout" because we have to read this value (feedback to the multiplier)
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end CRC_top;
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architecture structural of CRC_top is
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component input_wait
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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phi2 : in std_logic;
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input : in std_logic_vector(15 downto 0);
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output : out std_logic_vector(15 downto 0));
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end component;
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component gf_multiplier
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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phi2 : in std_logic;
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input : in std_logic_vector(31 downto 0);
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output_fcs : out std_logic_vector(15 downto 0); -- LS Word
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-- "inout" since we have to read this value (feedback)
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output_xor : out std_logic_vector(15 downto 0)); -- MS Word
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end component;
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component big_xor
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input_input : in std_logic_vector(15 downto 0);
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fcs_input : in std_logic_vector(15 downto 0);
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gf_input : in std_logic_vector(15 downto 0);
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output : out std_logic_vector(31 downto 0));
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end component;
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component ff_reset is
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port (
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phi2 : in std_logic;
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reset_glitch : in std_logic;
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reset_clean : out std_logic);
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end component;
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signal wait_intermediate : std_logic_vector(15 downto 0);
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-- Connects the input_wait component with the big_xor one
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signal fcs_intermediate : std_logic_vector(15 downto 0);
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-- Connects the multiplier with the output register
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signal xor_intermediate : std_logic_vector(15 downto 0);
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-- Connects the multiplier with the final XOR
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signal fcs_out_read : std_logic_vector (31 downto 0);
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-- This signal will avoid the use of "inout" ports
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signal reset_intermediate : std_logic;
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-- Clean reset to feed the whole circuit
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begin
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ff_reset_1 : ff_reset port map (phi2 => phi2, reset_glitch => reset,
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reset_clean => reset_intermediate);
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input_wait_1 : input_wait port map (reset => reset_intermediate, phi1 => phi1,
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phi2 => phi2, input => input,
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output => wait_intermediate);
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gf_multiplier_1 : gf_multiplier port map (reset => reset_intermediate,
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phi1 => phi1, phi2=> phi2,
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input => fcs_out_read,
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output_xor => xor_intermediate,
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output_fcs => fcs_intermediate);
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big_xor_1 : big_xor port map (reset => reset_intermediate, phi2 => phi2,
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input_input => wait_intermediate,
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fcs_input => fcs_intermediate,
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gf_input => xor_intermediate,
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output => fcs_out_read);
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fcs_out <= fcs_out_read;
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end structural;
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configuration cfg_CRC_top_structural of CRC_top is
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for structural
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for input_wait_1 : input_wait use entity work.input_wait(structural); end for;
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for gf_multiplier_1 : gf_multiplier use entity work.gf_multiplier(structural); end for;
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for big_xor_1 : big_xor use entity work.big_xor(behavior); end for;
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for ff_reset_1 : ff_reset use entity work.ff_reset(behavior); end for;
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end for;
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end cfg_CRC_top_structural;
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