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[/] [fast-crc/] [trunk/] [vhdl/] [CRC_top_syn.vhd] - Blame information for rev 2

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1 2 trueno 
 
2 
library IEEE;
3 
library csx_HRDLIB;
4 
library csx_IOLIB_3M;
5 
 
6 
use IEEE.std_logic_1164.all;
7 
use IEEE.std_logic_arith.all;
8 
use csx_HRDLIB.Vcomponents.all;
9 
use csx_IOLIB_3M.Vcomponents.all;
10 
 
11 
entity CRC_top is
12 
 
13 
   port( phi1, phi2, reset : in std_logic;  input : in std_logic_vector (0 to
14 
         15);  fcs_out : out std_logic_vector (0 to 31));
15 
 
16 
end CRC_top;
17 
 
18 
architecture SYN_structural of CRC_top is
19 
 
20 
   component ff_reset
21 
      port( phi2, reset_glitch : in std_logic;  reset_clean : out std_logic);
22 
   end component;
23 
 
24 
   component input_wait
25 
      port( phi1, phi2, reset : in std_logic;  input : in std_logic_vector (0
26 
            to 15);  output : out std_logic_vector (0 to 15));
27 
   end component;
28 
 
29 
   component gf_multiplier
30 
      port( reset, phi1, phi2 : in std_logic;  input : in std_logic_vector (0
31 
            to 31);  output_fcs, output_xor : out std_logic_vector (0 to 15));
32 
   end component;
33 
 
34 
   component big_xor
35 
      port( reset, phi2 : in std_logic;  input_input, fcs_input, gf_input : in
36 
            std_logic_vector (0 to 15);  output : out std_logic_vector (0 to
37 
            31));
38 
   end component;
39 
 
40 
   signal wait_intermediate_10, xor_intermediate_0, fcs_out_15, fcs_out_4,
41 
      fcs_intermediate_10, fcs_intermediate_8, fcs_out_29, xor_intermediate_9,
42 
      wait_intermediate_2, fcs_intermediate_6, fcs_intermediate_1, fcs_out_27,
43 
      fcs_out_20, wait_intermediate_5, reset_intermediate, xor_intermediate_11,
44 
      fcs_out_3, wait_intermediate_15, wait_intermediate_14,
45 
      wait_intermediate_13, wait_intermediate_11, wait_intermediate_4,
46 
      xor_intermediate_7, fcs_out_12, wait_intermediate_3, fcs_intermediate_7,
47 
      fcs_out_26, fcs_out_13, xor_intermediate_6, fcs_out_2,
48 
      xor_intermediate_10, fcs_intermediate_9, fcs_out_28, fcs_out_5,
49 
      fcs_intermediate_0, xor_intermediate_1, fcs_out_14, fcs_out_21,
50 
      xor_intermediate_8, wait_intermediate_8, fcs_intermediate_11,
51 
      xor_intermediate_15, xor_intermediate_3, fcs_out_31, fcs_out_16,
52 
      fcs_out_7, fcs_intermediate_13, wait_intermediate_6, wait_intermediate_1,
53 
      fcs_intermediate_5, fcs_intermediate_2, fcs_out_24, fcs_out_23, fcs_out_9
54 
      , fcs_intermediate_14, fcs_out_18, xor_intermediate_12,
55 
      fcs_intermediate_15, xor_intermediate_4, fcs_out_11, fcs_out_0,
56 
      wait_intermediate_7, fcs_out_19, fcs_intermediate_4, fcs_out_8,
57 
      fcs_out_25, xor_intermediate_13, xor_intermediate_5, fcs_out_10,
58 
      fcs_out_1, xor_intermediate_14, wait_intermediate_12, wait_intermediate_9
59 
      , wait_intermediate_0, fcs_intermediate_3, xor_intermediate_2, fcs_out_30
60 
      , fcs_out_6, fcs_out_17, fcs_out_22, fcs_intermediate_12 : std_logic;
61 
 
62 
begin
63 
   fcs_out <= ( fcs_out_31, fcs_out_30, fcs_out_29, fcs_out_28, fcs_out_27,
64 
      fcs_out_26, fcs_out_25, fcs_out_24, fcs_out_23, fcs_out_22, fcs_out_21,
65 
      fcs_out_20, fcs_out_19, fcs_out_18, fcs_out_17, fcs_out_16, fcs_out_15,
66 
      fcs_out_14, fcs_out_13, fcs_out_12, fcs_out_11, fcs_out_10, fcs_out_9,
67 
      fcs_out_8, fcs_out_7, fcs_out_6, fcs_out_5, fcs_out_4, fcs_out_3,
68 
      fcs_out_2, fcs_out_1, fcs_out_0 );
69 
 
70 
   ff_reset_1 : ff_reset port map( phi2 => phi2, reset_glitch => reset,
71 
                           reset_clean => reset_intermediate);
72 
   input_wait_1 : input_wait port map( phi1 => phi1, phi2 => phi2, reset =>
73 
                           reset_intermediate, input(0) => input(0), input(1)
74 
                           => input(1), input(2) => input(2), input(3) =>
75 
                           input(3), input(4) => input(4), input(5) => input(5)
76 
                           , input(6) => input(6), input(7) => input(7),
77 
                           input(8) => input(8), input(9) => input(9),
78 
                           input(10) => input(10), input(11) => input(11),
79 
                           input(12) => input(12), input(13) => input(13),
80 
                           input(14) => input(14), input(15) => input(15),
81 
                           output(0) => wait_intermediate_15, output(1) =>
82 
                           wait_intermediate_14, output(2) =>
83 
                           wait_intermediate_13, output(3) =>
84 
                           wait_intermediate_12, output(4) =>
85 
                           wait_intermediate_11, output(5) =>
86 
                           wait_intermediate_10, output(6) =>
87 
                           wait_intermediate_9, output(7) =>
88 
                           wait_intermediate_8, output(8) =>
89 
                           wait_intermediate_7, output(9) =>
90 
                           wait_intermediate_6, output(10) =>
91 
                           wait_intermediate_5, output(11) =>
92 
                           wait_intermediate_4, output(12) =>
93 
                           wait_intermediate_3, output(13) =>
94 
                           wait_intermediate_2, output(14) =>
95 
                           wait_intermediate_1, output(15) =>
96 
                           wait_intermediate_0);
97 
   gf_multiplier_1 : gf_multiplier port map( reset => reset_intermediate, phi1
98 
                           => phi1, phi2 => phi2, input(0) => fcs_out_31,
99 
                           input(1) => fcs_out_30, input(2) => fcs_out_29,
100 
                           input(3) => fcs_out_28, input(4) => fcs_out_27,
101 
                           input(5) => fcs_out_26, input(6) => fcs_out_25,
102 
                           input(7) => fcs_out_24, input(8) => fcs_out_23,
103 
                           input(9) => fcs_out_22, input(10) => fcs_out_21,
104 
                           input(11) => fcs_out_20, input(12) => fcs_out_19,
105 
                           input(13) => fcs_out_18, input(14) => fcs_out_17,
106 
                           input(15) => fcs_out_16, input(16) => fcs_out_15,
107 
                           input(17) => fcs_out_14, input(18) => fcs_out_13,
108 
                           input(19) => fcs_out_12, input(20) => fcs_out_11,
109 
                           input(21) => fcs_out_10, input(22) => fcs_out_9,
110 
                           input(23) => fcs_out_8, input(24) => fcs_out_7,
111 
                           input(25) => fcs_out_6, input(26) => fcs_out_5,
112 
                           input(27) => fcs_out_4, input(28) => fcs_out_3,
113 
                           input(29) => fcs_out_2, input(30) => fcs_out_1,
114 
                           input(31) => fcs_out_0, output_fcs(0) =>
115 
                           fcs_intermediate_15, output_fcs(1) =>
116 
                           fcs_intermediate_14, output_fcs(2) =>
117 
                           fcs_intermediate_13, output_fcs(3) =>
118 
                           fcs_intermediate_12, output_fcs(4) =>
119 
                           fcs_intermediate_11, output_fcs(5) =>
120 
                           fcs_intermediate_10, output_fcs(6) =>
121 
                           fcs_intermediate_9, output_fcs(7) =>
122 
                           fcs_intermediate_8, output_fcs(8) =>
123 
                           fcs_intermediate_7, output_fcs(9) =>
124 
                           fcs_intermediate_6, output_fcs(10) =>
125 
                           fcs_intermediate_5, output_fcs(11) =>
126 
                           fcs_intermediate_4, output_fcs(12) =>
127 
                           fcs_intermediate_3, output_fcs(13) =>
128 
                           fcs_intermediate_2, output_fcs(14) =>
129 
                           fcs_intermediate_1, output_fcs(15) =>
130 
                           fcs_intermediate_0, output_xor(0) =>
131 
                           xor_intermediate_15, output_xor(1) =>
132 
                           xor_intermediate_14, output_xor(2) =>
133 
                           xor_intermediate_13, output_xor(3) =>
134 
                           xor_intermediate_12, output_xor(4) =>
135 
                           xor_intermediate_11, output_xor(5) =>
136 
                           xor_intermediate_10, output_xor(6) =>
137 
                           xor_intermediate_9, output_xor(7) =>
138 
                           xor_intermediate_8, output_xor(8) =>
139 
                           xor_intermediate_7, output_xor(9) =>
140 
                           xor_intermediate_6, output_xor(10) =>
141 
                           xor_intermediate_5, output_xor(11) =>
142 
                           xor_intermediate_4, output_xor(12) =>
143 
                           xor_intermediate_3, output_xor(13) =>
144 
                           xor_intermediate_2, output_xor(14) =>
145 
                           xor_intermediate_1, output_xor(15) =>
146 
                           xor_intermediate_0);
147 
   big_xor_1 : big_xor port map( reset => reset_intermediate, phi2 => phi2,
148 
                           input_input(0) => wait_intermediate_15,
149 
                           input_input(1) => wait_intermediate_14,
150 
                           input_input(2) => wait_intermediate_13,
151 
                           input_input(3) => wait_intermediate_12,
152 
                           input_input(4) => wait_intermediate_11,
153 
                           input_input(5) => wait_intermediate_10,
154 
                           input_input(6) => wait_intermediate_9,
155 
                           input_input(7) => wait_intermediate_8,
156 
                           input_input(8) => wait_intermediate_7,
157 
                           input_input(9) => wait_intermediate_6,
158 
                           input_input(10) => wait_intermediate_5,
159 
                           input_input(11) => wait_intermediate_4,
160 
                           input_input(12) => wait_intermediate_3,
161 
                           input_input(13) => wait_intermediate_2,
162 
                           input_input(14) => wait_intermediate_1,
163 
                           input_input(15) => wait_intermediate_0, fcs_input(0)
164 
                           => fcs_intermediate_15, fcs_input(1) =>
165 
                           fcs_intermediate_14, fcs_input(2) =>
166 
                           fcs_intermediate_13, fcs_input(3) =>
167 
                           fcs_intermediate_12, fcs_input(4) =>
168 
                           fcs_intermediate_11, fcs_input(5) =>
169 
                           fcs_intermediate_10, fcs_input(6) =>
170 
                           fcs_intermediate_9, fcs_input(7) =>
171 
                           fcs_intermediate_8, fcs_input(8) =>
172 
                           fcs_intermediate_7, fcs_input(9) =>
173 
                           fcs_intermediate_6, fcs_input(10) =>
174 
                           fcs_intermediate_5, fcs_input(11) =>
175 
                           fcs_intermediate_4, fcs_input(12) =>
176 
                           fcs_intermediate_3, fcs_input(13) =>
177 
                           fcs_intermediate_2, fcs_input(14) =>
178 
                           fcs_intermediate_1, fcs_input(15) =>
179 
                           fcs_intermediate_0, gf_input(0) =>
180 
                           xor_intermediate_15, gf_input(1) =>
181 
                           xor_intermediate_14, gf_input(2) =>
182 
                           xor_intermediate_13, gf_input(3) =>
183 
                           xor_intermediate_12, gf_input(4) =>
184 
                           xor_intermediate_11, gf_input(5) =>
185 
                           xor_intermediate_10, gf_input(6) =>
186 
                           xor_intermediate_9, gf_input(7) =>
187 
                           xor_intermediate_8, gf_input(8) =>
188 
                           xor_intermediate_7, gf_input(9) =>
189 
                           xor_intermediate_6, gf_input(10) =>
190 
                           xor_intermediate_5, gf_input(11) =>
191 
                           xor_intermediate_4, gf_input(12) =>
192 
                           xor_intermediate_3, gf_input(13) =>
193 
                           xor_intermediate_2, gf_input(14) =>
194 
                           xor_intermediate_1, gf_input(15) =>
195 
                           xor_intermediate_0, output(0) => fcs_out_31,
196 
                           output(1) => fcs_out_30, output(2) => fcs_out_29,
197 
                           output(3) => fcs_out_28, output(4) => fcs_out_27,
198 
                           output(5) => fcs_out_26, output(6) => fcs_out_25,
199 
                           output(7) => fcs_out_24, output(8) => fcs_out_23,
200 
                           output(9) => fcs_out_22, output(10) => fcs_out_21,
201 
                           output(11) => fcs_out_20, output(12) => fcs_out_19,
202 
                           output(13) => fcs_out_18, output(14) => fcs_out_17,
203 
                           output(15) => fcs_out_16, output(16) => fcs_out_15,
204 
                           output(17) => fcs_out_14, output(18) => fcs_out_13,
205 
                           output(19) => fcs_out_12, output(20) => fcs_out_11,
206 
                           output(21) => fcs_out_10, output(22) => fcs_out_9,
207 
                           output(23) => fcs_out_8, output(24) => fcs_out_7,
208 
                           output(25) => fcs_out_6, output(26) => fcs_out_5,
209 
                           output(27) => fcs_out_4, output(28) => fcs_out_3,
210 
                           output(29) => fcs_out_2, output(30) => fcs_out_1,
211 
                           output(31) => fcs_out_0);
212 
 
213 
end SYN_structural;
214 
 
215 
library IEEE;
216 
library csx_HRDLIB;
217 
library csx_IOLIB_3M;
218 
 
219 
use IEEE.std_logic_1164.all;
220 
use IEEE.std_logic_arith.all;
221 
use csx_HRDLIB.Vcomponents.all;
222 
use csx_IOLIB_3M.Vcomponents.all;
223 
 
224 
entity ff_reset is
225 
 
226 
   port( phi2, reset_glitch : in std_logic;  reset_clean : out std_logic);
227 
 
228 
end ff_reset;
229 
 
230 
architecture SYN_behavior of ff_reset is
231 
 
232 
   component IN8
233 
      port( A : in std_logic;  Q : out std_logic);
234 
   end component;
235 
 
236 
   component DF8
237 
      port( C, D : in std_logic;  Q, QN : out std_logic);
238 
   end component;
239 
 
240 
   signal n15, n20 : std_logic;
241 
 
242 
begin
243 
 
244 
   U9 : IN8 port map( A => n15, Q => reset_clean);
245 
   reset_clean_reg : DF8 port map( C => phi2, D => reset_glitch, Q => n20, QN
246 
                           => n15);
247 
 
248 
end SYN_behavior;
249 
 
250 
library IEEE;
251 
library csx_HRDLIB;
252 
library csx_IOLIB_3M;
253 
 
254 
use IEEE.std_logic_1164.all;
255 
use IEEE.std_logic_arith.all;
256 
use csx_HRDLIB.Vcomponents.all;
257 
use csx_IOLIB_3M.Vcomponents.all;
258 
 
259 
entity input_phi2_register_0 is
260 
 
261 
   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
262 
         output : out std_logic_vector (0 to 15));
263 
 
264 
end input_phi2_register_0;
265 
 
266 
architecture SYN_behavior_0 of input_phi2_register_0 is
267 
 
268 
   component DFA2
269 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
270 
   end component;
271 
 
272 
   component BU4
273 
      port( A : in std_logic;  Q : out std_logic);
274 
   end component;
275 
 
276 
   signal n75, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118
277 
      , n119, n120, n121, n122, n123 : std_logic;
278 
 
279 
begin
280 
 
281 
   output_reg_15 : DFA2 port map( C => phi2, D => input(0), Q => output(0), QN
282 
                           => n108, RN => n75);
283 
   output_reg_14 : DFA2 port map( C => phi2, D => input(1), Q => output(1), QN
284 
                           => n109, RN => n75);
285 
   output_reg_13 : DFA2 port map( C => phi2, D => input(2), Q => output(2), QN
286 
                           => n110, RN => n75);
287 
   output_reg_12 : DFA2 port map( C => phi2, D => input(3), Q => output(3), QN
288 
                           => n111, RN => n75);
289 
   output_reg_11 : DFA2 port map( C => phi2, D => input(4), Q => output(4), QN
290 
                           => n112, RN => n75);
291 
   output_reg_10 : DFA2 port map( C => phi2, D => input(5), Q => output(5), QN
292 
                           => n113, RN => n75);
293 
   output_reg_9 : DFA2 port map( C => phi2, D => input(6), Q => output(6), QN
294 
                           => n114, RN => n75);
295 
   output_reg_8 : DFA2 port map( C => phi2, D => input(7), Q => output(7), QN
296 
                           => n115, RN => n75);
297 
   output_reg_7 : DFA2 port map( C => phi2, D => input(8), Q => output(8), QN
298 
                           => n116, RN => n75);
299 
   output_reg_6 : DFA2 port map( C => phi2, D => input(9), Q => output(9), QN
300 
                           => n117, RN => n75);
301 
   output_reg_5 : DFA2 port map( C => phi2, D => input(10), Q => output(10), QN
302 
                           => n118, RN => n75);
303 
   output_reg_4 : DFA2 port map( C => phi2, D => input(11), Q => output(11), QN
304 
                           => n119, RN => n75);
305 
   output_reg_3 : DFA2 port map( C => phi2, D => input(12), Q => output(12), QN
306 
                           => n120, RN => n75);
307 
   output_reg_2 : DFA2 port map( C => phi2, D => input(13), Q => output(13), QN
308 
                           => n121, RN => n75);
309 
   output_reg_1 : DFA2 port map( C => phi2, D => input(14), Q => output(14), QN
310 
                           => n122, RN => n75);
311 
   output_reg_0 : DFA2 port map( C => phi2, D => input(15), Q => output(15), QN
312 
                           => n123, RN => n75);
313 
   U48 : BU4 port map( A => reset, Q => n75);
314 
 
315 
end SYN_behavior_0;
316 
 
317 
library IEEE;
318 
library csx_HRDLIB;
319 
library csx_IOLIB_3M;
320 
 
321 
use IEEE.std_logic_1164.all;
322 
use IEEE.std_logic_arith.all;
323 
use csx_HRDLIB.Vcomponents.all;
324 
use csx_IOLIB_3M.Vcomponents.all;
325 
 
326 
entity input_phi2_register_1 is
327 
 
328 
   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
329 
         output : out std_logic_vector (0 to 15));
330 
 
331 
end input_phi2_register_1;
332 
 
333 
architecture SYN_behavior_1 of input_phi2_register_1 is
334 
 
335 
   component DFA
336 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
337 
   end component;
338 
 
339 
   component DFA2
340 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
341 
   end component;
342 
 
343 
   component BU2
344 
      port( A : in std_logic;  Q : out std_logic);
345 
   end component;
346 
 
347 
   signal n82, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125
348 
      , n126, n127, n128, n129, n130 : std_logic;
349 
 
350 
begin
351 
 
352 
   output_reg_15 : DFA port map( C => phi2, D => input(0), Q => output(0), QN
353 
                           => n115, RN => n82);
354 
   output_reg_14 : DFA port map( C => phi2, D => input(1), Q => output(1), QN
355 
                           => n116, RN => n82);
356 
   output_reg_13 : DFA2 port map( C => phi2, D => input(2), Q => output(2), QN
357 
                           => n117, RN => reset);
358 
   output_reg_12 : DFA2 port map( C => phi2, D => input(3), Q => output(3), QN
359 
                           => n118, RN => reset);
360 
   output_reg_11 : DFA2 port map( C => phi2, D => input(4), Q => output(4), QN
361 
                           => n119, RN => reset);
362 
   output_reg_10 : DFA2 port map( C => phi2, D => input(5), Q => output(5), QN
363 
                           => n120, RN => reset);
364 
   output_reg_9 : DFA2 port map( C => phi2, D => input(6), Q => output(6), QN
365 
                           => n121, RN => reset);
366 
   output_reg_8 : DFA2 port map( C => phi2, D => input(7), Q => output(7), QN
367 
                           => n122, RN => reset);
368 
   output_reg_7 : DFA2 port map( C => phi2, D => input(8), Q => output(8), QN
369 
                           => n123, RN => reset);
370 
   output_reg_6 : DFA port map( C => phi2, D => input(9), Q => output(9), QN =>
371 
                           n124, RN => n82);
372 
   output_reg_5 : DFA2 port map( C => phi2, D => input(10), Q => output(10), QN
373 
                           => n125, RN => reset);
374 
   output_reg_4 : DFA2 port map( C => phi2, D => input(11), Q => output(11), QN
375 
                           => n126, RN => reset);
376 
   output_reg_3 : DFA2 port map( C => phi2, D => input(12), Q => output(12), QN
377 
                           => n127, RN => reset);
378 
   output_reg_2 : DFA port map( C => phi2, D => input(13), Q => output(13), QN
379 
                           => n128, RN => n82);
380 
   output_reg_1 : DFA2 port map( C => phi2, D => input(14), Q => output(14), QN
381 
                           => n129, RN => reset);
382 
   output_reg_0 : DFA2 port map( C => phi2, D => input(15), Q => output(15), QN
383 
                           => n130, RN => reset);
384 
   U48 : BU2 port map( A => reset, Q => n82);
385 
 
386 
end SYN_behavior_1;
387 
 
388 
library IEEE;
389 
library csx_HRDLIB;
390 
library csx_IOLIB_3M;
391 
 
392 
use IEEE.std_logic_1164.all;
393 
use IEEE.std_logic_arith.all;
394 
use csx_HRDLIB.Vcomponents.all;
395 
use csx_IOLIB_3M.Vcomponents.all;
396 
 
397 
entity input_phi2_register_2 is
398 
 
399 
   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
400 
         output : out std_logic_vector (0 to 15));
401 
 
402 
end input_phi2_register_2;
403 
 
404 
architecture SYN_behavior_2 of input_phi2_register_2 is
405 
 
406 
   component DFA2
407 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
408 
   end component;
409 
 
410 
   component DFA
411 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
412 
   end component;
413 
 
414 
   signal n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
415 
      n118, n119, n120, n121, n122 : std_logic;
416 
 
417 
begin
418 
 
419 
   output_reg_15 : DFA2 port map( C => phi2, D => input(0), Q => output(0), QN
420 
                           => n107, RN => reset);
421 
   output_reg_14 : DFA2 port map( C => phi2, D => input(1), Q => output(1), QN
422 
                           => n108, RN => reset);
423 
   output_reg_13 : DFA2 port map( C => phi2, D => input(2), Q => output(2), QN
424 
                           => n109, RN => reset);
425 
   output_reg_12 : DFA2 port map( C => phi2, D => input(3), Q => output(3), QN
426 
                           => n110, RN => reset);
427 
   output_reg_11 : DFA2 port map( C => phi2, D => input(4), Q => output(4), QN
428 
                           => n111, RN => reset);
429 
   output_reg_10 : DFA2 port map( C => phi2, D => input(5), Q => output(5), QN
430 
                           => n112, RN => reset);
431 
   output_reg_9 : DFA2 port map( C => phi2, D => input(6), Q => output(6), QN
432 
                           => n113, RN => reset);
433 
   output_reg_8 : DFA2 port map( C => phi2, D => input(7), Q => output(7), QN
434 
                           => n114, RN => reset);
435 
   output_reg_7 : DFA2 port map( C => phi2, D => input(8), Q => output(8), QN
436 
                           => n115, RN => reset);
437 
   output_reg_6 : DFA2 port map( C => phi2, D => input(9), Q => output(9), QN
438 
                           => n116, RN => reset);
439 
   output_reg_5 : DFA2 port map( C => phi2, D => input(10), Q => output(10), QN
440 
                           => n117, RN => reset);
441 
   output_reg_4 : DFA port map( C => phi2, D => input(11), Q => output(11), QN
442 
                           => n118, RN => reset);
443 
   output_reg_3 : DFA port map( C => phi2, D => input(12), Q => output(12), QN
444 
                           => n119, RN => reset);
445 
   output_reg_2 : DFA port map( C => phi2, D => input(13), Q => output(13), QN
446 
                           => n120, RN => reset);
447 
   output_reg_1 : DFA port map( C => phi2, D => input(14), Q => output(14), QN
448 
                           => n121, RN => reset);
449 
   output_reg_0 : DFA port map( C => phi2, D => input(15), Q => output(15), QN
450 
                           => n122, RN => reset);
451 
 
452 
end SYN_behavior_2;
453 
 
454 
library IEEE;
455 
library csx_HRDLIB;
456 
library csx_IOLIB_3M;
457 
 
458 
use IEEE.std_logic_1164.all;
459 
use IEEE.std_logic_arith.all;
460 
use csx_HRDLIB.Vcomponents.all;
461 
use csx_IOLIB_3M.Vcomponents.all;
462 
 
463 
entity input_phi2_register_3 is
464 
 
465 
   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
466 
         output : out std_logic_vector (0 to 15));
467 
 
468 
end input_phi2_register_3;
469 
 
470 
architecture SYN_behavior_3 of input_phi2_register_3 is
471 
 
472 
   component IN3
473 
      port( A : in std_logic;  Q : out std_logic);
474 
   end component;
475 
 
476 
   component DFA
477 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
478 
   end component;
479 
 
480 
   component IN1
481 
      port( A : in std_logic;  Q : out std_logic);
482 
   end component;
483 
 
484 
   signal n97, n99, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
485 
      n142, n143, n144, n145, n146, n147 : std_logic;
486 
 
487 
begin
488 
 
489 
   U48 : IN3 port map( A => n97, Q => n99);
490 
   output_reg_15 : DFA port map( C => phi2, D => input(0), Q => output(0), QN
491 
                           => n132, RN => n99);
492 
   output_reg_14 : DFA port map( C => phi2, D => input(1), Q => output(1), QN
493 
                           => n133, RN => n99);
494 
   output_reg_13 : DFA port map( C => phi2, D => input(2), Q => output(2), QN
495 
                           => n134, RN => n99);
496 
   output_reg_12 : DFA port map( C => phi2, D => input(3), Q => output(3), QN
497 
                           => n135, RN => n99);
498 
   output_reg_11 : DFA port map( C => phi2, D => input(4), Q => output(4), QN
499 
                           => n136, RN => n99);
500 
   output_reg_10 : DFA port map( C => phi2, D => input(5), Q => output(5), QN
501 
                           => n137, RN => n99);
502 
   output_reg_9 : DFA port map( C => phi2, D => input(6), Q => output(6), QN =>
503 
                           n138, RN => n99);
504 
   output_reg_8 : DFA port map( C => phi2, D => input(7), Q => output(7), QN =>
505 
                           n139, RN => n99);
506 
   output_reg_7 : DFA port map( C => phi2, D => input(8), Q => output(8), QN =>
507 
                           n140, RN => n99);
508 
   output_reg_6 : DFA port map( C => phi2, D => input(9), Q => output(9), QN =>
509 
                           n141, RN => n99);
510 
   output_reg_5 : DFA port map( C => phi2, D => input(10), Q => output(10), QN
511 
                           => n142, RN => n99);
512 
   output_reg_4 : DFA port map( C => phi2, D => input(11), Q => output(11), QN
513 
                           => n143, RN => n99);
514 
   output_reg_3 : DFA port map( C => phi2, D => input(12), Q => output(12), QN
515 
                           => n144, RN => n99);
516 
   output_reg_2 : DFA port map( C => phi2, D => input(13), Q => output(13), QN
517 
                           => n145, RN => n99);
518 
   output_reg_1 : DFA port map( C => phi2, D => input(14), Q => output(14), QN
519 
                           => n146, RN => n99);
520 
   output_reg_0 : DFA port map( C => phi2, D => input(15), Q => output(15), QN
521 
                           => n147, RN => n99);
522 
   U49 : IN1 port map( A => reset, Q => n97);
523 
 
524 
end SYN_behavior_3;
525 
 
526 
library IEEE;
527 
library csx_HRDLIB;
528 
library csx_IOLIB_3M;
529 
 
530 
use IEEE.std_logic_1164.all;
531 
use IEEE.std_logic_arith.all;
532 
use csx_HRDLIB.Vcomponents.all;
533 
use csx_IOLIB_3M.Vcomponents.all;
534 
 
535 
entity input_phi1_register_0 is
536 
 
537 
   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
538 
         output : out std_logic_vector (0 to 15));
539 
 
540 
end input_phi1_register_0;
541 
 
542 
architecture SYN_behavior_0 of input_phi1_register_0 is
543 
 
544 
   component DFA2
545 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
546 
   end component;
547 
 
548 
   component IN1
549 
      port( A : in std_logic;  Q : out std_logic);
550 
   end component;
551 
 
552 
   component IN3
553 
      port( A : in std_logic;  Q : out std_logic);
554 
   end component;
555 
 
556 
   signal n76, n80, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
557 
      n123, n124, n125, n126, n127, n128 : std_logic;
558 
 
559 
begin
560 
 
561 
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => output(0), QN
562 
                           => n113, RN => n80);
563 
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => output(1), QN
564 
                           => n114, RN => n80);
565 
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => output(2), QN
566 
                           => n115, RN => n80);
567 
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => output(3), QN
568 
                           => n116, RN => n80);
569 
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => output(4), QN
570 
                           => n117, RN => n80);
571 
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => output(5), QN
572 
                           => n118, RN => n80);
573 
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => output(6), QN
574 
                           => n119, RN => n80);
575 
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => output(7), QN
576 
                           => n120, RN => n80);
577 
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => output(8), QN
578 
                           => n121, RN => n80);
579 
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => output(9), QN
580 
                           => n122, RN => n80);
581 
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => output(10), QN
582 
                           => n123, RN => n80);
583 
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => output(11), QN
584 
                           => n124, RN => n80);
585 
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => output(12), QN
586 
                           => n125, RN => n80);
587 
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => output(13), QN
588 
                           => n126, RN => n80);
589 
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => output(14), QN
590 
                           => n127, RN => n80);
591 
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => output(15), QN
592 
                           => n128, RN => n80);
593 
   U48 : IN1 port map( A => reset, Q => n76);
594 
   U49 : IN3 port map( A => n76, Q => n80);
595 
 
596 
end SYN_behavior_0;
597 
 
598 
library IEEE;
599 
library csx_HRDLIB;
600 
library csx_IOLIB_3M;
601 
 
602 
use IEEE.std_logic_1164.all;
603 
use IEEE.std_logic_arith.all;
604 
use csx_HRDLIB.Vcomponents.all;
605 
use csx_IOLIB_3M.Vcomponents.all;
606 
 
607 
entity input_phi1_register_1 is
608 
 
609 
   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
610 
         output : out std_logic_vector (0 to 15));
611 
 
612 
end input_phi1_register_1;
613 
 
614 
architecture SYN_behavior_1 of input_phi1_register_1 is
615 
 
616 
   component DFA2
617 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
618 
   end component;
619 
 
620 
   signal n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
621 
      n118, n119, n120, n121, n122 : std_logic;
622 
 
623 
begin
624 
 
625 
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => output(0), QN
626 
                           => n107, RN => reset);
627 
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => output(1), QN
628 
                           => n108, RN => reset);
629 
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => output(2), QN
630 
                           => n109, RN => reset);
631 
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => output(3), QN
632 
                           => n110, RN => reset);
633 
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => output(4), QN
634 
                           => n111, RN => reset);
635 
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => output(5), QN
636 
                           => n112, RN => reset);
637 
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => output(6), QN
638 
                           => n113, RN => reset);
639 
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => output(7), QN
640 
                           => n114, RN => reset);
641 
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => output(8), QN
642 
                           => n115, RN => reset);
643 
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => output(9), QN
644 
                           => n116, RN => reset);
645 
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => output(10), QN
646 
                           => n117, RN => reset);
647 
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => output(11), QN
648 
                           => n118, RN => reset);
649 
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => output(12), QN
650 
                           => n119, RN => reset);
651 
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => output(13), QN
652 
                           => n120, RN => reset);
653 
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => output(14), QN
654 
                           => n121, RN => reset);
655 
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => output(15), QN
656 
                           => n122, RN => reset);
657 
 
658 
end SYN_behavior_1;
659 
 
660 
library IEEE;
661 
library csx_HRDLIB;
662 
library csx_IOLIB_3M;
663 
 
664 
use IEEE.std_logic_1164.all;
665 
use IEEE.std_logic_arith.all;
666 
use csx_HRDLIB.Vcomponents.all;
667 
use csx_IOLIB_3M.Vcomponents.all;
668 
 
669 
entity input_phi1_register_2 is
670 
 
671 
   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
672 
         output : out std_logic_vector (0 to 15));
673 
 
674 
end input_phi1_register_2;
675 
 
676 
architecture SYN_behavior_2 of input_phi1_register_2 is
677 
 
678 
   component DFA2
679 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
680 
   end component;
681 
 
682 
   component IN1
683 
      port( A : in std_logic;  Q : out std_logic);
684 
   end component;
685 
 
686 
   component IN3
687 
      port( A : in std_logic;  Q : out std_logic);
688 
   end component;
689 
 
690 
   signal n84, n86, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
691 
      n129, n130, n131, n132, n133, n134 : std_logic;
692 
 
693 
begin
694 
 
695 
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => output(0), QN
696 
                           => n119, RN => n86);
697 
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => output(1), QN
698 
                           => n120, RN => n86);
699 
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => output(2), QN
700 
                           => n121, RN => n86);
701 
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => output(3), QN
702 
                           => n122, RN => n86);
703 
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => output(4), QN
704 
                           => n123, RN => n86);
705 
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => output(5), QN
706 
                           => n124, RN => n86);
707 
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => output(6), QN
708 
                           => n125, RN => n86);
709 
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => output(7), QN
710 
                           => n126, RN => n86);
711 
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => output(8), QN
712 
                           => n127, RN => n86);
713 
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => output(9), QN
714 
                           => n128, RN => n86);
715 
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => output(10), QN
716 
                           => n129, RN => n86);
717 
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => output(11), QN
718 
                           => n130, RN => n86);
719 
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => output(12), QN
720 
                           => n131, RN => n86);
721 
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => output(13), QN
722 
                           => n132, RN => n86);
723 
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => output(14), QN
724 
                           => n133, RN => n86);
725 
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => output(15), QN
726 
                           => n134, RN => n86);
727 
   U48 : IN1 port map( A => reset, Q => n84);
728 
   U49 : IN3 port map( A => n84, Q => n86);
729 
 
730 
end SYN_behavior_2;
731 
 
732 
library IEEE;
733 
library csx_HRDLIB;
734 
library csx_IOLIB_3M;
735 
 
736 
use IEEE.std_logic_1164.all;
737 
use IEEE.std_logic_arith.all;
738 
use csx_HRDLIB.Vcomponents.all;
739 
use csx_IOLIB_3M.Vcomponents.all;
740 
 
741 
entity input_phi1_register_3 is
742 
 
743 
   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
744 
         output : out std_logic_vector (0 to 15));
745 
 
746 
end input_phi1_register_3;
747 
 
748 
architecture SYN_behavior_3 of input_phi1_register_3 is
749 
 
750 
   component IN3
751 
      port( A : in std_logic;  Q : out std_logic);
752 
   end component;
753 
 
754 
   component IN1
755 
      port( A : in std_logic;  Q : out std_logic);
756 
   end component;
757 
 
758 
   component DFA2
759 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
760 
   end component;
761 
 
762 
   component IN4
763 
      port( A : in std_logic;  Q : out std_logic);
764 
   end component;
765 
 
766 
   signal n88, n90, n92, n98, n100, n102, n104, n106, n111, n115, n119, n123,
767 
      n127, n131, n135, n139, n157, n159, n209, n210, n211, n212, n213, n214,
768 
      n215, n216, n217, n218, n219, n220, n221, n222, n223, n224 : std_logic;
769 
 
770 
begin
771 
 
772 
   U48 : IN3 port map( A => n92, Q => output(9));
773 
   U49 : IN3 port map( A => n98, Q => output(5));
774 
   U50 : IN3 port map( A => n100, Q => output(15));
775 
   U51 : IN3 port map( A => n102, Q => output(1));
776 
   U52 : IN3 port map( A => n104, Q => output(2));
777 
   U53 : IN3 port map( A => n106, Q => output(12));
778 
   U54 : IN1 port map( A => reset, Q => n88);
779 
   U55 : IN3 port map( A => n88, Q => n90);
780 
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => n209, QN => n92
781 
                           , RN => n90);
782 
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => n210, QN =>
783 
                           n98, RN => n90);
784 
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => n211, QN =>
785 
                           n100, RN => n90);
786 
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => n212, QN =>
787 
                           n102, RN => n90);
788 
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => n213, QN =>
789 
                           n104, RN => n90);
790 
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => n214, QN =>
791 
                           n106, RN => n90);
792 
   U56 : IN4 port map( A => n111, Q => output(0));
793 
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => n215, QN =>
794 
                           n111, RN => n90);
795 
   U57 : IN4 port map( A => n115, Q => output(3));
796 
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => n216, QN =>
797 
                           n115, RN => n90);
798 
   U58 : IN4 port map( A => n119, Q => output(11));
799 
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => n217, QN =>
800 
                           n119, RN => n90);
801 
   U59 : IN4 port map( A => n123, Q => output(10));
802 
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => n218, QN =>
803 
                           n123, RN => n90);
804 
   U60 : IN4 port map( A => n127, Q => output(13));
805 
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => n219, QN =>
806 
                           n127, RN => n90);
807 
   U61 : IN4 port map( A => n131, Q => output(6));
808 
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => n220, QN =>
809 
                           n131, RN => n90);
810 
   U62 : IN4 port map( A => n135, Q => output(4));
811 
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => n221, QN =>
812 
                           n135, RN => n90);
813 
   U63 : IN4 port map( A => n139, Q => output(8));
814 
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => n222, QN =>
815 
                           n139, RN => n90);
816 
   U64 : IN4 port map( A => n157, Q => output(14));
817 
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => n223, QN =>
818 
                           n157, RN => n90);
819 
   U65 : IN4 port map( A => n159, Q => output(7));
820 
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => n224, QN =>
821 
                           n159, RN => n90);
822 
 
823 
end SYN_behavior_3;
824 
 
825 
library IEEE;
826 
library csx_HRDLIB;
827 
library csx_IOLIB_3M;
828 
 
829 
use IEEE.std_logic_1164.all;
830 
use IEEE.std_logic_arith.all;
831 
use csx_HRDLIB.Vcomponents.all;
832 
use csx_IOLIB_3M.Vcomponents.all;
833 
 
834 
entity input_wait is
835 
 
836 
   port( phi1, phi2, reset : in std_logic;  input : in std_logic_vector (0 to
837 
         15);  output : out std_logic_vector (0 to 15));
838 
 
839 
end input_wait;
840 
 
841 
architecture SYN_structural_architecture of input_wait is
842 
 
843 
   component input_phi2_register_0
844 
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
845 
            output : out std_logic_vector (0 to 15));
846 
   end component;
847 
 
848 
   component input_phi2_register_1
849 
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
850 
            output : out std_logic_vector (0 to 15));
851 
   end component;
852 
 
853 
   component input_phi2_register_2
854 
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
855 
            output : out std_logic_vector (0 to 15));
856 
   end component;
857 
 
858 
   component input_phi2_register_3
859 
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
860 
            output : out std_logic_vector (0 to 15));
861 
   end component;
862 
 
863 
   component input_phi1_register_0
864 
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
865 
            output : out std_logic_vector (0 to 15));
866 
   end component;
867 
 
868 
   component input_phi1_register_1
869 
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
870 
            output : out std_logic_vector (0 to 15));
871 
   end component;
872 
 
873 
   component input_phi1_register_2
874 
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
875 
            output : out std_logic_vector (0 to 15));
876 
   end component;
877 
 
878 
   component input_phi1_register_3
879 
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
880 
            output : out std_logic_vector (0 to 15));
881 
   end component;
882 
 
883 
   signal btw1and2_12, btw1and2_7, btw6and7_11, btw3and4_9, btw4and5_1,
884 
      btw5and6_14, btw5and6_4, btw6and7_9, btw7and8_2, btw2and3_10, btw2and3_3,
885 
      btw7and8_12, btw3and4_7, btw3and4_0, btw4and5_14, btw4and5_8, btw6and7_0,
886 
      btw6and7_7, btw3and4_11, btw4and5_13, btw1and2_15, btw1and2_9, btw2and3_4
887 
      , btw7and8_15, btw5and6_3, btw7and8_5, btw1and2_14, btw1and2_0,
888 
      btw4and5_6, btw5and6_13, btw1and2_13, btw1and2_8, btw7and8_4, btw1and2_6,
889 
      btw1and2_1, btw2and3_11, btw2and3_5, btw7and8_14, btw3and4_10, btw3and4_6
890 
      , btw4and5_12, btw6and7_6, btw4and5_7, btw5and6_12, btw3and4_8,
891 
      btw5and6_2, btw5and6_5, btw6and7_8, btw4and5_0, btw5and6_15, btw3and4_1,
892 
      btw6and7_10, btw4and5_15, btw6and7_1, btw4and5_9, btw2and3_2, btw7and8_13
893 
      , btw7and8_3, btw1and2_11, btw1and2_4, btw2and3_9, btw6and7_12,
894 
      btw7and8_8, btw4and5_2, btw5and6_7, btw1and2_10, btw1and2_5, btw1and2_3,
895 
      btw2and3_14, btw2and3_0, btw7and8_11, btw7and8_1, btw3and4_15,
896 
      btw2and3_13, btw3and4_4, btw3and4_3, btw6and7_3, btw5and6_9, btw6and7_4,
897 
      btw2and3_7, btw3and4_12, btw4and5_10, btw4and5_5, btw5and6_10, btw5and6_0
898 
      , btw7and8_6, btw1and2_2, btw2and3_12, btw2and3_6, btw6and7_15,
899 
      btw7and8_7, btw3and4_13, btw3and4_5, btw4and5_11, btw5and6_8, btw6and7_5,
900 
      btw6and7_14, btw4and5_4, btw5and6_11, btw5and6_6, btw5and6_1, btw2and3_8,
901 
      btw4and5_3, btw2and3_15, btw3and4_14, btw3and4_2, btw6and7_13, btw6and7_2
902 
      , btw7and8_9, btw2and3_1, btw7and8_10, btw7and8_0 : std_logic;
903 
 
904 
begin
905 
 
906 
   Input1 : input_phi2_register_3 port map( reset => reset, phi2 => phi2,
907 
                           input(0) => input(0), input(1) => input(1), input(2)
908 
                           => input(2), input(3) => input(3), input(4) =>
909 
                           input(4), input(5) => input(5), input(6) => input(6)
910 
                           , input(7) => input(7), input(8) => input(8),
911 
                           input(9) => input(9), input(10) => input(10),
912 
                           input(11) => input(11), input(12) => input(12),
913 
                           input(13) => input(13), input(14) => input(14),
914 
                           input(15) => input(15), output(0) => btw1and2_15,
915 
                           output(1) => btw1and2_14, output(2) => btw1and2_13,
916 
                           output(3) => btw1and2_12, output(4) => btw1and2_11,
917 
                           output(5) => btw1and2_10, output(6) => btw1and2_9,
918 
                           output(7) => btw1and2_8, output(8) => btw1and2_7,
919 
                           output(9) => btw1and2_6, output(10) => btw1and2_5,
920 
                           output(11) => btw1and2_4, output(12) => btw1and2_3,
921 
                           output(13) => btw1and2_2, output(14) => btw1and2_1,
922 
                           output(15) => btw1and2_0);
923 
   Input8 : input_phi1_register_3 port map( reset => reset, phi1 => phi1,
924 
                           input(0) => btw7and8_15, input(1) => btw7and8_14,
925 
                           input(2) => btw7and8_13, input(3) => btw7and8_12,
926 
                           input(4) => btw7and8_11, input(5) => btw7and8_10,
927 
                           input(6) => btw7and8_9, input(7) => btw7and8_8,
928 
                           input(8) => btw7and8_7, input(9) => btw7and8_6,
929 
                           input(10) => btw7and8_5, input(11) => btw7and8_4,
930 
                           input(12) => btw7and8_3, input(13) => btw7and8_2,
931 
                           input(14) => btw7and8_1, input(15) => btw7and8_0,
932 
                           output(0) => output(0), output(1) => output(1),
933 
                           output(2) => output(2), output(3) => output(3),
934 
                           output(4) => output(4), output(5) => output(5),
935 
                           output(6) => output(6), output(7) => output(7),
936 
                           output(8) => output(8), output(9) => output(9),
937 
                           output(10) => output(10), output(11) => output(11),
938 
                           output(12) => output(12), output(13) => output(13),
939 
                           output(14) => output(14), output(15) => output(15));
940 
   Input2 : input_phi1_register_2 port map( reset => reset, phi1 => phi1,
941 
                           input(0) => btw1and2_15, input(1) => btw1and2_14,
942 
                           input(2) => btw1and2_13, input(3) => btw1and2_12,
943 
                           input(4) => btw1and2_11, input(5) => btw1and2_10,
944 
                           input(6) => btw1and2_9, input(7) => btw1and2_8,
945 
                           input(8) => btw1and2_7, input(9) => btw1and2_6,
946 
                           input(10) => btw1and2_5, input(11) => btw1and2_4,
947 
                           input(12) => btw1and2_3, input(13) => btw1and2_2,
948 
                           input(14) => btw1and2_1, input(15) => btw1and2_0,
949 
                           output(0) => btw2and3_15, output(1) => btw2and3_14,
950 
                           output(2) => btw2and3_13, output(3) => btw2and3_12,
951 
                           output(4) => btw2and3_11, output(5) => btw2and3_10,
952 
                           output(6) => btw2and3_9, output(7) => btw2and3_8,
953 
                           output(8) => btw2and3_7, output(9) => btw2and3_6,
954 
                           output(10) => btw2and3_5, output(11) => btw2and3_4,
955 
                           output(12) => btw2and3_3, output(13) => btw2and3_2,
956 
                           output(14) => btw2and3_1, output(15) => btw2and3_0);
957 
   Input6 : input_phi1_register_1 port map( reset => reset, phi1 => phi1,
958 
                           input(0) => btw5and6_15, input(1) => btw5and6_14,
959 
                           input(2) => btw5and6_13, input(3) => btw5and6_12,
960 
                           input(4) => btw5and6_11, input(5) => btw5and6_10,
961 
                           input(6) => btw5and6_9, input(7) => btw5and6_8,
962 
                           input(8) => btw5and6_7, input(9) => btw5and6_6,
963 
                           input(10) => btw5and6_5, input(11) => btw5and6_4,
964 
                           input(12) => btw5and6_3, input(13) => btw5and6_2,
965 
                           input(14) => btw5and6_1, input(15) => btw5and6_0,
966 
                           output(0) => btw6and7_15, output(1) => btw6and7_14,
967 
                           output(2) => btw6and7_13, output(3) => btw6and7_12,
968 
                           output(4) => btw6and7_11, output(5) => btw6and7_10,
969 
                           output(6) => btw6and7_9, output(7) => btw6and7_8,
970 
                           output(8) => btw6and7_7, output(9) => btw6and7_6,
971 
                           output(10) => btw6and7_5, output(11) => btw6and7_4,
972 
                           output(12) => btw6and7_3, output(13) => btw6and7_2,
973 
                           output(14) => btw6and7_1, output(15) => btw6and7_0);
974 
   Input7 : input_phi2_register_2 port map( reset => reset, phi2 => phi2,
975 
                           input(0) => btw6and7_15, input(1) => btw6and7_14,
976 
                           input(2) => btw6and7_13, input(3) => btw6and7_12,
977 
                           input(4) => btw6and7_11, input(5) => btw6and7_10,
978 
                           input(6) => btw6and7_9, input(7) => btw6and7_8,
979 
                           input(8) => btw6and7_7, input(9) => btw6and7_6,
980 
                           input(10) => btw6and7_5, input(11) => btw6and7_4,
981 
                           input(12) => btw6and7_3, input(13) => btw6and7_2,
982 
                           input(14) => btw6and7_1, input(15) => btw6and7_0,
983 
                           output(0) => btw7and8_15, output(1) => btw7and8_14,
984 
                           output(2) => btw7and8_13, output(3) => btw7and8_12,
985 
                           output(4) => btw7and8_11, output(5) => btw7and8_10,
986 
                           output(6) => btw7and8_9, output(7) => btw7and8_8,
987 
                           output(8) => btw7and8_7, output(9) => btw7and8_6,
988 
                           output(10) => btw7and8_5, output(11) => btw7and8_4,
989 
                           output(12) => btw7and8_3, output(13) => btw7and8_2,
990 
                           output(14) => btw7and8_1, output(15) => btw7and8_0);
991 
   Input3 : input_phi2_register_1 port map( reset => reset, phi2 => phi2,
992 
                           input(0) => btw2and3_15, input(1) => btw2and3_14,
993 
                           input(2) => btw2and3_13, input(3) => btw2and3_12,
994 
                           input(4) => btw2and3_11, input(5) => btw2and3_10,
995 
                           input(6) => btw2and3_9, input(7) => btw2and3_8,
996 
                           input(8) => btw2and3_7, input(9) => btw2and3_6,
997 
                           input(10) => btw2and3_5, input(11) => btw2and3_4,
998 
                           input(12) => btw2and3_3, input(13) => btw2and3_2,
999 
                           input(14) => btw2and3_1, input(15) => btw2and3_0,
1000 
                           output(0) => btw3and4_15, output(1) => btw3and4_14,
1001 
                           output(2) => btw3and4_13, output(3) => btw3and4_12,
1002 
                           output(4) => btw3and4_11, output(5) => btw3and4_10,
1003 
                           output(6) => btw3and4_9, output(7) => btw3and4_8,
1004 
                           output(8) => btw3and4_7, output(9) => btw3and4_6,
1005 
                           output(10) => btw3and4_5, output(11) => btw3and4_4,
1006 
                           output(12) => btw3and4_3, output(13) => btw3and4_2,
1007 
                           output(14) => btw3and4_1, output(15) => btw3and4_0);
1008 
   Input4 : input_phi1_register_0 port map( reset => reset, phi1 => phi1,
1009 
                           input(0) => btw3and4_15, input(1) => btw3and4_14,
1010 
                           input(2) => btw3and4_13, input(3) => btw3and4_12,
1011 
                           input(4) => btw3and4_11, input(5) => btw3and4_10,
1012 
                           input(6) => btw3and4_9, input(7) => btw3and4_8,
1013 
                           input(8) => btw3and4_7, input(9) => btw3and4_6,
1014 
                           input(10) => btw3and4_5, input(11) => btw3and4_4,
1015 
                           input(12) => btw3and4_3, input(13) => btw3and4_2,
1016 
                           input(14) => btw3and4_1, input(15) => btw3and4_0,
1017 
                           output(0) => btw4and5_15, output(1) => btw4and5_14,
1018 
                           output(2) => btw4and5_13, output(3) => btw4and5_12,
1019 
                           output(4) => btw4and5_11, output(5) => btw4and5_10,
1020 
                           output(6) => btw4and5_9, output(7) => btw4and5_8,
1021 
                           output(8) => btw4and5_7, output(9) => btw4and5_6,
1022 
                           output(10) => btw4and5_5, output(11) => btw4and5_4,
1023 
                           output(12) => btw4and5_3, output(13) => btw4and5_2,
1024 
                           output(14) => btw4and5_1, output(15) => btw4and5_0);
1025 
   Input5 : input_phi2_register_0 port map( reset => reset, phi2 => phi2,
1026 
                           input(0) => btw4and5_15, input(1) => btw4and5_14,
1027 
                           input(2) => btw4and5_13, input(3) => btw4and5_12,
1028 
                           input(4) => btw4and5_11, input(5) => btw4and5_10,
1029 
                           input(6) => btw4and5_9, input(7) => btw4and5_8,
1030 
                           input(8) => btw4and5_7, input(9) => btw4and5_6,
1031 
                           input(10) => btw4and5_5, input(11) => btw4and5_4,
1032 
                           input(12) => btw4and5_3, input(13) => btw4and5_2,
1033 
                           input(14) => btw4and5_1, input(15) => btw4and5_0,
1034 
                           output(0) => btw5and6_15, output(1) => btw5and6_14,
1035 
                           output(2) => btw5and6_13, output(3) => btw5and6_12,
1036 
                           output(4) => btw5and6_11, output(5) => btw5and6_10,
1037 
                           output(6) => btw5and6_9, output(7) => btw5and6_8,
1038 
                           output(8) => btw5and6_7, output(9) => btw5and6_6,
1039 
                           output(10) => btw5and6_5, output(11) => btw5and6_4,
1040 
                           output(12) => btw5and6_3, output(13) => btw5and6_2,
1041 
                           output(14) => btw5and6_1, output(15) => btw5and6_0);
1042 
 
1043 
end SYN_structural_architecture;
1044 
 
1045 
library IEEE;
1046 
library csx_HRDLIB;
1047 
library csx_IOLIB_3M;
1048 
 
1049 
use IEEE.std_logic_1164.all;
1050 
use IEEE.std_logic_arith.all;
1051 
use csx_HRDLIB.Vcomponents.all;
1052 
use csx_IOLIB_3M.Vcomponents.all;
1053 
 
1054 
entity gf_xor_input is
1055 
 
1056 
   port( input_fcs : in std_logic_vector (0 to 31);  output_wip : out
1057 
         std_logic_vector (0 to 31));
1058 
 
1059 
end gf_xor_input;
1060 
 
1061 
architecture SYN_behavior of gf_xor_input is
1062 
 
1063 
   component EO1
1064 
      port( A, B : in std_logic;  Q : out std_logic);
1065 
   end component;
1066 
 
1067 
   signal output_wip_22, output_wip_6, output_wip_28, output_wip_8,
1068 
      output_wip_26, output_wip_27, output_wip_20, output_wip_0, output_wip_7,
1069 
      output_wip_29, net8524, output_wip_11, output_wip_14, net8460,
1070 
      output_wip_4, net6785, output_wip_31, output_wip_23, output_wip_5,
1071 
      output_wip_9 : std_logic;
1072 
 
1073 
begin
1074 
   output_wip <= ( output_wip_31, net6785, output_wip_29, output_wip_28,
1075 
      output_wip_27, output_wip_26, output_wip_31, net6785, output_wip_23,
1076 
      output_wip_22, output_wip_5, output_wip_20, output_wip_31, output_wip_11,
1077 
      net8460, output_wip_9, output_wip_4, output_wip_14, net8460,
1078 
      output_wip_23, output_wip_11, net8524, output_wip_9, output_wip_8,
1079 
      output_wip_7, output_wip_6, output_wip_5, output_wip_4, output_wip_14,
1080 
      net8524, output_wip_9, output_wip_0 );
1081 
 
1082 
   U7 : EO1 port map( A => input_fcs(1), B => input_fcs(2), Q => net8524);
1083 
   U8 : EO1 port map( A => input_fcs(1), B => input_fcs(2), Q => net8460);
1084 
   U9 : EO1 port map( A => input_fcs(1), B => input_fcs(5), Q => net6785);
1085 
   U10 : EO1 port map( A => input_fcs(7), B => input_fcs(3), Q => output_wip_28
1086 
                           );
1087 
   U11 : EO1 port map( A => input_fcs(5), B => input_fcs(9), Q => output_wip_26
1088 
                           );
1089 
   U12 : EO1 port map( A => input_fcs(5), B => input_fcs(3), Q => output_wip_0)
1090 
                           ;
1091 
   U13 : EO1 port map( A => input_fcs(1), B => input_fcs(0), Q => output_wip_11
1092 
                           );
1093 
   U14 : EO1 port map( A => input_fcs(1), B => input_fcs(0), Q => output_wip_14
1094 
                           );
1095 
   U15 : EO1 port map( A => input_fcs(4), B => input_fcs(8), Q => output_wip_27
1096 
                           );
1097 
   U16 : EO1 port map( A => input_fcs(3), B => input_fcs(6), Q => output_wip_20
1098 
                           );
1099 
   U17 : EO1 port map( A => input_fcs(3), B => input_fcs(4), Q => output_wip_8)
1100 
                           ;
1101 
   U18 : EO1 port map( A => input_fcs(1), B => input_fcs(3), Q => output_wip_22
1102 
                           );
1103 
   U19 : EO1 port map( A => input_fcs(1), B => input_fcs(4), Q => output_wip_6)
1104 
                           ;
1105 
   U20 : EO1 port map( A => input_fcs(2), B => input_fcs(6), Q => output_wip_29
1106 
                           );
1107 
   U21 : EO1 port map( A => input_fcs(2), B => input_fcs(3), Q => output_wip_9)
1108 
                           ;
1109 
   U22 : EO1 port map( A => input_fcs(2), B => input_fcs(5), Q => output_wip_5)
1110 
                           ;
1111 
   U23 : EO1 port map( A => input_fcs(0), B => input_fcs(5), Q => output_wip_7)
1112 
                           ;
1113 
   U24 : EO1 port map( A => input_fcs(2), B => input_fcs(0), Q => output_wip_23
1114 
                           );
1115 
   U25 : EO1 port map( A => input_fcs(0), B => input_fcs(4), Q => output_wip_31
1116 
                           );
1117 
   U26 : EO1 port map( A => input_fcs(3), B => input_fcs(0), Q => output_wip_4)
1118 
                           ;
1119 
 
1120 
end SYN_behavior;
1121 
 
1122 
library IEEE;
1123 
library csx_HRDLIB;
1124 
library csx_IOLIB_3M;
1125 
 
1126 
use IEEE.std_logic_1164.all;
1127 
use IEEE.std_logic_arith.all;
1128 
use csx_HRDLIB.Vcomponents.all;
1129 
use csx_IOLIB_3M.Vcomponents.all;
1130 
 
1131 
entity gf_xor_2x is
1132 
 
1133 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1134 
         out std_logic_vector (0 to 31));
1135 
 
1136 
end gf_xor_2x;
1137 
 
1138 
architecture SYN_behavior of gf_xor_2x is
1139 
 
1140 
   component EO1
1141 
      port( A, B : in std_logic;  Q : out std_logic);
1142 
   end component;
1143 
 
1144 
begin
1145 
 
1146 
   U7 : EO1 port map( A => input_wip(16), B => input_fcs(6), Q =>
1147 
                           output_wip(16));
1148 
   U8 : EO1 port map( A => input_wip(14), B => input_fcs(6), Q =>
1149 
                           output_wip(14));
1150 
   U9 : EO1 port map( A => input_wip(21), B => input_fcs(6), Q =>
1151 
                           output_wip(21));
1152 
   U10 : EO1 port map( A => input_wip(29), B => input_fcs(6), Q =>
1153 
                           output_wip(29));
1154 
   U11 : EO1 port map( A => input_wip(10), B => input_fcs(6), Q =>
1155 
                           output_wip(10));
1156 
   U12 : EO1 port map( A => input_wip(24), B => input_fcs(7), Q =>
1157 
                           output_wip(24));
1158 
   U13 : EO1 port map( A => input_wip(1), B => input_fcs(7), Q => output_wip(1)
1159 
                           );
1160 
   U14 : EO1 port map( A => input_wip(9), B => input_fcs(4), Q => output_wip(9)
1161 
                           );
1162 
   U15 : EO1 port map( A => input_wip(12), B => input_fcs(7), Q =>
1163 
                           output_wip(12));
1164 
   U16 : EO1 port map( A => input_wip(13), B => input_fcs(5), Q =>
1165 
                           output_wip(13));
1166 
   U17 : EO1 port map( A => input_wip(17), B => input_fcs(4), Q =>
1167 
                           output_wip(17));
1168 
   U18 : EO1 port map( A => input_wip(18), B => input_fcs(5), Q =>
1169 
                           output_wip(18));
1170 
   U19 : EO1 port map( A => input_wip(23), B => input_fcs(5), Q =>
1171 
                           output_wip(23));
1172 
   U20 : EO1 port map( A => input_wip(25), B => input_fcs(7), Q =>
1173 
                           output_wip(25));
1174 
   U21 : EO1 port map( A => input_wip(30), B => input_fcs(4), Q =>
1175 
                           output_wip(30));
1176 
   U22 : EO1 port map( A => input_wip(0), B => input_fcs(6), Q => output_wip(0)
1177 
                           );
1178 
   U23 : EO1 port map( A => input_wip(31), B => input_fcs(6), Q =>
1179 
                           output_wip(31));
1180 
   U24 : EO1 port map( A => input_wip(6), B => input_fcs(7), Q => output_wip(6)
1181 
                           );
1182 
   U25 : EO1 port map( A => input_wip(11), B => input_fcs(7), Q =>
1183 
                           output_wip(11));
1184 
   U26 : EO1 port map( A => input_wip(8), B => input_fcs(6), Q => output_wip(8)
1185 
                           );
1186 
   U27 : EO1 port map( A => input_wip(3), B => input_fcs(9), Q => output_wip(3)
1187 
                           );
1188 
   U28 : EO1 port map( A => input_wip(4), B => input_fcs(10), Q =>
1189 
                           output_wip(4));
1190 
   U29 : EO1 port map( A => input_wip(5), B => input_fcs(11), Q =>
1191 
                           output_wip(5));
1192 
   U30 : EO1 port map( A => input_wip(20), B => input_fcs(3), Q =>
1193 
                           output_wip(20));
1194 
   U31 : EO1 port map( A => input_wip(7), B => input_fcs(8), Q => output_wip(7)
1195 
                           );
1196 
   U32 : EO1 port map( A => input_wip(2), B => input_fcs(8), Q => output_wip(2)
1197 
                           );
1198 
   U33 : EO1 port map( A => input_wip(26), B => input_fcs(8), Q =>
1199 
                           output_wip(26));
1200 
   U34 : EO1 port map( A => input_wip(28), B => input_fcs(5), Q =>
1201 
                           output_wip(28));
1202 
   U35 : EO1 port map( A => input_wip(15), B => input_fcs(7), Q =>
1203 
                           output_wip(15));
1204 
   U36 : EO1 port map( A => input_wip(27), B => input_fcs(4), Q =>
1205 
                           output_wip(27));
1206 
   U37 : EO1 port map( A => input_wip(22), B => input_fcs(4), Q =>
1207 
                           output_wip(22));
1208 
   U38 : EO1 port map( A => input_wip(19), B => input_fcs(3), Q =>
1209 
                           output_wip(19));
1210 
 
1211 
end SYN_behavior;
1212 
 
1213 
library IEEE;
1214 
library csx_HRDLIB;
1215 
library csx_IOLIB_3M;
1216 
 
1217 
use IEEE.std_logic_1164.all;
1218 
use IEEE.std_logic_arith.all;
1219 
use csx_HRDLIB.Vcomponents.all;
1220 
use csx_IOLIB_3M.Vcomponents.all;
1221 
 
1222 
entity gf_xor_3x is
1223 
 
1224 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1225 
         out std_logic_vector (0 to 31));
1226 
 
1227 
end gf_xor_3x;
1228 
 
1229 
architecture SYN_behavior of gf_xor_3x is
1230 
 
1231 
   component EO1
1232 
      port( A, B : in std_logic;  Q : out std_logic);
1233 
   end component;
1234 
 
1235 
begin
1236 
 
1237 
   U7 : EO1 port map( A => input_wip(25), B => input_fcs(8), Q =>
1238 
                           output_wip(25));
1239 
   U8 : EO1 port map( A => input_wip(12), B => input_fcs(8), Q =>
1240 
                           output_wip(12));
1241 
   U9 : EO1 port map( A => input_wip(13), B => input_fcs(8), Q =>
1242 
                           output_wip(13));
1243 
   U10 : EO1 port map( A => input_wip(18), B => input_fcs(8), Q =>
1244 
                           output_wip(18));
1245 
   U11 : EO1 port map( A => input_wip(24), B => input_fcs(8), Q =>
1246 
                           output_wip(24));
1247 
   U12 : EO1 port map( A => input_wip(23), B => input_fcs(7), Q =>
1248 
                           output_wip(23));
1249 
   U13 : EO1 port map( A => input_wip(27), B => input_fcs(7), Q =>
1250 
                           output_wip(27));
1251 
   U14 : EO1 port map( A => input_wip(16), B => input_fcs(7), Q =>
1252 
                           output_wip(16));
1253 
   U15 : EO1 port map( A => input_wip(17), B => input_fcs(7), Q =>
1254 
                           output_wip(17));
1255 
   U16 : EO1 port map( A => input_wip(29), B => input_fcs(7), Q =>
1256 
                           output_wip(29));
1257 
   U17 : EO1 port map( A => input_wip(22), B => input_fcs(6), Q =>
1258 
                           output_wip(22));
1259 
   U18 : EO1 port map( A => input_wip(28), B => input_fcs(6), Q =>
1260 
                           output_wip(28));
1261 
   U19 : EO1 port map( A => input_wip(19), B => input_fcs(6), Q =>
1262 
                           output_wip(19));
1263 
   U20 : EO1 port map( A => input_wip(20), B => input_fcs(6), Q =>
1264 
                           output_wip(20));
1265 
   U21 : EO1 port map( A => input_wip(30), B => input_fcs(6), Q =>
1266 
                           output_wip(30));
1267 
   U22 : EO1 port map( A => input_wip(7), B => input_fcs(13), Q =>
1268 
                           output_wip(7));
1269 
   U23 : EO1 port map( A => input_wip(11), B => input_fcs(11), Q =>
1270 
                           output_wip(11));
1271 
   U24 : EO1 port map( A => input_fcs(11), B => input_wip(4), Q =>
1272 
                           output_wip(4));
1273 
   U25 : EO1 port map( A => input_wip(6), B => input_fcs(12), Q =>
1274 
                           output_wip(6));
1275 
   U26 : EO1 port map( A => input_fcs(12), B => input_wip(5), Q =>
1276 
                           output_wip(5));
1277 
   U27 : EO1 port map( A => input_wip(21), B => input_fcs(10), Q =>
1278 
                           output_wip(21));
1279 
   U28 : EO1 port map( A => input_wip(15), B => input_fcs(10), Q =>
1280 
                           output_wip(15));
1281 
   U29 : EO1 port map( A => input_wip(10), B => input_fcs(10), Q =>
1282 
                           output_wip(10));
1283 
   U30 : EO1 port map( A => input_fcs(10), B => input_wip(3), Q =>
1284 
                           output_wip(3));
1285 
   U31 : EO1 port map( A => input_wip(31), B => input_fcs(9), Q =>
1286 
                           output_wip(31));
1287 
   U32 : EO1 port map( A => input_wip(14), B => input_fcs(9), Q =>
1288 
                           output_wip(14));
1289 
   U33 : EO1 port map( A => input_wip(8), B => input_fcs(9), Q => output_wip(8)
1290 
                           );
1291 
   U34 : EO1 port map( A => input_fcs(9), B => input_wip(2), Q => output_wip(2)
1292 
                           );
1293 
   U35 : EO1 port map( A => input_wip(26), B => input_fcs(9), Q =>
1294 
                           output_wip(26));
1295 
   U36 : EO1 port map( A => input_fcs(8), B => input_wip(1), Q => output_wip(1)
1296 
                           );
1297 
   U37 : EO1 port map( A => input_fcs(7), B => input_wip(0), Q => output_wip(0)
1298 
                           );
1299 
   U38 : EO1 port map( A => input_fcs(6), B => input_wip(9), Q => output_wip(9)
1300 
                           );
1301 
 
1302 
end SYN_behavior;
1303 
 
1304 
library IEEE;
1305 
library csx_HRDLIB;
1306 
library csx_IOLIB_3M;
1307 
 
1308 
use IEEE.std_logic_1164.all;
1309 
use IEEE.std_logic_arith.all;
1310 
use csx_HRDLIB.Vcomponents.all;
1311 
use csx_IOLIB_3M.Vcomponents.all;
1312 
 
1313 
entity gf_xor_4x is
1314 
 
1315 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1316 
         out std_logic_vector (0 to 31));
1317 
 
1318 
end gf_xor_4x;
1319 
 
1320 
architecture SYN_behavior of gf_xor_4x is
1321 
 
1322 
   component EO1
1323 
      port( A, B : in std_logic;  Q : out std_logic);
1324 
   end component;
1325 
 
1326 
begin
1327 
 
1328 
   U7 : EO1 port map( A => input_wip(26), B => input_fcs(10), Q =>
1329 
                           output_wip(26));
1330 
   U8 : EO1 port map( A => input_wip(0), B => input_fcs(10), Q => output_wip(0)
1331 
                           );
1332 
   U9 : EO1 port map( A => input_wip(1), B => input_fcs(11), Q => output_wip(1)
1333 
                           );
1334 
   U10 : EO1 port map( A => input_wip(7), B => input_fcs(14), Q =>
1335 
                           output_wip(7));
1336 
   U11 : EO1 port map( A => input_wip(12), B => input_fcs(12), Q =>
1337 
                           output_wip(12));
1338 
   U12 : EO1 port map( A => input_wip(14), B => input_fcs(10), Q =>
1339 
                           output_wip(14));
1340 
   U13 : EO1 port map( A => input_wip(16), B => input_fcs(8), Q =>
1341 
                           output_wip(16));
1342 
   U14 : EO1 port map( A => input_wip(18), B => input_fcs(9), Q =>
1343 
                           output_wip(18));
1344 
   U15 : EO1 port map( A => input_wip(19), B => input_fcs(9), Q =>
1345 
                           output_wip(19));
1346 
   U16 : EO1 port map( A => input_wip(25), B => input_fcs(9), Q =>
1347 
                           output_wip(25));
1348 
   U17 : EO1 port map( A => input_wip(8), B => input_fcs(14), Q =>
1349 
                           output_wip(8));
1350 
   U18 : EO1 port map( A => input_wip(13), B => input_fcs(9), Q =>
1351 
                           output_wip(13));
1352 
   U19 : EO1 port map( A => input_wip(15), B => input_fcs(11), Q =>
1353 
                           output_wip(15));
1354 
   U20 : EO1 port map( A => input_wip(20), B => input_fcs(11), Q =>
1355 
                           output_wip(20));
1356 
   U21 : EO1 port map( A => input_wip(21), B => input_fcs(12), Q =>
1357 
                           output_wip(21));
1358 
   U22 : EO1 port map( A => input_wip(22), B => input_fcs(10), Q =>
1359 
                           output_wip(22));
1360 
   U23 : EO1 port map( A => input_wip(24), B => input_fcs(10), Q =>
1361 
                           output_wip(24));
1362 
   U24 : EO1 port map( A => input_wip(27), B => input_fcs(9), Q =>
1363 
                           output_wip(27));
1364 
   U25 : EO1 port map( A => input_wip(29), B => input_fcs(8), Q =>
1365 
                           output_wip(29));
1366 
   U26 : EO1 port map( A => input_wip(30), B => input_fcs(8), Q =>
1367 
                           output_wip(30));
1368 
   U27 : EO1 port map( A => input_wip(28), B => input_fcs(7), Q =>
1369 
                           output_wip(28));
1370 
   U28 : EO1 port map( A => input_wip(10), B => input_fcs(26), Q =>
1371 
                           output_wip(10));
1372 
   U29 : EO1 port map( A => input_wip(11), B => input_fcs(27), Q =>
1373 
                           output_wip(11));
1374 
   U30 : EO1 port map( A => input_wip(6), B => input_fcs(13), Q =>
1375 
                           output_wip(6));
1376 
   U31 : EO1 port map( A => input_wip(3), B => input_fcs(13), Q =>
1377 
                           output_wip(3));
1378 
   U32 : EO1 port map( A => input_wip(2), B => input_fcs(12), Q =>
1379 
                           output_wip(2));
1380 
   U33 : EO1 port map( A => input_wip(4), B => input_fcs(14), Q =>
1381 
                           output_wip(4));
1382 
   U34 : EO1 port map( A => input_wip(31), B => input_fcs(15), Q =>
1383 
                           output_wip(31));
1384 
   U35 : EO1 port map( A => input_wip(9), B => input_fcs(15), Q =>
1385 
                           output_wip(9));
1386 
   U36 : EO1 port map( A => input_wip(5), B => input_fcs(15), Q =>
1387 
                           output_wip(5));
1388 
   U37 : EO1 port map( A => input_wip(23), B => input_fcs(11), Q =>
1389 
                           output_wip(23));
1390 
   U38 : EO1 port map( A => input_wip(17), B => input_fcs(8), Q =>
1391 
                           output_wip(17));
1392 
 
1393 
end SYN_behavior;
1394 
 
1395 
library IEEE;
1396 
library csx_HRDLIB;
1397 
library csx_IOLIB_3M;
1398 
 
1399 
use IEEE.std_logic_1164.all;
1400 
use IEEE.std_logic_arith.all;
1401 
use csx_HRDLIB.Vcomponents.all;
1402 
use csx_IOLIB_3M.Vcomponents.all;
1403 
 
1404 
entity gf_xor_5x is
1405 
 
1406 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1407 
         out std_logic_vector (0 to 31));
1408 
 
1409 
end gf_xor_5x;
1410 
 
1411 
architecture SYN_behavior of gf_xor_5x is
1412 
 
1413 
   component EO1
1414 
      port( A, B : in std_logic;  Q : out std_logic);
1415 
   end component;
1416 
 
1417 
   signal output_wip_5, output_wip_22, output_wip_30, output_wip_17,
1418 
      output_wip_10, output_wip_2, output_wip_25, output_wip_19, output_wip_11,
1419 
      output_wip_18, output_wip_3, output_wip_24, output_wip_4, output_wip_23,
1420 
      output_wip_31, output_wip_16, output_wip_6, output_wip_14, output_wip_28,
1421 
      output_wip_8, output_wip_13, output_wip_26, output_wip_1, output_wip_12,
1422 
      output_wip_9, output_wip_27, output_wip_7, output_wip_29, output_wip_15 :
1423 
      std_logic;
1424 
 
1425 
begin
1426 
   output_wip <= ( output_wip_31, output_wip_30, output_wip_29, output_wip_28,
1427 
      output_wip_27, output_wip_26, output_wip_25, output_wip_24, output_wip_23
1428 
      , output_wip_22, input_wip(10), input_wip(11), output_wip_19,
1429 
      output_wip_18, output_wip_17, output_wip_16, output_wip_15, output_wip_14
1430 
      , output_wip_13, output_wip_12, output_wip_11, output_wip_10,
1431 
      output_wip_9, output_wip_8, output_wip_7, output_wip_6, output_wip_5,
1432 
      output_wip_4, output_wip_3, output_wip_2, output_wip_1, input_wip(31) );
1433 
 
1434 
   U7 : EO1 port map( A => input_wip(28), B => input_fcs(8), Q => output_wip_3)
1435 
                           ;
1436 
   U8 : EO1 port map( A => input_wip(0), B => input_fcs(16), Q => output_wip_31
1437 
                           );
1438 
   U9 : EO1 port map( A => input_wip(1), B => input_fcs(17), Q => output_wip_30
1439 
                           );
1440 
   U10 : EO1 port map( A => input_wip(2), B => input_fcs(18), Q =>
1441 
                           output_wip_29);
1442 
   U11 : EO1 port map( A => input_wip(3), B => input_fcs(19), Q =>
1443 
                           output_wip_28);
1444 
   U12 : EO1 port map( A => input_wip(4), B => input_fcs(20), Q =>
1445 
                           output_wip_27);
1446 
   U13 : EO1 port map( A => input_wip(5), B => input_fcs(21), Q =>
1447 
                           output_wip_26);
1448 
   U14 : EO1 port map( A => input_wip(6), B => input_fcs(22), Q =>
1449 
                           output_wip_25);
1450 
   U15 : EO1 port map( A => input_wip(7), B => input_fcs(23), Q =>
1451 
                           output_wip_24);
1452 
   U16 : EO1 port map( A => input_wip(9), B => input_fcs(25), Q =>
1453 
                           output_wip_22);
1454 
   U17 : EO1 port map( A => input_wip(12), B => input_fcs(28), Q =>
1455 
                           output_wip_19);
1456 
   U18 : EO1 port map( A => input_wip(14), B => input_fcs(14), Q =>
1457 
                           output_wip_17);
1458 
   U19 : EO1 port map( A => input_wip(15), B => input_fcs(15), Q =>
1459 
                           output_wip_16);
1460 
   U20 : EO1 port map( A => input_fcs(15), B => input_wip(8), Q =>
1461 
                           output_wip_23);
1462 
   U21 : EO1 port map( A => input_wip(21), B => input_fcs(13), Q =>
1463 
                           output_wip_10);
1464 
   U22 : EO1 port map( A => input_fcs(13), B => input_wip(13), Q =>
1465 
                           output_wip_18);
1466 
   U23 : EO1 port map( A => input_wip(30), B => input_fcs(9), Q => output_wip_1
1467 
                           );
1468 
   U24 : EO1 port map( A => input_fcs(9), B => input_wip(17), Q =>
1469 
                           output_wip_14);
1470 
   U25 : EO1 port map( A => input_wip(29), B => input_fcs(9), Q => output_wip_2
1471 
                           );
1472 
   U26 : EO1 port map( A => input_fcs(12), B => input_wip(20), Q =>
1473 
                           output_wip_11);
1474 
   U27 : EO1 port map( A => input_wip(24), B => input_fcs(12), Q =>
1475 
                           output_wip_7);
1476 
   U28 : EO1 port map( A => input_wip(23), B => input_fcs(12), Q =>
1477 
                           output_wip_8);
1478 
   U29 : EO1 port map( A => input_wip(27), B => input_fcs(11), Q =>
1479 
                           output_wip_4);
1480 
   U30 : EO1 port map( A => input_wip(26), B => input_fcs(11), Q =>
1481 
                           output_wip_5);
1482 
   U31 : EO1 port map( A => input_fcs(11), B => input_wip(22), Q =>
1483 
                           output_wip_9);
1484 
   U32 : EO1 port map( A => input_wip(19), B => input_fcs(10), Q =>
1485 
                           output_wip_12);
1486 
   U33 : EO1 port map( A => input_wip(18), B => input_fcs(10), Q =>
1487 
                           output_wip_13);
1488 
   U34 : EO1 port map( A => input_fcs(10), B => input_wip(16), Q =>
1489 
                           output_wip_15);
1490 
   U35 : EO1 port map( A => input_wip(25), B => input_fcs(10), Q =>
1491 
                           output_wip_6);
1492 
 
1493 
end SYN_behavior;
1494 
 
1495 
library IEEE;
1496 
library csx_HRDLIB;
1497 
library csx_IOLIB_3M;
1498 
 
1499 
use IEEE.std_logic_1164.all;
1500 
use IEEE.std_logic_arith.all;
1501 
use csx_HRDLIB.Vcomponents.all;
1502 
use csx_IOLIB_3M.Vcomponents.all;
1503 
 
1504 
entity gf_xor_6x is
1505 
 
1506 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1507 
         out std_logic_vector (0 to 31));
1508 
 
1509 
end gf_xor_6x;
1510 
 
1511 
architecture SYN_behavior of gf_xor_6x is
1512 
 
1513 
   component EO1
1514 
      port( A, B : in std_logic;  Q : out std_logic);
1515 
   end component;
1516 
 
1517 
   signal output_wip_5, output_wip_17, output_wip_10, output_wip_2,
1518 
      output_wip_11, output_wip_18, output_wip_3, output_wip_4, output_wip_23,
1519 
      output_wip_6, output_wip_16, output_wip_8, output_wip_14, output_wip_13,
1520 
      output_wip_1, output_wip_12, output_wip_9, output_wip_7, output_wip_15 :
1521 
      std_logic;
1522 
 
1523 
begin
1524 
   output_wip <= ( input_wip(0), input_wip(1), input_wip(2), input_wip(3),
1525 
      input_wip(4), input_wip(5), input_wip(6), input_wip(7), output_wip_23,
1526 
      input_wip(9), input_wip(10), input_wip(11), input_wip(12), output_wip_18,
1527 
      output_wip_17, output_wip_16, output_wip_15, output_wip_14, output_wip_13
1528 
      , output_wip_12, output_wip_11, output_wip_10, output_wip_9, output_wip_8
1529 
      , output_wip_7, output_wip_6, output_wip_5, output_wip_4, output_wip_3,
1530 
      output_wip_2, output_wip_1, input_wip(31) );
1531 
 
1532 
   U7 : EO1 port map( A => input_wip(27), B => input_fcs(12), Q => output_wip_4
1533 
                           );
1534 
   U8 : EO1 port map( A => input_wip(28), B => input_fcs(12), Q => output_wip_3
1535 
                           );
1536 
   U9 : EO1 port map( A => input_wip(18), B => input_fcs(12), Q =>
1537 
                           output_wip_13);
1538 
   U10 : EO1 port map( A => input_wip(19), B => input_fcs(11), Q =>
1539 
                           output_wip_12);
1540 
   U11 : EO1 port map( A => input_wip(23), B => input_fcs(14), Q =>
1541 
                           output_wip_8);
1542 
   U12 : EO1 port map( A => input_wip(25), B => input_fcs(11), Q =>
1543 
                           output_wip_6);
1544 
   U13 : EO1 port map( A => input_wip(30), B => input_fcs(14), Q =>
1545 
                           output_wip_1);
1546 
   U14 : EO1 port map( A => input_wip(16), B => input_fcs(11), Q =>
1547 
                           output_wip_15);
1548 
   U15 : EO1 port map( A => input_wip(22), B => input_fcs(13), Q =>
1549 
                           output_wip_9);
1550 
   U16 : EO1 port map( A => input_wip(29), B => input_fcs(13), Q =>
1551 
                           output_wip_2);
1552 
   U17 : EO1 port map( A => input_wip(8), B => input_fcs(24), Q =>
1553 
                           output_wip_23);
1554 
   U18 : EO1 port map( A => input_wip(13), B => input_fcs(29), Q =>
1555 
                           output_wip_18);
1556 
   U19 : EO1 port map( A => input_wip(14), B => input_fcs(30), Q =>
1557 
                           output_wip_17);
1558 
   U20 : EO1 port map( A => input_wip(15), B => input_fcs(31), Q =>
1559 
                           output_wip_16);
1560 
   U21 : EO1 port map( A => input_wip(21), B => input_fcs(15), Q =>
1561 
                           output_wip_10);
1562 
   U22 : EO1 port map( A => input_wip(20), B => input_fcs(14), Q =>
1563 
                           output_wip_11);
1564 
   U23 : EO1 port map( A => input_wip(24), B => input_fcs(13), Q =>
1565 
                           output_wip_7);
1566 
   U24 : EO1 port map( A => input_wip(17), B => input_fcs(11), Q =>
1567 
                           output_wip_14);
1568 
   U25 : EO1 port map( A => input_wip(26), B => input_fcs(12), Q =>
1569 
                           output_wip_5);
1570 
 
1571 
end SYN_behavior;
1572 
 
1573 
library IEEE;
1574 
library csx_HRDLIB;
1575 
library csx_IOLIB_3M;
1576 
 
1577 
use IEEE.std_logic_1164.all;
1578 
use IEEE.std_logic_arith.all;
1579 
use csx_HRDLIB.Vcomponents.all;
1580 
use csx_IOLIB_3M.Vcomponents.all;
1581 
 
1582 
entity gf_xor_7x is
1583 
 
1584 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1585 
         out std_logic_vector (0 to 31));
1586 
 
1587 
end gf_xor_7x;
1588 
 
1589 
architecture SYN_behavior of gf_xor_7x is
1590 
 
1591 
   component EO1
1592 
      port( A, B : in std_logic;  Q : out std_logic);
1593 
   end component;
1594 
 
1595 
   signal output_wip_5, output_wip_2, output_wip_11, output_wip_3, output_wip_4
1596 
      , output_wip_6, output_wip_8, output_wip_14, output_wip_13, output_wip_1,
1597 
      output_wip_12, output_wip_9, output_wip_7, output_wip_15 : std_logic;
1598 
 
1599 
begin
1600 
   output_wip <= ( input_wip(0), input_wip(1), input_wip(2), input_wip(3),
1601 
      input_wip(4), input_wip(5), input_wip(6), input_wip(7), input_wip(8),
1602 
      input_wip(9), input_wip(10), input_wip(11), input_wip(12), input_wip(13),
1603 
      input_wip(14), input_wip(15), output_wip_15, output_wip_14, output_wip_13
1604 
      , output_wip_12, output_wip_11, input_wip(21), output_wip_9, output_wip_8
1605 
      , output_wip_7, output_wip_6, output_wip_5, output_wip_4, output_wip_3,
1606 
      output_wip_2, output_wip_1, input_wip(31) );
1607 
 
1608 
   U7 : EO1 port map( A => input_wip(17), B => input_fcs(12), Q =>
1609 
                           output_wip_14);
1610 
   U8 : EO1 port map( A => input_fcs(12), B => input_wip(16), Q =>
1611 
                           output_wip_15);
1612 
   U9 : EO1 port map( A => input_wip(29), B => input_fcs(14), Q => output_wip_2
1613 
                           );
1614 
   U10 : EO1 port map( A => input_wip(26), B => input_fcs(14), Q =>
1615 
                           output_wip_5);
1616 
   U11 : EO1 port map( A => input_fcs(14), B => input_wip(22), Q =>
1617 
                           output_wip_9);
1618 
   U12 : EO1 port map( A => input_wip(30), B => input_fcs(15), Q =>
1619 
                           output_wip_1);
1620 
   U13 : EO1 port map( A => input_fcs(15), B => input_wip(20), Q =>
1621 
                           output_wip_11);
1622 
   U14 : EO1 port map( A => input_wip(24), B => input_fcs(15), Q =>
1623 
                           output_wip_7);
1624 
   U15 : EO1 port map( A => input_wip(23), B => input_fcs(15), Q =>
1625 
                           output_wip_8);
1626 
   U16 : EO1 port map( A => input_wip(19), B => input_fcs(13), Q =>
1627 
                           output_wip_12);
1628 
   U17 : EO1 port map( A => input_fcs(13), B => input_wip(18), Q =>
1629 
                           output_wip_13);
1630 
   U18 : EO1 port map( A => input_wip(28), B => input_fcs(13), Q =>
1631 
                           output_wip_3);
1632 
   U19 : EO1 port map( A => input_wip(27), B => input_fcs(13), Q =>
1633 
                           output_wip_4);
1634 
   U20 : EO1 port map( A => input_wip(25), B => input_fcs(13), Q =>
1635 
                           output_wip_6);
1636 
 
1637 
end SYN_behavior;
1638 
 
1639 
library IEEE;
1640 
library csx_HRDLIB;
1641 
library csx_IOLIB_3M;
1642 
 
1643 
use IEEE.std_logic_1164.all;
1644 
use IEEE.std_logic_arith.all;
1645 
use csx_HRDLIB.Vcomponents.all;
1646 
use csx_IOLIB_3M.Vcomponents.all;
1647 
 
1648 
entity gf_xor_8x is
1649 
 
1650 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1651 
         out std_logic_vector (0 to 31));
1652 
 
1653 
end gf_xor_8x;
1654 
 
1655 
architecture SYN_behavior of gf_xor_8x is
1656 
 
1657 
   component EO1
1658 
      port( A, B : in std_logic;  Q : out std_logic);
1659 
   end component;
1660 
 
1661 
   signal output_wip_5, output_wip_2, output_wip_3, output_wip_4, output_wip_6,
1662 
      output_wip_14, output_wip_13, output_wip_12 : std_logic;
1663 
 
1664 
begin
1665 
   output_wip <= ( input_wip(0), input_wip(1), input_wip(2), input_wip(3),
1666 
      input_wip(4), input_wip(5), input_wip(6), input_wip(7), input_wip(8),
1667 
      input_wip(9), input_wip(10), input_wip(11), input_wip(12), input_wip(13),
1668 
      input_wip(14), input_wip(15), input_wip(16), output_wip_14, output_wip_13
1669 
      , output_wip_12, input_wip(20), input_wip(21), input_wip(22),
1670 
      input_wip(23), input_wip(24), output_wip_6, output_wip_5, output_wip_4,
1671 
      output_wip_3, output_wip_2, input_wip(30), input_wip(31) );
1672 
 
1673 
   U7 : EO1 port map( A => input_wip(18), B => input_fcs(14), Q =>
1674 
                           output_wip_13);
1675 
   U8 : EO1 port map( A => input_wip(19), B => input_fcs(14), Q =>
1676 
                           output_wip_12);
1677 
   U9 : EO1 port map( A => input_wip(28), B => input_fcs(14), Q => output_wip_3
1678 
                           );
1679 
   U10 : EO1 port map( A => input_wip(27), B => input_fcs(15), Q =>
1680 
                           output_wip_4);
1681 
   U11 : EO1 port map( A => input_wip(29), B => input_fcs(15), Q =>
1682 
                           output_wip_2);
1683 
   U12 : EO1 port map( A => input_wip(17), B => input_fcs(13), Q =>
1684 
                           output_wip_14);
1685 
   U13 : EO1 port map( A => input_wip(25), B => input_fcs(14), Q =>
1686 
                           output_wip_6);
1687 
   U14 : EO1 port map( A => input_wip(26), B => input_fcs(15), Q =>
1688 
                           output_wip_5);
1689 
 
1690 
end SYN_behavior;
1691 
 
1692 
library IEEE;
1693 
library csx_HRDLIB;
1694 
library csx_IOLIB_3M;
1695 
 
1696 
use IEEE.std_logic_1164.all;
1697 
use IEEE.std_logic_arith.all;
1698 
use csx_HRDLIB.Vcomponents.all;
1699 
use csx_IOLIB_3M.Vcomponents.all;
1700 
 
1701 
entity gf_xor_9x is
1702 
 
1703 
   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
1704 
         out std_logic_vector (0 to 31));
1705 
 
1706 
end gf_xor_9x;
1707 
 
1708 
architecture SYN_behavior of gf_xor_9x is
1709 
 
1710 
   component EO1
1711 
      port( A, B : in std_logic;  Q : out std_logic);
1712 
   end component;
1713 
 
1714 
   signal output_wip_12 : std_logic;
1715 
 
1716 
begin
1717 
   output_wip <= ( input_wip(0), input_wip(1), input_wip(2), input_wip(3),
1718 
      input_wip(4), input_wip(5), input_wip(6), input_wip(7), input_wip(8),
1719 
      input_wip(9), input_wip(10), input_wip(11), input_wip(12), input_wip(13),
1720 
      input_wip(14), input_wip(15), input_wip(16), input_wip(17), input_wip(18)
1721 
      , output_wip_12, input_wip(20), input_wip(21), input_wip(22),
1722 
      input_wip(23), input_wip(24), input_wip(25), input_wip(26), input_wip(27)
1723 
      , input_wip(28), input_wip(29), input_wip(30), input_wip(31) );
1724 
 
1725 
   U7 : EO1 port map( A => input_wip(19), B => input_fcs(15), Q =>
1726 
                           output_wip_12);
1727 
 
1728 
end SYN_behavior;
1729 
 
1730 
library IEEE;
1731 
library csx_HRDLIB;
1732 
library csx_IOLIB_3M;
1733 
 
1734 
use IEEE.std_logic_1164.all;
1735 
use IEEE.std_logic_arith.all;
1736 
use csx_HRDLIB.Vcomponents.all;
1737 
use csx_IOLIB_3M.Vcomponents.all;
1738 
 
1739 
entity gf_phi1_register_out is
1740 
 
1741 
   port( reset, phi1 : in std_logic;  input_wip : in std_logic_vector (0 to 31)
1742 
         ;  output_final : out std_logic_vector (0 to 31));
1743 
 
1744 
end gf_phi1_register_out;
1745 
 
1746 
architecture SYN_behavior of gf_phi1_register_out is
1747 
 
1748 
   component DFA2
1749 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
1750 
   end component;
1751 
 
1752 
   component BU8
1753 
      port( A : in std_logic;  Q : out std_logic);
1754 
   end component;
1755 
 
1756 
   component IN2
1757 
      port( A : in std_logic;  Q : out std_logic);
1758 
   end component;
1759 
 
1760 
   component DFA
1761 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
1762 
   end component;
1763 
 
1764 
   component IN3
1765 
      port( A : in std_logic;  Q : out std_logic);
1766 
   end component;
1767 
 
1768 
   signal n107, n108, n110, n112, n114, n116, n118, n120, n122, n124, n126,
1769 
      n128, n130, n132, n134, n136, n138, n220, n221, n222, n223, n224, n225,
1770 
      n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
1771 
      n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
1772 
      n250, n251 : std_logic;
1773 
 
1774 
begin
1775 
 
1776 
   output_final_reg_29 : DFA2 port map( C => phi1, D => input_wip(2), Q =>
1777 
                           output_final(2), QN => n220, RN => n107);
1778 
   output_final_reg_27 : DFA2 port map( C => phi1, D => input_wip(4), Q =>
1779 
                           output_final(4), QN => n221, RN => n107);
1780 
   output_final_reg_25 : DFA2 port map( C => phi1, D => input_wip(6), Q =>
1781 
                           output_final(6), QN => n222, RN => n107);
1782 
   output_final_reg_24 : DFA2 port map( C => phi1, D => input_wip(7), Q =>
1783 
                           output_final(7), QN => n223, RN => n107);
1784 
   output_final_reg_23 : DFA2 port map( C => phi1, D => input_wip(8), Q =>
1785 
                           output_final(8), QN => n224, RN => n107);
1786 
   output_final_reg_22 : DFA2 port map( C => phi1, D => input_wip(9), Q =>
1787 
                           output_final(9), QN => n225, RN => n107);
1788 
   output_final_reg_21 : DFA2 port map( C => phi1, D => input_wip(10), Q =>
1789 
                           output_final(10), QN => n226, RN => n107);
1790 
   output_final_reg_20 : DFA2 port map( C => phi1, D => input_wip(11), Q =>
1791 
                           output_final(11), QN => n227, RN => n107);
1792 
   output_final_reg_19 : DFA2 port map( C => phi1, D => input_wip(12), Q =>
1793 
                           output_final(12), QN => n228, RN => n107);
1794 
   output_final_reg_18 : DFA2 port map( C => phi1, D => input_wip(13), Q =>
1795 
                           output_final(13), QN => n229, RN => n107);
1796 
   output_final_reg_17 : DFA2 port map( C => phi1, D => input_wip(14), Q =>
1797 
                           output_final(14), QN => n230, RN => n107);
1798 
   output_final_reg_16 : DFA2 port map( C => phi1, D => input_wip(15), Q =>
1799 
                           output_final(15), QN => n231, RN => n107);
1800 
   U80 : BU8 port map( A => reset, Q => n107);
1801 
   U81 : IN2 port map( A => n108, Q => output_final(25));
1802 
   U82 : IN2 port map( A => n110, Q => output_final(21));
1803 
   U83 : IN2 port map( A => n112, Q => output_final(31));
1804 
   U84 : IN2 port map( A => n114, Q => output_final(17));
1805 
   U85 : IN2 port map( A => n116, Q => output_final(18));
1806 
   U86 : IN2 port map( A => n118, Q => output_final(28));
1807 
   output_final_reg_3 : DFA port map( C => phi1, D => input_wip(28), Q => n232,
1808 
                           QN => n118, RN => n107);
1809 
   output_final_reg_13 : DFA port map( C => phi1, D => input_wip(18), Q => n233
1810 
                           , QN => n116, RN => n107);
1811 
   output_final_reg_14 : DFA port map( C => phi1, D => input_wip(17), Q => n234
1812 
                           , QN => n114, RN => n107);
1813 
   output_final_reg_0 : DFA port map( C => phi1, D => input_wip(31), Q => n235,
1814 
                           QN => n112, RN => n107);
1815 
   output_final_reg_10 : DFA port map( C => phi1, D => input_wip(21), Q => n236
1816 
                           , QN => n110, RN => n107);
1817 
   output_final_reg_6 : DFA port map( C => phi1, D => input_wip(25), Q => n237,
1818 
                           QN => n108, RN => n107);
1819 
   U87 : IN3 port map( A => n120, Q => output_final(16));
1820 
   output_final_reg_15 : DFA2 port map( C => phi1, D => input_wip(16), Q =>
1821 
                           n238, QN => n120, RN => n107);
1822 
   U88 : IN3 port map( A => n122, Q => output_final(19));
1823 
   output_final_reg_12 : DFA2 port map( C => phi1, D => input_wip(19), Q =>
1824 
                           n239, QN => n122, RN => n107);
1825 
   U89 : IN3 port map( A => n124, Q => output_final(27));
1826 
   output_final_reg_4 : DFA2 port map( C => phi1, D => input_wip(27), Q => n240
1827 
                           , QN => n124, RN => n107);
1828 
   U90 : IN3 port map( A => n126, Q => output_final(26));
1829 
   output_final_reg_5 : DFA2 port map( C => phi1, D => input_wip(26), Q => n241
1830 
                           , QN => n126, RN => n107);
1831 
   U91 : IN3 port map( A => n128, Q => output_final(29));
1832 
   output_final_reg_2 : DFA2 port map( C => phi1, D => input_wip(29), Q => n242
1833 
                           , QN => n128, RN => n107);
1834 
   U92 : IN3 port map( A => n130, Q => output_final(22));
1835 
   output_final_reg_9 : DFA2 port map( C => phi1, D => input_wip(22), Q => n243
1836 
                           , QN => n130, RN => n107);
1837 
   U93 : IN3 port map( A => n132, Q => output_final(20));
1838 
   output_final_reg_11 : DFA2 port map( C => phi1, D => input_wip(20), Q =>
1839 
                           n244, QN => n132, RN => n107);
1840 
   U94 : IN3 port map( A => n134, Q => output_final(24));
1841 
   output_final_reg_7 : DFA2 port map( C => phi1, D => input_wip(24), Q => n245
1842 
                           , QN => n134, RN => n107);
1843 
   U95 : IN3 port map( A => n136, Q => output_final(30));
1844 
   output_final_reg_1 : DFA2 port map( C => phi1, D => input_wip(30), Q => n246
1845 
                           , QN => n136, RN => n107);
1846 
   U96 : IN3 port map( A => n138, Q => output_final(23));
1847 
   output_final_reg_8 : DFA2 port map( C => phi1, D => input_wip(23), Q => n247
1848 
                           , QN => n138, RN => n107);
1849 
   output_final_reg_26 : DFA2 port map( C => phi1, D => input_wip(5), Q =>
1850 
                           output_final(5), QN => n248, RN => n107);
1851 
   output_final_reg_30 : DFA2 port map( C => phi1, D => input_wip(1), Q =>
1852 
                           output_final(1), QN => n249, RN => n107);
1853 
   output_final_reg_31 : DFA2 port map( C => phi1, D => input_wip(0), Q =>
1854 
                           output_final(0), QN => n250, RN => n107);
1855 
   output_final_reg_28 : DFA2 port map( C => phi1, D => input_wip(3), Q =>
1856 
                           output_final(3), QN => n251, RN => n107);
1857 
 
1858 
end SYN_behavior;
1859 
 
1860 
library IEEE;
1861 
library csx_HRDLIB;
1862 
library csx_IOLIB_3M;
1863 
 
1864 
use IEEE.std_logic_1164.all;
1865 
use IEEE.std_logic_arith.all;
1866 
use csx_HRDLIB.Vcomponents.all;
1867 
use csx_IOLIB_3M.Vcomponents.all;
1868 
 
1869 
entity gf_phi1_register_0 is
1870 
 
1871 
   port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
1872 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
1873 
         std_logic_vector (0 to 31));
1874 
 
1875 
end gf_phi1_register_0;
1876 
 
1877 
architecture SYN_behavior_0 of gf_phi1_register_0 is
1878 
 
1879 
   component DFA
1880 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
1881 
   end component;
1882 
 
1883 
   component IN1
1884 
      port( A : in std_logic;  Q : out std_logic);
1885 
   end component;
1886 
 
1887 
   component IN3
1888 
      port( A : in std_logic;  Q : out std_logic);
1889 
   end component;
1890 
 
1891 
   component DFA2
1892 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
1893 
   end component;
1894 
 
1895 
   component BU4
1896 
      port( A : in std_logic;  Q : out std_logic);
1897 
   end component;
1898 
 
1899 
   component BU8
1900 
      port( A : in std_logic;  Q : out std_logic);
1901 
   end component;
1902 
 
1903 
   component IN4
1904 
      port( A : in std_logic;  Q : out std_logic);
1905 
   end component;
1906 
 
1907 
   signal n187, n188, n189, n191, n193, n195, n197, n199, n201, n203, n205,
1908 
      n207, n209, n211, n213, n215, n217, n219, n221, n223, n225, n227, n229,
1909 
      n231, n233, n235, n237, n239, n241, n243, n245, n247, n249, n251, n253,
1910 
      n255, n257, n259, n261, n263, n265, n267, n269, n271, n273, n442, n443,
1911 
      n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455,
1912 
      n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
1913 
      n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
1914 
      n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
1915 
      n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
1916 
      n504, n505 : std_logic;
1917 
 
1918 
begin
1919 
 
1920 
   output_wip_reg_27 : DFA port map( C => phi1, D => input_wip(4), Q => n442,
1921 
                           QN => n203, RN => n188);
1922 
   output_wip_reg_24 : DFA port map( C => phi1, D => input_wip(7), Q => n443,
1923 
                           QN => n209, RN => n187);
1924 
   output_wip_reg_22 : DFA port map( C => phi1, D => input_wip(9), Q => n444,
1925 
                           QN => n211, RN => n187);
1926 
   output_wip_reg_23 : DFA port map( C => phi1, D => input_wip(8), Q => n445,
1927 
                           QN => n227, RN => n188);
1928 
   U147 : IN1 port map( A => n197, Q => output_wip(1));
1929 
   U148 : IN1 port map( A => n199, Q => output_wip(2));
1930 
   U149 : IN1 port map( A => n203, Q => output_wip(4));
1931 
   U150 : IN1 port map( A => n207, Q => output_wip(6));
1932 
   U151 : IN1 port map( A => n209, Q => output_wip(7));
1933 
   U152 : IN1 port map( A => n211, Q => output_wip(9));
1934 
   U153 : IN1 port map( A => n213, Q => output_wip(12));
1935 
   U154 : IN1 port map( A => n215, Q => output_wip(14));
1936 
   U155 : IN1 port map( A => n217, Q => output_wip(28));
1937 
   U156 : IN1 port map( A => n219, Q => output_wip(16));
1938 
   U157 : IN1 port map( A => n221, Q => output_wip(18));
1939 
   U158 : IN1 port map( A => n223, Q => output_wip(19));
1940 
   U159 : IN1 port map( A => n225, Q => output_wip(25));
1941 
   U160 : IN1 port map( A => n227, Q => output_wip(8));
1942 
   U161 : IN1 port map( A => n229, Q => output_wip(13));
1943 
   U162 : IN1 port map( A => n231, Q => output_wip(15));
1944 
   U163 : IN1 port map( A => n233, Q => output_wip(17));
1945 
   U164 : IN1 port map( A => n235, Q => output_wip(20));
1946 
   U165 : IN1 port map( A => n237, Q => output_wip(21));
1947 
   U166 : IN1 port map( A => n239, Q => output_wip(22));
1948 
   U167 : IN1 port map( A => n241, Q => output_wip(23));
1949 
   U168 : IN1 port map( A => n243, Q => output_wip(24));
1950 
   U169 : IN1 port map( A => n245, Q => output_wip(26));
1951 
   U170 : IN1 port map( A => n247, Q => output_wip(27));
1952 
   U171 : IN1 port map( A => n249, Q => output_wip(29));
1953 
   U172 : IN1 port map( A => n251, Q => output_wip(30));
1954 
   U173 : IN1 port map( A => n257, Q => output_fcs(7));
1955 
   U174 : IN3 port map( A => n263, Q => output_fcs(14));
1956 
   U175 : IN3 port map( A => n269, Q => output_fcs(8));
1957 
   output_fcs_reg_31 : DFA2 port map( C => phi1, D => input_fcs(0), Q =>
1958 
                           output_fcs(0), QN => n446, RN => n188);
1959 
   output_fcs_reg_30 : DFA2 port map( C => phi1, D => input_fcs(1), Q =>
1960 
                           output_fcs(1), QN => n447, RN => n188);
1961 
   output_fcs_reg_29 : DFA2 port map( C => phi1, D => input_fcs(2), Q =>
1962 
                           output_fcs(2), QN => n448, RN => n188);
1963 
   output_fcs_reg_28 : DFA2 port map( C => phi1, D => input_fcs(3), Q =>
1964 
                           output_fcs(3), QN => n449, RN => n187);
1965 
   output_fcs_reg_26 : DFA2 port map( C => phi1, D => input_fcs(5), Q =>
1966 
                           output_fcs(5), QN => n450, RN => n188);
1967 
   output_fcs_reg_15 : DFA2 port map( C => phi1, D => input_fcs(16), Q =>
1968 
                           output_fcs(16), QN => n451, RN => n187);
1969 
   output_fcs_reg_14 : DFA2 port map( C => phi1, D => input_fcs(17), Q =>
1970 
                           output_fcs(17), QN => n452, RN => n187);
1971 
   output_fcs_reg_13 : DFA2 port map( C => phi1, D => input_fcs(18), Q =>
1972 
                           output_fcs(18), QN => n453, RN => n188);
1973 
   output_fcs_reg_12 : DFA2 port map( C => phi1, D => input_fcs(19), Q =>
1974 
                           output_fcs(19), QN => n454, RN => n188);
1975 
   output_fcs_reg_11 : DFA2 port map( C => phi1, D => input_fcs(20), Q =>
1976 
                           output_fcs(20), QN => n455, RN => n187);
1977 
   output_fcs_reg_10 : DFA2 port map( C => phi1, D => input_fcs(21), Q =>
1978 
                           output_fcs(21), QN => n456, RN => n187);
1979 
   output_fcs_reg_9 : DFA2 port map( C => phi1, D => input_fcs(22), Q =>
1980 
                           output_fcs(22), QN => n457, RN => n188);
1981 
   output_fcs_reg_8 : DFA2 port map( C => phi1, D => input_fcs(23), Q =>
1982 
                           output_fcs(23), QN => n458, RN => n188);
1983 
   output_fcs_reg_7 : DFA2 port map( C => phi1, D => input_fcs(24), Q =>
1984 
                           output_fcs(24), QN => n459, RN => n187);
1985 
   output_fcs_reg_6 : DFA2 port map( C => phi1, D => input_fcs(25), Q =>
1986 
                           output_fcs(25), QN => n460, RN => n188);
1987 
   output_fcs_reg_3 : DFA2 port map( C => phi1, D => input_fcs(28), Q =>
1988 
                           output_fcs(28), QN => n461, RN => n187);
1989 
   output_fcs_reg_2 : DFA2 port map( C => phi1, D => input_fcs(29), Q =>
1990 
                           output_fcs(29), QN => n462, RN => n187);
1991 
   output_fcs_reg_1 : DFA2 port map( C => phi1, D => input_fcs(30), Q =>
1992 
                           output_fcs(30), QN => n463, RN => n188);
1993 
   output_fcs_reg_0 : DFA2 port map( C => phi1, D => input_fcs(31), Q =>
1994 
                           output_fcs(31), QN => n464, RN => n188);
1995 
   U176 : BU4 port map( A => reset, Q => n187);
1996 
   U177 : BU8 port map( A => n187, Q => n188);
1997 
   U178 : IN3 port map( A => n189, Q => output_wip(31));
1998 
   output_wip_reg_0 : DFA2 port map( C => phi1, D => input_wip(31), Q => n465,
1999 
                           QN => n189, RN => n188);
2000 
   U179 : IN3 port map( A => n191, Q => output_wip(10));
2001 
   output_wip_reg_21 : DFA2 port map( C => phi1, D => input_wip(10), Q => n466,
2002 
                           QN => n191, RN => n188);
2003 
   U180 : IN3 port map( A => n193, Q => output_wip(11));
2004 
   output_wip_reg_20 : DFA2 port map( C => phi1, D => input_wip(11), Q => n467,
2005 
                           QN => n193, RN => n188);
2006 
   U181 : IN3 port map( A => n195, Q => output_wip(0));
2007 
   output_wip_reg_31 : DFA2 port map( C => phi1, D => input_wip(0), Q => n468,
2008 
                           QN => n195, RN => n188);
2009 
   output_wip_reg_30 : DFA2 port map( C => phi1, D => input_wip(1), Q => n469,
2010 
                           QN => n197, RN => n188);
2011 
   output_wip_reg_29 : DFA2 port map( C => phi1, D => input_wip(2), Q => n470,
2012 
                           QN => n199, RN => n187);
2013 
   U182 : IN3 port map( A => n201, Q => output_wip(3));
2014 
   output_wip_reg_28 : DFA2 port map( C => phi1, D => input_wip(3), Q => n471,
2015 
                           QN => n201, RN => n187);
2016 
   U183 : IN3 port map( A => n205, Q => output_wip(5));
2017 
   output_wip_reg_26 : DFA2 port map( C => phi1, D => input_wip(5), Q => n472,
2018 
                           QN => n205, RN => n188);
2019 
   output_wip_reg_25 : DFA2 port map( C => phi1, D => input_wip(6), Q => n473,
2020 
                           QN => n207, RN => n187);
2021 
   output_wip_reg_19 : DFA2 port map( C => phi1, D => input_wip(12), Q => n474,
2022 
                           QN => n213, RN => n187);
2023 
   output_wip_reg_17 : DFA2 port map( C => phi1, D => input_wip(14), Q => n475,
2024 
                           QN => n215, RN => n187);
2025 
   output_wip_reg_3 : DFA2 port map( C => phi1, D => input_wip(28), Q => n476,
2026 
                           QN => n217, RN => n187);
2027 
   output_wip_reg_15 : DFA2 port map( C => phi1, D => input_wip(16), Q => n477,
2028 
                           QN => n219, RN => n188);
2029 
   output_wip_reg_13 : DFA2 port map( C => phi1, D => input_wip(18), Q => n478,
2030 
                           QN => n221, RN => n188);
2031 
   output_wip_reg_12 : DFA2 port map( C => phi1, D => input_wip(19), Q => n479,
2032 
                           QN => n223, RN => n188);
2033 
   output_wip_reg_6 : DFA2 port map( C => phi1, D => input_wip(25), Q => n480,
2034 
                           QN => n225, RN => n188);
2035 
   output_wip_reg_18 : DFA2 port map( C => phi1, D => input_wip(13), Q => n481,
2036 
                           QN => n229, RN => n188);
2037 
   output_wip_reg_16 : DFA2 port map( C => phi1, D => input_wip(15), Q => n482,
2038 
                           QN => n231, RN => n187);
2039 
   output_wip_reg_14 : DFA2 port map( C => phi1, D => input_wip(17), Q => n483,
2040 
                           QN => n233, RN => n187);
2041 
   output_wip_reg_11 : DFA2 port map( C => phi1, D => input_wip(20), Q => n484,
2042 
                           QN => n235, RN => n188);
2043 
   output_wip_reg_10 : DFA2 port map( C => phi1, D => input_wip(21), Q => n485,
2044 
                           QN => n237, RN => n187);
2045 
   output_wip_reg_9 : DFA2 port map( C => phi1, D => input_wip(22), Q => n486,
2046 
                           QN => n239, RN => n187);
2047 
   output_wip_reg_8 : DFA2 port map( C => phi1, D => input_wip(23), Q => n487,
2048 
                           QN => n241, RN => n188);
2049 
   output_wip_reg_7 : DFA2 port map( C => phi1, D => input_wip(24), Q => n488,
2050 
                           QN => n243, RN => n188);
2051 
   output_wip_reg_5 : DFA2 port map( C => phi1, D => input_wip(26), Q => n489,
2052 
                           QN => n245, RN => n188);
2053 
   output_wip_reg_4 : DFA2 port map( C => phi1, D => input_wip(27), Q => n490,
2054 
                           QN => n247, RN => n187);
2055 
   output_wip_reg_2 : DFA2 port map( C => phi1, D => input_wip(29), Q => n491,
2056 
                           QN => n249, RN => n188);
2057 
   output_wip_reg_1 : DFA2 port map( C => phi1, D => input_wip(30), Q => n492,
2058 
                           QN => n251, RN => n188);
2059 
   U184 : IN4 port map( A => n253, Q => output_fcs(26));
2060 
   U185 : IN4 port map( A => n255, Q => output_fcs(27));
2061 
   U186 : IN4 port map( A => n259, Q => output_fcs(13));
2062 
   U187 : IN4 port map( A => n261, Q => output_fcs(15));
2063 
   U188 : IN4 port map( A => n265, Q => output_fcs(12));
2064 
   U189 : IN4 port map( A => n267, Q => output_fcs(11));
2065 
   U190 : IN4 port map( A => n271, Q => output_fcs(10));
2066 
   output_fcs_reg_21 : DFA2 port map( C => phi1, D => input_fcs(10), Q => n493,
2067 
                           QN => n271, RN => n187);
2068 
   U191 : IN4 port map( A => n273, Q => output_fcs(9));
2069 
   output_fcs_reg_22 : DFA2 port map( C => phi1, D => input_fcs(9), Q => n494,
2070 
                           QN => n273, RN => n188);
2071 
   output_fcs_reg_24 : DFA2 port map( C => phi1, D => input_fcs(7), Q => n495,
2072 
                           QN => n257, RN => n188);
2073 
   output_fcs_reg_25 : DFA2 port map( C => phi1, D => input_fcs(6), Q =>
2074 
                           output_fcs(6), QN => n496, RN => n188);
2075 
   output_fcs_reg_4 : DFA2 port map( C => phi1, D => input_fcs(27), Q => n497,
2076 
                           QN => n255, RN => n187);
2077 
   output_fcs_reg_5 : DFA2 port map( C => phi1, D => input_fcs(26), Q => n498,
2078 
                           QN => n253, RN => n187);
2079 
   output_fcs_reg_27 : DFA2 port map( C => phi1, D => input_fcs(4), Q =>
2080 
                           output_fcs(4), QN => n499, RN => n187);
2081 
   output_fcs_reg_17 : DFA2 port map( C => phi1, D => input_fcs(14), Q => n500,
2082 
                           QN => n263, RN => n188);
2083 
   output_fcs_reg_16 : DFA2 port map( C => phi1, D => input_fcs(15), Q => n501,
2084 
                           QN => n261, RN => n188);
2085 
   output_fcs_reg_23 : DFA2 port map( C => phi1, D => input_fcs(8), Q => n502,
2086 
                           QN => n269, RN => n188);
2087 
   output_fcs_reg_18 : DFA2 port map( C => phi1, D => input_fcs(13), Q => n503,
2088 
                           QN => n259, RN => n187);
2089 
   output_fcs_reg_19 : DFA2 port map( C => phi1, D => input_fcs(12), Q => n504,
2090 
                           QN => n265, RN => n187);
2091 
   output_fcs_reg_20 : DFA2 port map( C => phi1, D => input_fcs(11), Q => n505,
2092 
                           QN => n267, RN => n188);
2093 
 
2094 
end SYN_behavior_0;
2095 
 
2096 
library IEEE;
2097 
library csx_HRDLIB;
2098 
library csx_IOLIB_3M;
2099 
 
2100 
use IEEE.std_logic_1164.all;
2101 
use IEEE.std_logic_arith.all;
2102 
use csx_HRDLIB.Vcomponents.all;
2103 
use csx_IOLIB_3M.Vcomponents.all;
2104 
 
2105 
entity gf_phi1_register_1 is
2106 
 
2107 
   port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
2108 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
2109 
         std_logic_vector (0 to 31));
2110 
 
2111 
end gf_phi1_register_1;
2112 
 
2113 
architecture SYN_behavior_1 of gf_phi1_register_1 is
2114 
 
2115 
   component DFA
2116 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2117 
   end component;
2118 
 
2119 
   component IN1
2120 
      port( A : in std_logic;  Q : out std_logic);
2121 
   end component;
2122 
 
2123 
   component DFA2
2124 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2125 
   end component;
2126 
 
2127 
   component BU8
2128 
      port( A : in std_logic;  Q : out std_logic);
2129 
   end component;
2130 
 
2131 
   component BU4
2132 
      port( A : in std_logic;  Q : out std_logic);
2133 
   end component;
2134 
 
2135 
   component DFA4
2136 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2137 
   end component;
2138 
 
2139 
   component IN3
2140 
      port( A : in std_logic;  Q : out std_logic);
2141 
   end component;
2142 
 
2143 
   component IN4
2144 
      port( A : in std_logic;  Q : out std_logic);
2145 
   end component;
2146 
 
2147 
   component IN8
2148 
      port( A : in std_logic;  Q : out std_logic);
2149 
   end component;
2150 
 
2151 
   signal n214, n232, n236, n244, n252, n270, n274, n315, n317, n319, n321,
2152 
      n323, n325, n327, n329, n331, n333, n335, n337, n339, n341, n343, n345,
2153 
      n347, n349, n351, n353, n355, n357, n359, n361, n363, n365, n367, n369,
2154 
      n371, n373, n375, n377, n379, n381, n383, n385, n549, n550, n551, n552,
2155 
      n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
2156 
      n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
2157 
      n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
2158 
      n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
2159 
      n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612 :
2160 
      std_logic;
2161 
 
2162 
begin
2163 
 
2164 
   output_wip_reg_24 : DFA port map( C => phi1, D => input_wip(7), Q => n549,
2165 
                           QN => n236, RN => n232);
2166 
   output_wip_reg_29 : DFA port map( C => phi1, D => input_wip(2), Q => n550,
2167 
                           QN => n270, RN => n214);
2168 
   output_wip_reg_28 : DFA port map( C => phi1, D => input_wip(3), Q => n551,
2169 
                           QN => n274, RN => n232);
2170 
   output_wip_reg_12 : DFA port map( C => phi1, D => input_wip(19), Q => n552,
2171 
                           QN => n335, RN => n232);
2172 
   output_wip_reg_5 : DFA port map( C => phi1, D => input_wip(26), Q => n553,
2173 
                           QN => n349, RN => n232);
2174 
   U147 : IN1 port map( A => n236, Q => output_wip(7));
2175 
   U148 : IN1 port map( A => n270, Q => output_wip(2));
2176 
   U149 : IN1 port map( A => n274, Q => output_wip(3));
2177 
   U150 : IN1 port map( A => n317, Q => output_wip(9));
2178 
   U151 : IN1 port map( A => n323, Q => output_wip(13));
2179 
   U152 : IN1 port map( A => n331, Q => output_wip(17));
2180 
   U153 : IN1 port map( A => n335, Q => output_wip(19));
2181 
   U154 : IN1 port map( A => n341, Q => output_wip(22));
2182 
   U155 : IN1 port map( A => n345, Q => output_wip(24));
2183 
   U156 : IN1 port map( A => n349, Q => output_wip(26));
2184 
   U157 : IN1 port map( A => n351, Q => output_wip(27));
2185 
   U158 : IN1 port map( A => n353, Q => output_wip(28));
2186 
   U159 : IN1 port map( A => n357, Q => output_wip(30));
2187 
   U160 : IN1 port map( A => n359, Q => output_wip(31));
2188 
   U161 : IN1 port map( A => n361, Q => output_wip(4));
2189 
   U162 : IN1 port map( A => n363, Q => output_wip(5));
2190 
   U163 : IN1 port map( A => n365, Q => output_wip(6));
2191 
   U164 : IN1 port map( A => n367, Q => output_wip(11));
2192 
   U165 : IN1 port map( A => n373, Q => output_fcs(11));
2193 
   U166 : IN1 port map( A => n371, Q => output_fcs(10));
2194 
   output_fcs_reg_19 : DFA2 port map( C => phi1, D => input_fcs(12), Q =>
2195 
                           output_fcs(12), QN => n554, RN => n214);
2196 
   output_fcs_reg_18 : DFA2 port map( C => phi1, D => input_fcs(13), Q =>
2197 
                           output_fcs(13), QN => n555, RN => n232);
2198 
   output_fcs_reg_17 : DFA2 port map( C => phi1, D => input_fcs(14), Q =>
2199 
                           output_fcs(14), QN => n556, RN => n214);
2200 
   output_fcs_reg_16 : DFA2 port map( C => phi1, D => input_fcs(15), Q =>
2201 
                           output_fcs(15), QN => n557, RN => n232);
2202 
   output_fcs_reg_15 : DFA2 port map( C => phi1, D => input_fcs(16), Q =>
2203 
                           output_fcs(16), QN => n558, RN => n232);
2204 
   output_fcs_reg_14 : DFA2 port map( C => phi1, D => input_fcs(17), Q =>
2205 
                           output_fcs(17), QN => n559, RN => n232);
2206 
   output_fcs_reg_13 : DFA2 port map( C => phi1, D => input_fcs(18), Q =>
2207 
                           output_fcs(18), QN => n560, RN => n232);
2208 
   output_fcs_reg_12 : DFA2 port map( C => phi1, D => input_fcs(19), Q =>
2209 
                           output_fcs(19), QN => n561, RN => n232);
2210 
   output_fcs_reg_11 : DFA2 port map( C => phi1, D => input_fcs(20), Q =>
2211 
                           output_fcs(20), QN => n562, RN => n232);
2212 
   output_fcs_reg_10 : DFA2 port map( C => phi1, D => input_fcs(21), Q =>
2213 
                           output_fcs(21), QN => n563, RN => n232);
2214 
   output_fcs_reg_9 : DFA2 port map( C => phi1, D => input_fcs(22), Q =>
2215 
                           output_fcs(22), QN => n564, RN => n232);
2216 
   output_fcs_reg_8 : DFA2 port map( C => phi1, D => input_fcs(23), Q =>
2217 
                           output_fcs(23), QN => n565, RN => n232);
2218 
   output_fcs_reg_7 : DFA2 port map( C => phi1, D => input_fcs(24), Q =>
2219 
                           output_fcs(24), QN => n566, RN => n232);
2220 
   output_fcs_reg_6 : DFA2 port map( C => phi1, D => input_fcs(25), Q =>
2221 
                           output_fcs(25), QN => n567, RN => n232);
2222 
   output_fcs_reg_5 : DFA2 port map( C => phi1, D => input_fcs(26), Q =>
2223 
                           output_fcs(26), QN => n568, RN => n232);
2224 
   output_fcs_reg_4 : DFA2 port map( C => phi1, D => input_fcs(27), Q =>
2225 
                           output_fcs(27), QN => n569, RN => n232);
2226 
   output_fcs_reg_3 : DFA2 port map( C => phi1, D => input_fcs(28), Q =>
2227 
                           output_fcs(28), QN => n570, RN => n232);
2228 
   output_fcs_reg_2 : DFA2 port map( C => phi1, D => input_fcs(29), Q =>
2229 
                           output_fcs(29), QN => n571, RN => n232);
2230 
   output_fcs_reg_1 : DFA2 port map( C => phi1, D => input_fcs(30), Q =>
2231 
                           output_fcs(30), QN => n572, RN => n232);
2232 
   output_fcs_reg_0 : DFA2 port map( C => phi1, D => input_fcs(31), Q =>
2233 
                           output_fcs(31), QN => n573, RN => n232);
2234 
   U167 : BU8 port map( A => n214, Q => n232);
2235 
   U168 : BU4 port map( A => reset, Q => n214);
2236 
   output_fcs_reg_24 : DFA4 port map( C => phi1, D => input_fcs(7), Q => n574,
2237 
                           QN => n383, RN => n232);
2238 
   output_fcs_reg_25 : DFA4 port map( C => phi1, D => input_fcs(6), Q => n575,
2239 
                           QN => n385, RN => n232);
2240 
   U169 : IN3 port map( A => n244, Q => output_wip(0));
2241 
   output_wip_reg_31 : DFA2 port map( C => phi1, D => input_wip(0), Q => n576,
2242 
                           QN => n244, RN => n232);
2243 
   U170 : IN3 port map( A => n252, Q => output_wip(1));
2244 
   output_wip_reg_30 : DFA2 port map( C => phi1, D => input_wip(1), Q => n577,
2245 
                           QN => n252, RN => n232);
2246 
   U171 : IN3 port map( A => n315, Q => output_wip(8));
2247 
   output_wip_reg_23 : DFA2 port map( C => phi1, D => input_wip(8), Q => n578,
2248 
                           QN => n315, RN => n232);
2249 
   output_wip_reg_22 : DFA2 port map( C => phi1, D => input_wip(9), Q => n579,
2250 
                           QN => n317, RN => n214);
2251 
   U172 : IN3 port map( A => n319, Q => output_wip(10));
2252 
   output_wip_reg_21 : DFA2 port map( C => phi1, D => input_wip(10), Q => n580,
2253 
                           QN => n319, RN => n214);
2254 
   U173 : IN3 port map( A => n321, Q => output_wip(12));
2255 
   output_wip_reg_19 : DFA2 port map( C => phi1, D => input_wip(12), Q => n581,
2256 
                           QN => n321, RN => n214);
2257 
   output_wip_reg_18 : DFA2 port map( C => phi1, D => input_wip(13), Q => n582,
2258 
                           QN => n323, RN => n232);
2259 
   U174 : IN3 port map( A => n325, Q => output_wip(14));
2260 
   output_wip_reg_17 : DFA2 port map( C => phi1, D => input_wip(14), Q => n583,
2261 
                           QN => n325, RN => n232);
2262 
   U175 : IN3 port map( A => n327, Q => output_wip(15));
2263 
   output_wip_reg_16 : DFA2 port map( C => phi1, D => input_wip(15), Q => n584,
2264 
                           QN => n327, RN => n214);
2265 
   U176 : IN3 port map( A => n329, Q => output_wip(16));
2266 
   output_wip_reg_15 : DFA2 port map( C => phi1, D => input_wip(16), Q => n585,
2267 
                           QN => n329, RN => n214);
2268 
   output_wip_reg_14 : DFA2 port map( C => phi1, D => input_wip(17), Q => n586,
2269 
                           QN => n331, RN => n232);
2270 
   U177 : IN3 port map( A => n333, Q => output_wip(18));
2271 
   output_wip_reg_13 : DFA2 port map( C => phi1, D => input_wip(18), Q => n587,
2272 
                           QN => n333, RN => n232);
2273 
   U178 : IN3 port map( A => n337, Q => output_wip(20));
2274 
   output_wip_reg_11 : DFA2 port map( C => phi1, D => input_wip(20), Q => n588,
2275 
                           QN => n337, RN => n232);
2276 
   U179 : IN3 port map( A => n339, Q => output_wip(21));
2277 
   output_wip_reg_10 : DFA2 port map( C => phi1, D => input_wip(21), Q => n589,
2278 
                           QN => n339, RN => n232);
2279 
   output_wip_reg_9 : DFA2 port map( C => phi1, D => input_wip(22), Q => n590,
2280 
                           QN => n341, RN => n232);
2281 
   U180 : IN3 port map( A => n343, Q => output_wip(23));
2282 
   output_wip_reg_8 : DFA2 port map( C => phi1, D => input_wip(23), Q => n591,
2283 
                           QN => n343, RN => n214);
2284 
   output_wip_reg_7 : DFA2 port map( C => phi1, D => input_wip(24), Q => n592,
2285 
                           QN => n345, RN => n214);
2286 
   U181 : IN3 port map( A => n347, Q => output_wip(25));
2287 
   output_wip_reg_6 : DFA2 port map( C => phi1, D => input_wip(25), Q => n593,
2288 
                           QN => n347, RN => n232);
2289 
   output_wip_reg_4 : DFA2 port map( C => phi1, D => input_wip(27), Q => n594,
2290 
                           QN => n351, RN => n214);
2291 
   output_wip_reg_3 : DFA2 port map( C => phi1, D => input_wip(28), Q => n595,
2292 
                           QN => n353, RN => n232);
2293 
   U182 : IN3 port map( A => n355, Q => output_wip(29));
2294 
   output_wip_reg_2 : DFA2 port map( C => phi1, D => input_wip(29), Q => n596,
2295 
                           QN => n355, RN => n232);
2296 
   output_wip_reg_1 : DFA2 port map( C => phi1, D => input_wip(30), Q => n597,
2297 
                           QN => n357, RN => n232);
2298 
   output_wip_reg_0 : DFA2 port map( C => phi1, D => input_wip(31), Q => n598,
2299 
                           QN => n359, RN => n232);
2300 
   output_wip_reg_27 : DFA2 port map( C => phi1, D => input_wip(4), Q => n599,
2301 
                           QN => n361, RN => n232);
2302 
   output_wip_reg_26 : DFA2 port map( C => phi1, D => input_wip(5), Q => n600,
2303 
                           QN => n363, RN => n214);
2304 
   output_wip_reg_25 : DFA2 port map( C => phi1, D => input_wip(6), Q => n601,
2305 
                           QN => n365, RN => n214);
2306 
   output_wip_reg_20 : DFA2 port map( C => phi1, D => input_wip(11), Q => n602,
2307 
                           QN => n367, RN => n214);
2308 
   U183 : IN4 port map( A => n369, Q => output_fcs(9));
2309 
   output_fcs_reg_20 : DFA2 port map( C => phi1, D => input_fcs(11), Q => n603,
2310 
                           QN => n373, RN => n214);
2311 
   U184 : IN4 port map( A => n375, Q => output_fcs(3));
2312 
   U185 : IN4 port map( A => n377, Q => output_fcs(8));
2313 
   U186 : IN8 port map( A => n385, Q => output_fcs(6));
2314 
   U187 : IN8 port map( A => n383, Q => output_fcs(7));
2315 
   U188 : IN4 port map( A => n379, Q => output_fcs(5));
2316 
   U189 : IN4 port map( A => n381, Q => output_fcs(4));
2317 
   output_fcs_reg_27 : DFA2 port map( C => phi1, D => input_fcs(4), Q => n604,
2318 
                           QN => n381, RN => n214);
2319 
   output_fcs_reg_21 : DFA2 port map( C => phi1, D => input_fcs(10), Q => n605,
2320 
                           QN => n371, RN => n214);
2321 
   output_fcs_reg_30 : DFA2 port map( C => phi1, D => input_fcs(1), Q =>
2322 
                           output_fcs(1), QN => n606, RN => n214);
2323 
   output_fcs_reg_23 : DFA2 port map( C => phi1, D => input_fcs(8), Q => n607,
2324 
                           QN => n377, RN => n214);
2325 
   output_fcs_reg_22 : DFA2 port map( C => phi1, D => input_fcs(9), Q => n608,
2326 
                           QN => n369, RN => n214);
2327 
   output_fcs_reg_26 : DFA2 port map( C => phi1, D => input_fcs(5), Q => n609,
2328 
                           QN => n379, RN => n214);
2329 
   output_fcs_reg_29 : DFA2 port map( C => phi1, D => input_fcs(2), Q =>
2330 
                           output_fcs(2), QN => n610, RN => n232);
2331 
   output_fcs_reg_28 : DFA2 port map( C => phi1, D => input_fcs(3), Q => n611,
2332 
                           QN => n375, RN => n214);
2333 
   output_fcs_reg_31 : DFA2 port map( C => phi1, D => input_fcs(0), Q =>
2334 
                           output_fcs(0), QN => n612, RN => n232);
2335 
 
2336 
end SYN_behavior_1;
2337 
 
2338 
library IEEE;
2339 
library csx_HRDLIB;
2340 
library csx_IOLIB_3M;
2341 
 
2342 
use IEEE.std_logic_1164.all;
2343 
use IEEE.std_logic_arith.all;
2344 
use csx_HRDLIB.Vcomponents.all;
2345 
use csx_IOLIB_3M.Vcomponents.all;
2346 
 
2347 
entity gf_phi1_register_2 is
2348 
 
2349 
   port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
2350 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
2351 
         std_logic_vector (0 to 31));
2352 
 
2353 
end gf_phi1_register_2;
2354 
 
2355 
architecture SYN_behavior_2 of gf_phi1_register_2 is
2356 
 
2357 
   component IN1
2358 
      port( A : in std_logic;  Q : out std_logic);
2359 
   end component;
2360 
 
2361 
   component DFA2
2362 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2363 
   end component;
2364 
 
2365 
   component BU4
2366 
      port( A : in std_logic;  Q : out std_logic);
2367 
   end component;
2368 
 
2369 
   component BU2
2370 
      port( A : in std_logic;  Q : out std_logic);
2371 
   end component;
2372 
 
2373 
   component IN3
2374 
      port( A : in std_logic;  Q : out std_logic);
2375 
   end component;
2376 
 
2377 
   component IN4
2378 
      port( A : in std_logic;  Q : out std_logic);
2379 
   end component;
2380 
 
2381 
   signal n318, n322, n326, n330, n342, n346, n350, n354, n358, n362, n366,
2382 
      n370, n374, n378, n557, n558, n559, n560, n561, n562, n563, n564, n565,
2383 
      n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
2384 
      n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
2385 
      n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
2386 
      n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
2387 
      n614, n615, n616, n617, n618, n619, n620 : std_logic;
2388 
 
2389 
begin
2390 
 
2391 
   U147 : IN1 port map( A => n366, Q => output_wip(19));
2392 
   output_fcs_reg_31 : DFA2 port map( C => phi1, D => input_fcs(0), Q =>
2393 
                           output_fcs(0), QN => n557, RN => n326);
2394 
   output_fcs_reg_30 : DFA2 port map( C => phi1, D => input_fcs(1), Q =>
2395 
                           output_fcs(1), QN => n558, RN => n322);
2396 
   output_fcs_reg_29 : DFA2 port map( C => phi1, D => input_fcs(2), Q =>
2397 
                           output_fcs(2), QN => n559, RN => n326);
2398 
   output_fcs_reg_28 : DFA2 port map( C => phi1, D => input_fcs(3), Q =>
2399 
                           output_fcs(3), QN => n560, RN => n322);
2400 
   output_fcs_reg_27 : DFA2 port map( C => phi1, D => input_fcs(4), Q =>
2401 
                           output_fcs(4), QN => n561, RN => n326);
2402 
   output_fcs_reg_26 : DFA2 port map( C => phi1, D => input_fcs(5), Q =>
2403 
                           output_fcs(5), QN => n562, RN => n322);
2404 
   output_fcs_reg_25 : DFA2 port map( C => phi1, D => input_fcs(6), Q =>
2405 
                           output_fcs(6), QN => n563, RN => n326);
2406 
   output_fcs_reg_24 : DFA2 port map( C => phi1, D => input_fcs(7), Q =>
2407 
                           output_fcs(7), QN => n564, RN => n322);
2408 
   output_fcs_reg_23 : DFA2 port map( C => phi1, D => input_fcs(8), Q =>
2409 
                           output_fcs(8), QN => n565, RN => n326);
2410 
   output_fcs_reg_22 : DFA2 port map( C => phi1, D => input_fcs(9), Q =>
2411 
                           output_fcs(9), QN => n566, RN => n322);
2412 
   output_fcs_reg_21 : DFA2 port map( C => phi1, D => input_fcs(10), Q =>
2413 
                           output_fcs(10), QN => n567, RN => n318);
2414 
   output_fcs_reg_20 : DFA2 port map( C => phi1, D => input_fcs(11), Q =>
2415 
                           output_fcs(11), QN => n568, RN => n326);
2416 
   output_fcs_reg_15 : DFA2 port map( C => phi1, D => input_fcs(16), Q =>
2417 
                           output_fcs(16), QN => n569, RN => n322);
2418 
   output_fcs_reg_14 : DFA2 port map( C => phi1, D => input_fcs(17), Q =>
2419 
                           output_fcs(17), QN => n570, RN => n322);
2420 
   output_fcs_reg_13 : DFA2 port map( C => phi1, D => input_fcs(18), Q =>
2421 
                           output_fcs(18), QN => n571, RN => n322);
2422 
   output_fcs_reg_12 : DFA2 port map( C => phi1, D => input_fcs(19), Q =>
2423 
                           output_fcs(19), QN => n572, RN => n322);
2424 
   output_fcs_reg_11 : DFA2 port map( C => phi1, D => input_fcs(20), Q =>
2425 
                           output_fcs(20), QN => n573, RN => n322);
2426 
   output_fcs_reg_10 : DFA2 port map( C => phi1, D => input_fcs(21), Q =>
2427 
                           output_fcs(21), QN => n574, RN => n322);
2428 
   output_fcs_reg_9 : DFA2 port map( C => phi1, D => input_fcs(22), Q =>
2429 
                           output_fcs(22), QN => n575, RN => n322);
2430 
   output_fcs_reg_8 : DFA2 port map( C => phi1, D => input_fcs(23), Q =>
2431 
                           output_fcs(23), QN => n576, RN => n318);
2432 
   output_fcs_reg_7 : DFA2 port map( C => phi1, D => input_fcs(24), Q =>
2433 
                           output_fcs(24), QN => n577, RN => n322);
2434 
   output_fcs_reg_6 : DFA2 port map( C => phi1, D => input_fcs(25), Q =>
2435 
                           output_fcs(25), QN => n578, RN => n322);
2436 
   output_fcs_reg_5 : DFA2 port map( C => phi1, D => input_fcs(26), Q =>
2437 
                           output_fcs(26), QN => n579, RN => n322);
2438 
   output_fcs_reg_4 : DFA2 port map( C => phi1, D => input_fcs(27), Q =>
2439 
                           output_fcs(27), QN => n580, RN => n322);
2440 
   output_fcs_reg_3 : DFA2 port map( C => phi1, D => input_fcs(28), Q =>
2441 
                           output_fcs(28), QN => n581, RN => n322);
2442 
   output_fcs_reg_2 : DFA2 port map( C => phi1, D => input_fcs(29), Q =>
2443 
                           output_fcs(29), QN => n582, RN => n326);
2444 
   output_fcs_reg_1 : DFA2 port map( C => phi1, D => input_fcs(30), Q =>
2445 
                           output_fcs(30), QN => n583, RN => n322);
2446 
   output_fcs_reg_0 : DFA2 port map( C => phi1, D => input_fcs(31), Q =>
2447 
                           output_fcs(31), QN => n584, RN => n326);
2448 
   output_wip_reg_31 : DFA2 port map( C => phi1, D => input_wip(0), Q =>
2449 
                           output_wip(0), QN => n585, RN => n322);
2450 
   output_wip_reg_30 : DFA2 port map( C => phi1, D => input_wip(1), Q =>
2451 
                           output_wip(1), QN => n586, RN => n322);
2452 
   output_wip_reg_29 : DFA2 port map( C => phi1, D => input_wip(2), Q =>
2453 
                           output_wip(2), QN => n587, RN => n322);
2454 
   output_wip_reg_28 : DFA2 port map( C => phi1, D => input_wip(3), Q =>
2455 
                           output_wip(3), QN => n588, RN => n318);
2456 
   output_wip_reg_27 : DFA2 port map( C => phi1, D => input_wip(4), Q =>
2457 
                           output_wip(4), QN => n589, RN => n326);
2458 
   output_wip_reg_26 : DFA2 port map( C => phi1, D => input_wip(5), Q =>
2459 
                           output_wip(5), QN => n590, RN => n326);
2460 
   output_wip_reg_25 : DFA2 port map( C => phi1, D => input_wip(6), Q =>
2461 
                           output_wip(6), QN => n591, RN => n326);
2462 
   output_wip_reg_24 : DFA2 port map( C => phi1, D => input_wip(7), Q =>
2463 
                           output_wip(7), QN => n592, RN => n326);
2464 
   output_wip_reg_23 : DFA2 port map( C => phi1, D => input_wip(8), Q =>
2465 
                           output_wip(8), QN => n593, RN => n326);
2466 
   output_wip_reg_22 : DFA2 port map( C => phi1, D => input_wip(9), Q =>
2467 
                           output_wip(9), QN => n594, RN => n326);
2468 
   output_wip_reg_21 : DFA2 port map( C => phi1, D => input_wip(10), Q =>
2469 
                           output_wip(10), QN => n595, RN => n326);
2470 
   output_wip_reg_20 : DFA2 port map( C => phi1, D => input_wip(11), Q =>
2471 
                           output_wip(11), QN => n596, RN => n318);
2472 
   output_wip_reg_19 : DFA2 port map( C => phi1, D => input_wip(12), Q =>
2473 
                           output_wip(12), QN => n597, RN => n326);
2474 
   output_wip_reg_18 : DFA2 port map( C => phi1, D => input_wip(13), Q =>
2475 
                           output_wip(13), QN => n598, RN => n326);
2476 
   output_wip_reg_17 : DFA2 port map( C => phi1, D => input_wip(14), Q =>
2477 
                           output_wip(14), QN => n599, RN => n326);
2478 
   output_wip_reg_16 : DFA2 port map( C => phi1, D => input_wip(15), Q =>
2479 
                           output_wip(15), QN => n600, RN => n326);
2480 
   output_wip_reg_10 : DFA2 port map( C => phi1, D => input_wip(21), Q =>
2481 
                           output_wip(21), QN => n601, RN => n326);
2482 
   output_wip_reg_0 : DFA2 port map( C => phi1, D => input_wip(31), Q =>
2483 
                           output_wip(31), QN => n602, RN => n326);
2484 
   U148 : BU4 port map( A => n318, Q => n326);
2485 
   U149 : BU4 port map( A => n318, Q => n322);
2486 
   U150 : BU2 port map( A => reset, Q => n318);
2487 
   U151 : IN3 port map( A => n330, Q => output_wip(27));
2488 
   output_wip_reg_4 : DFA2 port map( C => phi1, D => input_wip(27), Q => n603,
2489 
                           QN => n330, RN => n318);
2490 
   U152 : IN3 port map( A => n342, Q => output_wip(29));
2491 
   output_wip_reg_2 : DFA2 port map( C => phi1, D => input_wip(29), Q => n604,
2492 
                           QN => n342, RN => n318);
2493 
   U153 : IN3 port map( A => n346, Q => output_wip(26));
2494 
   output_wip_reg_5 : DFA2 port map( C => phi1, D => input_wip(26), Q => n605,
2495 
                           QN => n346, RN => n318);
2496 
   U154 : IN3 port map( A => n350, Q => output_wip(17));
2497 
   output_wip_reg_14 : DFA2 port map( C => phi1, D => input_wip(17), Q => n606,
2498 
                           QN => n350, RN => n318);
2499 
   U155 : IN3 port map( A => n354, Q => output_wip(25));
2500 
   output_wip_reg_6 : DFA2 port map( C => phi1, D => input_wip(25), Q => n607,
2501 
                           QN => n354, RN => n318);
2502 
   U156 : IN3 port map( A => n358, Q => output_wip(28));
2503 
   output_wip_reg_3 : DFA2 port map( C => phi1, D => input_wip(28), Q => n608,
2504 
                           QN => n358, RN => n326);
2505 
   U157 : IN3 port map( A => n362, Q => output_wip(18));
2506 
   output_wip_reg_13 : DFA2 port map( C => phi1, D => input_wip(18), Q => n609,
2507 
                           QN => n362, RN => n326);
2508 
   output_wip_reg_12 : DFA2 port map( C => phi1, D => input_wip(19), Q => n610,
2509 
                           QN => n366, RN => n326);
2510 
   U158 : IN4 port map( A => n370, Q => output_fcs(13));
2511 
   U159 : IN4 port map( A => n374, Q => output_fcs(15));
2512 
   U160 : IN4 port map( A => n378, Q => output_fcs(14));
2513 
   output_fcs_reg_18 : DFA2 port map( C => phi1, D => input_fcs(13), Q => n611,
2514 
                           QN => n370, RN => n322);
2515 
   output_fcs_reg_16 : DFA2 port map( C => phi1, D => input_fcs(15), Q => n612,
2516 
                           QN => n374, RN => n326);
2517 
   output_wip_reg_15 : DFA2 port map( C => phi1, D => input_wip(16), Q =>
2518 
                           output_wip(16), QN => n613, RN => n322);
2519 
   output_wip_reg_9 : DFA2 port map( C => phi1, D => input_wip(22), Q =>
2520 
                           output_wip(22), QN => n614, RN => n326);
2521 
   output_wip_reg_11 : DFA2 port map( C => phi1, D => input_wip(20), Q =>
2522 
                           output_wip(20), QN => n615, RN => n322);
2523 
   output_wip_reg_8 : DFA2 port map( C => phi1, D => input_wip(23), Q =>
2524 
                           output_wip(23), QN => n616, RN => n326);
2525 
   output_wip_reg_7 : DFA2 port map( C => phi1, D => input_wip(24), Q =>
2526 
                           output_wip(24), QN => n617, RN => n322);
2527 
   output_wip_reg_1 : DFA2 port map( C => phi1, D => input_wip(30), Q =>
2528 
                           output_wip(30), QN => n618, RN => n326);
2529 
   output_fcs_reg_19 : DFA2 port map( C => phi1, D => input_fcs(12), Q =>
2530 
                           output_fcs(12), QN => n619, RN => n322);
2531 
   output_fcs_reg_17 : DFA2 port map( C => phi1, D => input_fcs(14), Q => n620,
2532 
                           QN => n378, RN => n322);
2533 
 
2534 
end SYN_behavior_2;
2535 
 
2536 
library IEEE;
2537 
library csx_HRDLIB;
2538 
library csx_IOLIB_3M;
2539 
 
2540 
use IEEE.std_logic_1164.all;
2541 
use IEEE.std_logic_arith.all;
2542 
use csx_HRDLIB.Vcomponents.all;
2543 
use csx_IOLIB_3M.Vcomponents.all;
2544 
 
2545 
entity gf_phi1_register_3 is
2546 
 
2547 
   port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
2548 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
2549 
         std_logic_vector (0 to 31));
2550 
 
2551 
end gf_phi1_register_3;
2552 
 
2553 
architecture SYN_behavior_3 of gf_phi1_register_3 is
2554 
 
2555 
   component DFA
2556 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2557 
   end component;
2558 
 
2559 
   component IN1
2560 
      port( A : in std_logic;  Q : out std_logic);
2561 
   end component;
2562 
 
2563 
   component DFA2
2564 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2565 
   end component;
2566 
 
2567 
   component BU4
2568 
      port( A : in std_logic;  Q : out std_logic);
2569 
   end component;
2570 
 
2571 
   component BU8
2572 
      port( A : in std_logic;  Q : out std_logic);
2573 
   end component;
2574 
 
2575 
   component IN3
2576 
      port( A : in std_logic;  Q : out std_logic);
2577 
   end component;
2578 
 
2579 
   component IN4
2580 
      port( A : in std_logic;  Q : out std_logic);
2581 
   end component;
2582 
 
2583 
   signal n340, n344, n348, n356, n364, n372, n380, n430, n432, n434, n436,
2584 
      n438, n440, n442, n444, n446, n448, n450, n452, n454, n456, n458, n460,
2585 
      n462, n464, n466, n468, n470, n472, n474, n627, n628, n629, n630, n631,
2586 
      n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
2587 
      n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
2588 
      n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
2589 
      n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
2590 
      n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690 :
2591 
      std_logic;
2592 
 
2593 
begin
2594 
 
2595 
   output_wip_reg_11 : DFA port map( C => phi1, D => input_wip(20), Q => n627,
2596 
                           QN => n434, RN => n344);
2597 
   output_wip_reg_8 : DFA port map( C => phi1, D => input_wip(23), Q => n628,
2598 
                           QN => n436, RN => n344);
2599 
   output_wip_reg_1 : DFA port map( C => phi1, D => input_wip(30), Q => n629,
2600 
                           QN => n446, RN => n340);
2601 
   output_wip_reg_9 : DFA port map( C => phi1, D => input_wip(22), Q => n630,
2602 
                           QN => n452, RN => n344);
2603 
   output_wip_reg_2 : DFA port map( C => phi1, D => input_wip(29), Q => n631,
2604 
                           QN => n456, RN => n344);
2605 
   U147 : IN1 port map( A => n430, Q => output_wip(18));
2606 
   U148 : IN1 port map( A => n432, Q => output_wip(19));
2607 
   U149 : IN1 port map( A => n434, Q => output_wip(20));
2608 
   U150 : IN1 port map( A => n436, Q => output_wip(23));
2609 
   U151 : IN1 port map( A => n438, Q => output_wip(24));
2610 
   U152 : IN1 port map( A => n440, Q => output_wip(25));
2611 
   U153 : IN1 port map( A => n442, Q => output_wip(27));
2612 
   U154 : IN1 port map( A => n444, Q => output_wip(28));
2613 
   U155 : IN1 port map( A => n446, Q => output_wip(30));
2614 
   U156 : IN1 port map( A => n448, Q => output_wip(16));
2615 
   U157 : IN1 port map( A => n450, Q => output_wip(17));
2616 
   U158 : IN1 port map( A => n452, Q => output_wip(22));
2617 
   U159 : IN1 port map( A => n454, Q => output_wip(26));
2618 
   U160 : IN1 port map( A => n456, Q => output_wip(29));
2619 
   output_fcs_reg_31 : DFA2 port map( C => phi1, D => input_fcs(0), Q =>
2620 
                           output_fcs(0), QN => n632, RN => n340);
2621 
   output_fcs_reg_30 : DFA2 port map( C => phi1, D => input_fcs(1), Q =>
2622 
                           output_fcs(1), QN => n633, RN => n340);
2623 
   output_fcs_reg_29 : DFA2 port map( C => phi1, D => input_fcs(2), Q =>
2624 
                           output_fcs(2), QN => n634, RN => n344);
2625 
   output_fcs_reg_28 : DFA2 port map( C => phi1, D => input_fcs(3), Q =>
2626 
                           output_fcs(3), QN => n635, RN => n344);
2627 
   output_fcs_reg_27 : DFA2 port map( C => phi1, D => input_fcs(4), Q =>
2628 
                           output_fcs(4), QN => n636, RN => n340);
2629 
   output_fcs_reg_26 : DFA2 port map( C => phi1, D => input_fcs(5), Q =>
2630 
                           output_fcs(5), QN => n637, RN => n344);
2631 
   output_fcs_reg_25 : DFA2 port map( C => phi1, D => input_fcs(6), Q =>
2632 
                           output_fcs(6), QN => n638, RN => n340);
2633 
   output_fcs_reg_24 : DFA2 port map( C => phi1, D => input_fcs(7), Q =>
2634 
                           output_fcs(7), QN => n639, RN => n340);
2635 
   output_fcs_reg_5 : DFA2 port map( C => phi1, D => input_fcs(26), Q =>
2636 
                           output_fcs(26), QN => n640, RN => n344);
2637 
   output_fcs_reg_4 : DFA2 port map( C => phi1, D => input_fcs(27), Q =>
2638 
                           output_fcs(27), QN => n641, RN => n344);
2639 
   output_wip_reg_21 : DFA2 port map( C => phi1, D => input_wip(10), Q =>
2640 
                           output_wip(10), QN => n642, RN => n340);
2641 
   output_wip_reg_20 : DFA2 port map( C => phi1, D => input_wip(11), Q =>
2642 
                           output_wip(11), QN => n643, RN => n344);
2643 
   output_wip_reg_0 : DFA2 port map( C => phi1, D => input_wip(31), Q =>
2644 
                           output_wip(31), QN => n644, RN => n344);
2645 
   U161 : BU4 port map( A => reset, Q => n340);
2646 
   U162 : BU8 port map( A => n340, Q => n344);
2647 
   U163 : IN3 port map( A => n348, Q => output_wip(21));
2648 
   output_wip_reg_10 : DFA2 port map( C => phi1, D => input_wip(21), Q => n645,
2649 
                           QN => n348, RN => n344);
2650 
   U164 : IN3 port map( A => n356, Q => output_wip(8));
2651 
   output_wip_reg_23 : DFA2 port map( C => phi1, D => input_wip(8), Q => n646,
2652 
                           QN => n356, RN => n344);
2653 
   U165 : IN3 port map( A => n364, Q => output_wip(13));
2654 
   output_wip_reg_18 : DFA2 port map( C => phi1, D => input_wip(13), Q => n647,
2655 
                           QN => n364, RN => n344);
2656 
   U166 : IN3 port map( A => n372, Q => output_wip(14));
2657 
   output_wip_reg_17 : DFA2 port map( C => phi1, D => input_wip(14), Q => n648,
2658 
                           QN => n372, RN => n344);
2659 
   U167 : IN3 port map( A => n380, Q => output_wip(15));
2660 
   output_wip_reg_16 : DFA2 port map( C => phi1, D => input_wip(15), Q => n649,
2661 
                           QN => n380, RN => n344);
2662 
   output_wip_reg_13 : DFA2 port map( C => phi1, D => input_wip(18), Q => n650,
2663 
                           QN => n430, RN => n340);
2664 
   output_wip_reg_12 : DFA2 port map( C => phi1, D => input_wip(19), Q => n651,
2665 
                           QN => n432, RN => n340);
2666 
   output_wip_reg_7 : DFA2 port map( C => phi1, D => input_wip(24), Q => n652,
2667 
                           QN => n438, RN => n340);
2668 
   output_wip_reg_6 : DFA2 port map( C => phi1, D => input_wip(25), Q => n653,
2669 
                           QN => n440, RN => n340);
2670 
   output_wip_reg_4 : DFA2 port map( C => phi1, D => input_wip(27), Q => n654,
2671 
                           QN => n442, RN => n340);
2672 
   output_wip_reg_3 : DFA2 port map( C => phi1, D => input_wip(28), Q => n655,
2673 
                           QN => n444, RN => n340);
2674 
   output_wip_reg_15 : DFA2 port map( C => phi1, D => input_wip(16), Q => n656,
2675 
                           QN => n448, RN => n340);
2676 
   output_wip_reg_14 : DFA2 port map( C => phi1, D => input_wip(17), Q => n657,
2677 
                           QN => n450, RN => n344);
2678 
   output_wip_reg_5 : DFA2 port map( C => phi1, D => input_wip(26), Q => n658,
2679 
                           QN => n454, RN => n344);
2680 
   U168 : IN4 port map( A => n458, Q => output_fcs(24));
2681 
   U169 : IN4 port map( A => n460, Q => output_fcs(29));
2682 
   U170 : IN4 port map( A => n462, Q => output_fcs(30));
2683 
   U171 : IN4 port map( A => n464, Q => output_fcs(31));
2684 
   U172 : IN4 port map( A => n466, Q => output_fcs(15));
2685 
   U173 : IN4 port map( A => n468, Q => output_fcs(14));
2686 
   U174 : IN4 port map( A => n470, Q => output_fcs(13));
2687 
   U175 : IN4 port map( A => n472, Q => output_fcs(12));
2688 
   U176 : IN4 port map( A => n474, Q => output_fcs(11));
2689 
   output_fcs_reg_21 : DFA2 port map( C => phi1, D => input_fcs(10), Q =>
2690 
                           output_fcs(10), QN => n659, RN => n340);
2691 
   output_fcs_reg_0 : DFA2 port map( C => phi1, D => input_fcs(31), Q => n660,
2692 
                           QN => n464, RN => n344);
2693 
   output_fcs_reg_1 : DFA2 port map( C => phi1, D => input_fcs(30), Q => n661,
2694 
                           QN => n462, RN => n340);
2695 
   output_fcs_reg_2 : DFA2 port map( C => phi1, D => input_fcs(29), Q => n662,
2696 
                           QN => n460, RN => n340);
2697 
   output_fcs_reg_7 : DFA2 port map( C => phi1, D => input_fcs(24), Q => n663,
2698 
                           QN => n458, RN => n344);
2699 
   output_wip_reg_31 : DFA2 port map( C => phi1, D => input_wip(0), Q =>
2700 
                           output_wip(0), QN => n664, RN => n344);
2701 
   output_wip_reg_30 : DFA2 port map( C => phi1, D => input_wip(1), Q =>
2702 
                           output_wip(1), QN => n665, RN => n344);
2703 
   output_wip_reg_29 : DFA2 port map( C => phi1, D => input_wip(2), Q =>
2704 
                           output_wip(2), QN => n666, RN => n340);
2705 
   output_wip_reg_28 : DFA2 port map( C => phi1, D => input_wip(3), Q =>
2706 
                           output_wip(3), QN => n667, RN => n344);
2707 
   output_wip_reg_27 : DFA2 port map( C => phi1, D => input_wip(4), Q =>
2708 
                           output_wip(4), QN => n668, RN => n344);
2709 
   output_wip_reg_26 : DFA2 port map( C => phi1, D => input_wip(5), Q =>
2710 
                           output_wip(5), QN => n669, RN => n340);
2711 
   output_wip_reg_25 : DFA2 port map( C => phi1, D => input_wip(6), Q =>
2712 
                           output_wip(6), QN => n670, RN => n344);
2713 
   output_wip_reg_24 : DFA2 port map( C => phi1, D => input_wip(7), Q =>
2714 
                           output_wip(7), QN => n671, RN => n340);
2715 
   output_wip_reg_22 : DFA2 port map( C => phi1, D => input_wip(9), Q =>
2716 
                           output_wip(9), QN => n672, RN => n344);
2717 
   output_wip_reg_19 : DFA2 port map( C => phi1, D => input_wip(12), Q =>
2718 
                           output_wip(12), QN => n673, RN => n344);
2719 
   output_fcs_reg_15 : DFA2 port map( C => phi1, D => input_fcs(16), Q =>
2720 
                           output_fcs(16), QN => n674, RN => n344);
2721 
   output_fcs_reg_14 : DFA2 port map( C => phi1, D => input_fcs(17), Q =>
2722 
                           output_fcs(17), QN => n675, RN => n340);
2723 
   output_fcs_reg_13 : DFA2 port map( C => phi1, D => input_fcs(18), Q =>
2724 
                           output_fcs(18), QN => n676, RN => n340);
2725 
   output_fcs_reg_12 : DFA2 port map( C => phi1, D => input_fcs(19), Q =>
2726 
                           output_fcs(19), QN => n677, RN => n340);
2727 
   output_fcs_reg_11 : DFA2 port map( C => phi1, D => input_fcs(20), Q =>
2728 
                           output_fcs(20), QN => n678, RN => n344);
2729 
   output_fcs_reg_10 : DFA2 port map( C => phi1, D => input_fcs(21), Q =>
2730 
                           output_fcs(21), QN => n679, RN => n344);
2731 
   output_fcs_reg_9 : DFA2 port map( C => phi1, D => input_fcs(22), Q =>
2732 
                           output_fcs(22), QN => n680, RN => n344);
2733 
   output_fcs_reg_8 : DFA2 port map( C => phi1, D => input_fcs(23), Q =>
2734 
                           output_fcs(23), QN => n681, RN => n340);
2735 
   output_fcs_reg_6 : DFA2 port map( C => phi1, D => input_fcs(25), Q =>
2736 
                           output_fcs(25), QN => n682, RN => n340);
2737 
   output_fcs_reg_3 : DFA2 port map( C => phi1, D => input_fcs(28), Q =>
2738 
                           output_fcs(28), QN => n683, RN => n344);
2739 
   output_fcs_reg_17 : DFA2 port map( C => phi1, D => input_fcs(14), Q => n684,
2740 
                           QN => n468, RN => n344);
2741 
   output_fcs_reg_23 : DFA2 port map( C => phi1, D => input_fcs(8), Q =>
2742 
                           output_fcs(8), QN => n685, RN => n344);
2743 
   output_fcs_reg_16 : DFA2 port map( C => phi1, D => input_fcs(15), Q => n686,
2744 
                           QN => n466, RN => n344);
2745 
   output_fcs_reg_18 : DFA2 port map( C => phi1, D => input_fcs(13), Q => n687,
2746 
                           QN => n470, RN => n340);
2747 
   output_fcs_reg_19 : DFA2 port map( C => phi1, D => input_fcs(12), Q => n688,
2748 
                           QN => n472, RN => n340);
2749 
   output_fcs_reg_20 : DFA2 port map( C => phi1, D => input_fcs(11), Q => n689,
2750 
                           QN => n474, RN => n344);
2751 
   output_fcs_reg_22 : DFA2 port map( C => phi1, D => input_fcs(9), Q =>
2752 
                           output_fcs(9), QN => n690, RN => n344);
2753 
 
2754 
end SYN_behavior_3;
2755 
 
2756 
library IEEE;
2757 
library csx_HRDLIB;
2758 
library csx_IOLIB_3M;
2759 
 
2760 
use IEEE.std_logic_1164.all;
2761 
use IEEE.std_logic_arith.all;
2762 
use csx_HRDLIB.Vcomponents.all;
2763 
use csx_IOLIB_3M.Vcomponents.all;
2764 
 
2765 
entity gf_phi2_register_0 is
2766 
 
2767 
   port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
2768 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
2769 
         std_logic_vector (0 to 31));
2770 
 
2771 
end gf_phi2_register_0;
2772 
 
2773 
architecture SYN_behavior_0 of gf_phi2_register_0 is
2774 
 
2775 
   component DFA
2776 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2777 
   end component;
2778 
 
2779 
   component DFA2
2780 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2781 
   end component;
2782 
 
2783 
   component BU4
2784 
      port( A : in std_logic;  Q : out std_logic);
2785 
   end component;
2786 
 
2787 
   component BU2
2788 
      port( A : in std_logic;  Q : out std_logic);
2789 
   end component;
2790 
 
2791 
   component IN4
2792 
      port( A : in std_logic;  Q : out std_logic);
2793 
   end component;
2794 
 
2795 
   signal n190, n192, n194, n196, n200, n204, n208, n212, n216, n359, n360,
2796 
      n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
2797 
      n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384,
2798 
      n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
2799 
      n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
2800 
      n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
2801 
      n421, n422 : std_logic;
2802 
 
2803 
begin
2804 
 
2805 
   output_wip_reg_30 : DFA port map( C => phi2, D => input_wip(1), Q =>
2806 
                           output_wip(1), QN => n359, RN => n192);
2807 
   output_wip_reg_29 : DFA port map( C => phi2, D => input_wip(2), Q =>
2808 
                           output_wip(2), QN => n360, RN => n192);
2809 
   output_wip_reg_27 : DFA port map( C => phi2, D => input_wip(4), Q =>
2810 
                           output_wip(4), QN => n361, RN => n192);
2811 
   output_wip_reg_25 : DFA port map( C => phi2, D => input_wip(6), Q =>
2812 
                           output_wip(6), QN => n362, RN => n194);
2813 
   output_wip_reg_24 : DFA port map( C => phi2, D => input_wip(7), Q =>
2814 
                           output_wip(7), QN => n363, RN => n192);
2815 
   output_wip_reg_22 : DFA port map( C => phi2, D => input_wip(9), Q =>
2816 
                           output_wip(9), QN => n364, RN => n194);
2817 
   output_wip_reg_19 : DFA port map( C => phi2, D => input_wip(12), Q =>
2818 
                           output_wip(12), QN => n365, RN => n192);
2819 
   output_wip_reg_17 : DFA port map( C => phi2, D => input_wip(14), Q =>
2820 
                           output_wip(14), QN => n366, RN => n190);
2821 
   output_wip_reg_3 : DFA port map( C => phi2, D => input_wip(28), Q =>
2822 
                           output_wip(28), QN => n367, RN => n192);
2823 
   output_wip_reg_15 : DFA port map( C => phi2, D => input_wip(16), Q =>
2824 
                           output_wip(16), QN => n368, RN => n190);
2825 
   output_wip_reg_13 : DFA port map( C => phi2, D => input_wip(18), Q =>
2826 
                           output_wip(18), QN => n369, RN => n190);
2827 
   output_wip_reg_12 : DFA port map( C => phi2, D => input_wip(19), Q =>
2828 
                           output_wip(19), QN => n370, RN => n190);
2829 
   output_wip_reg_6 : DFA port map( C => phi2, D => input_wip(25), Q =>
2830 
                           output_wip(25), QN => n371, RN => n194);
2831 
   output_wip_reg_23 : DFA port map( C => phi2, D => input_wip(8), Q =>
2832 
                           output_wip(8), QN => n372, RN => n194);
2833 
   output_wip_reg_18 : DFA port map( C => phi2, D => input_wip(13), Q =>
2834 
                           output_wip(13), QN => n373, RN => n194);
2835 
   output_wip_reg_16 : DFA port map( C => phi2, D => input_wip(15), Q =>
2836 
                           output_wip(15), QN => n374, RN => n192);
2837 
   output_wip_reg_14 : DFA port map( C => phi2, D => input_wip(17), Q =>
2838 
                           output_wip(17), QN => n375, RN => n194);
2839 
   output_wip_reg_11 : DFA port map( C => phi2, D => input_wip(20), Q =>
2840 
                           output_wip(20), QN => n376, RN => n194);
2841 
   output_wip_reg_10 : DFA port map( C => phi2, D => input_wip(21), Q =>
2842 
                           output_wip(21), QN => n377, RN => n194);
2843 
   output_wip_reg_9 : DFA port map( C => phi2, D => input_wip(22), Q =>
2844 
                           output_wip(22), QN => n378, RN => n194);
2845 
   output_wip_reg_8 : DFA port map( C => phi2, D => input_wip(23), Q =>
2846 
                           output_wip(23), QN => n379, RN => n192);
2847 
   output_wip_reg_7 : DFA port map( C => phi2, D => input_wip(24), Q =>
2848 
                           output_wip(24), QN => n380, RN => n194);
2849 
   output_wip_reg_5 : DFA port map( C => phi2, D => input_wip(26), Q =>
2850 
                           output_wip(26), QN => n381, RN => n192);
2851 
   output_wip_reg_4 : DFA port map( C => phi2, D => input_wip(27), Q =>
2852 
                           output_wip(27), QN => n382, RN => n194);
2853 
   output_wip_reg_2 : DFA port map( C => phi2, D => input_wip(29), Q =>
2854 
                           output_wip(29), QN => n383, RN => n192);
2855 
   output_wip_reg_1 : DFA port map( C => phi2, D => input_wip(30), Q =>
2856 
                           output_wip(30), QN => n384, RN => n194);
2857 
   output_fcs_reg_31 : DFA2 port map( C => phi2, D => input_fcs(0), Q =>
2858 
                           output_fcs(0), QN => n385, RN => n192);
2859 
   output_fcs_reg_30 : DFA2 port map( C => phi2, D => input_fcs(1), Q =>
2860 
                           output_fcs(1), QN => n386, RN => n194);
2861 
   output_fcs_reg_29 : DFA2 port map( C => phi2, D => input_fcs(2), Q =>
2862 
                           output_fcs(2), QN => n387, RN => n194);
2863 
   output_fcs_reg_28 : DFA2 port map( C => phi2, D => input_fcs(3), Q =>
2864 
                           output_fcs(3), QN => n388, RN => n190);
2865 
   output_fcs_reg_27 : DFA2 port map( C => phi2, D => input_fcs(4), Q =>
2866 
                           output_fcs(4), QN => n389, RN => n194);
2867 
   output_fcs_reg_26 : DFA2 port map( C => phi2, D => input_fcs(5), Q =>
2868 
                           output_fcs(5), QN => n390, RN => n194);
2869 
   output_fcs_reg_7 : DFA port map( C => phi2, D => input_fcs(24), Q =>
2870 
                           output_fcs(24), QN => n391, RN => n194);
2871 
   output_fcs_reg_2 : DFA port map( C => phi2, D => input_fcs(29), Q =>
2872 
                           output_fcs(29), QN => n392, RN => n194);
2873 
   output_fcs_reg_1 : DFA port map( C => phi2, D => input_fcs(30), Q =>
2874 
                           output_fcs(30), QN => n393, RN => n194);
2875 
   output_fcs_reg_0 : DFA port map( C => phi2, D => input_fcs(31), Q =>
2876 
                           output_fcs(31), QN => n394, RN => n194);
2877 
   U147 : BU4 port map( A => n190, Q => n194);
2878 
   U148 : BU4 port map( A => n190, Q => n192);
2879 
   U149 : BU2 port map( A => reset, Q => n190);
2880 
   U150 : IN4 port map( A => n196, Q => output_fcs(13));
2881 
   U151 : IN4 port map( A => n200, Q => output_fcs(15));
2882 
   output_fcs_reg_24 : DFA port map( C => phi2, D => input_fcs(7), Q =>
2883 
                           output_fcs(7), QN => n395, RN => n192);
2884 
   output_wip_reg_0 : DFA port map( C => phi2, D => input_wip(31), Q =>
2885 
                           output_wip(31), QN => n396, RN => n194);
2886 
   output_fcs_reg_17 : DFA2 port map( C => phi2, D => input_fcs(14), Q =>
2887 
                           output_fcs(14), QN => n397, RN => n194);
2888 
   U152 : IN4 port map( A => n204, Q => output_fcs(12));
2889 
   U153 : IN4 port map( A => n208, Q => output_fcs(9));
2890 
   U154 : IN4 port map( A => n212, Q => output_fcs(11));
2891 
   U155 : IN4 port map( A => n216, Q => output_fcs(10));
2892 
   output_fcs_reg_25 : DFA2 port map( C => phi2, D => input_fcs(6), Q =>
2893 
                           output_fcs(6), QN => n398, RN => n190);
2894 
   output_wip_reg_21 : DFA port map( C => phi2, D => input_wip(10), Q =>
2895 
                           output_wip(10), QN => n399, RN => n194);
2896 
   output_wip_reg_20 : DFA port map( C => phi2, D => input_wip(11), Q =>
2897 
                           output_wip(11), QN => n400, RN => n192);
2898 
   output_fcs_reg_5 : DFA port map( C => phi2, D => input_fcs(26), Q =>
2899 
                           output_fcs(26), QN => n401, RN => n194);
2900 
   output_fcs_reg_4 : DFA port map( C => phi2, D => input_fcs(27), Q =>
2901 
                           output_fcs(27), QN => n402, RN => n192);
2902 
   output_wip_reg_31 : DFA2 port map( C => phi2, D => input_wip(0), Q =>
2903 
                           output_wip(0), QN => n403, RN => n190);
2904 
   output_wip_reg_28 : DFA2 port map( C => phi2, D => input_wip(3), Q =>
2905 
                           output_wip(3), QN => n404, RN => n194);
2906 
   output_wip_reg_26 : DFA2 port map( C => phi2, D => input_wip(5), Q =>
2907 
                           output_wip(5), QN => n405, RN => n194);
2908 
   output_fcs_reg_23 : DFA2 port map( C => phi2, D => input_fcs(8), Q =>
2909 
                           output_fcs(8), QN => n406, RN => n192);
2910 
   output_fcs_reg_3 : DFA2 port map( C => phi2, D => input_fcs(28), Q =>
2911 
                           output_fcs(28), QN => n407, RN => n194);
2912 
   output_fcs_reg_6 : DFA2 port map( C => phi2, D => input_fcs(25), Q =>
2913 
                           output_fcs(25), QN => n408, RN => n194);
2914 
   output_fcs_reg_8 : DFA2 port map( C => phi2, D => input_fcs(23), Q =>
2915 
                           output_fcs(23), QN => n409, RN => n192);
2916 
   output_fcs_reg_9 : DFA2 port map( C => phi2, D => input_fcs(22), Q =>
2917 
                           output_fcs(22), QN => n410, RN => n190);
2918 
   output_fcs_reg_10 : DFA2 port map( C => phi2, D => input_fcs(21), Q =>
2919 
                           output_fcs(21), QN => n411, RN => n192);
2920 
   output_fcs_reg_11 : DFA2 port map( C => phi2, D => input_fcs(20), Q =>
2921 
                           output_fcs(20), QN => n412, RN => n192);
2922 
   output_fcs_reg_12 : DFA2 port map( C => phi2, D => input_fcs(19), Q =>
2923 
                           output_fcs(19), QN => n413, RN => n192);
2924 
   output_fcs_reg_13 : DFA2 port map( C => phi2, D => input_fcs(18), Q =>
2925 
                           output_fcs(18), QN => n414, RN => n192);
2926 
   output_fcs_reg_14 : DFA2 port map( C => phi2, D => input_fcs(17), Q =>
2927 
                           output_fcs(17), QN => n415, RN => n192);
2928 
   output_fcs_reg_15 : DFA2 port map( C => phi2, D => input_fcs(16), Q =>
2929 
                           output_fcs(16), QN => n416, RN => n192);
2930 
   output_fcs_reg_16 : DFA2 port map( C => phi2, D => input_fcs(15), Q => n417,
2931 
                           QN => n200, RN => n192);
2932 
   output_fcs_reg_18 : DFA2 port map( C => phi2, D => input_fcs(13), Q => n418,
2933 
                           QN => n196, RN => n190);
2934 
   output_fcs_reg_19 : DFA2 port map( C => phi2, D => input_fcs(12), Q => n419,
2935 
                           QN => n204, RN => n192);
2936 
   output_fcs_reg_20 : DFA2 port map( C => phi2, D => input_fcs(11), Q => n420,
2937 
                           QN => n212, RN => n192);
2938 
   output_fcs_reg_22 : DFA2 port map( C => phi2, D => input_fcs(9), Q => n421,
2939 
                           QN => n208, RN => n192);
2940 
   output_fcs_reg_21 : DFA2 port map( C => phi2, D => input_fcs(10), Q => n422,
2941 
                           QN => n216, RN => n192);
2942 
 
2943 
end SYN_behavior_0;
2944 
 
2945 
library IEEE;
2946 
library csx_HRDLIB;
2947 
library csx_IOLIB_3M;
2948 
 
2949 
use IEEE.std_logic_1164.all;
2950 
use IEEE.std_logic_arith.all;
2951 
use csx_HRDLIB.Vcomponents.all;
2952 
use csx_IOLIB_3M.Vcomponents.all;
2953 
 
2954 
entity gf_phi2_register_1 is
2955 
 
2956 
   port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
2957 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
2958 
         std_logic_vector (0 to 31));
2959 
 
2960 
end gf_phi2_register_1;
2961 
 
2962 
architecture SYN_behavior_1 of gf_phi2_register_1 is
2963 
 
2964 
   component DFA
2965 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2966 
   end component;
2967 
 
2968 
   component BU4
2969 
      port( A : in std_logic;  Q : out std_logic);
2970 
   end component;
2971 
 
2972 
   component BU2
2973 
      port( A : in std_logic;  Q : out std_logic);
2974 
   end component;
2975 
 
2976 
   component IN4
2977 
      port( A : in std_logic;  Q : out std_logic);
2978 
   end component;
2979 
 
2980 
   component DFA2
2981 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
2982 
   end component;
2983 
 
2984 
   signal n198, n202, n206, n210, n218, n234, n238, n242, n246, n250, n395,
2985 
      n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407,
2986 
      n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419,
2987 
      n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431,
2988 
      n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443,
2989 
      n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455,
2990 
      n456, n457, n458 : std_logic;
2991 
 
2992 
begin
2993 
 
2994 
   output_fcs_reg_27 : DFA port map( C => phi2, D => input_fcs(4), Q =>
2995 
                           output_fcs(4), QN => n395, RN => n202);
2996 
   output_wip_reg_24 : DFA port map( C => phi2, D => input_wip(7), Q =>
2997 
                           output_wip(7), QN => n396, RN => n202);
2998 
   output_wip_reg_29 : DFA port map( C => phi2, D => input_wip(2), Q =>
2999 
                           output_wip(2), QN => n397, RN => n202);
3000 
   output_wip_reg_28 : DFA port map( C => phi2, D => input_wip(3), Q =>
3001 
                           output_wip(3), QN => n398, RN => n202);
3002 
   output_wip_reg_22 : DFA port map( C => phi2, D => input_wip(9), Q =>
3003 
                           output_wip(9), QN => n399, RN => n202);
3004 
   output_wip_reg_18 : DFA port map( C => phi2, D => input_wip(13), Q =>
3005 
                           output_wip(13), QN => n400, RN => n202);
3006 
   output_wip_reg_14 : DFA port map( C => phi2, D => input_wip(17), Q =>
3007 
                           output_wip(17), QN => n401, RN => n202);
3008 
   output_wip_reg_12 : DFA port map( C => phi2, D => input_wip(19), Q =>
3009 
                           output_wip(19), QN => n402, RN => n202);
3010 
   output_wip_reg_9 : DFA port map( C => phi2, D => input_wip(22), Q =>
3011 
                           output_wip(22), QN => n403, RN => n202);
3012 
   output_wip_reg_7 : DFA port map( C => phi2, D => input_wip(24), Q =>
3013 
                           output_wip(24), QN => n404, RN => n202);
3014 
   output_wip_reg_5 : DFA port map( C => phi2, D => input_wip(26), Q =>
3015 
                           output_wip(26), QN => n405, RN => n206);
3016 
   output_wip_reg_4 : DFA port map( C => phi2, D => input_wip(27), Q =>
3017 
                           output_wip(27), QN => n406, RN => n202);
3018 
   output_wip_reg_3 : DFA port map( C => phi2, D => input_wip(28), Q =>
3019 
                           output_wip(28), QN => n407, RN => n206);
3020 
   output_wip_reg_1 : DFA port map( C => phi2, D => input_wip(30), Q =>
3021 
                           output_wip(30), QN => n408, RN => n202);
3022 
   output_wip_reg_0 : DFA port map( C => phi2, D => input_wip(31), Q =>
3023 
                           output_wip(31), QN => n409, RN => n206);
3024 
   output_wip_reg_27 : DFA port map( C => phi2, D => input_wip(4), Q =>
3025 
                           output_wip(4), QN => n410, RN => n206);
3026 
   output_wip_reg_26 : DFA port map( C => phi2, D => input_wip(5), Q =>
3027 
                           output_wip(5), QN => n411, RN => n202);
3028 
   output_wip_reg_25 : DFA port map( C => phi2, D => input_wip(6), Q =>
3029 
                           output_wip(6), QN => n412, RN => n206);
3030 
   output_wip_reg_20 : DFA port map( C => phi2, D => input_wip(11), Q =>
3031 
                           output_wip(11), QN => n413, RN => n202);
3032 
   output_fcs_reg_31 : DFA port map( C => phi2, D => input_fcs(0), Q =>
3033 
                           output_fcs(0), QN => n414, RN => n202);
3034 
   output_fcs_reg_17 : DFA port map( C => phi2, D => input_fcs(14), Q =>
3035 
                           output_fcs(14), QN => n415, RN => n202);
3036 
   output_fcs_reg_16 : DFA port map( C => phi2, D => input_fcs(15), Q =>
3037 
                           output_fcs(15), QN => n416, RN => n202);
3038 
   output_fcs_reg_15 : DFA port map( C => phi2, D => input_fcs(16), Q =>
3039 
                           output_fcs(16), QN => n417, RN => n202);
3040 
   output_fcs_reg_14 : DFA port map( C => phi2, D => input_fcs(17), Q =>
3041 
                           output_fcs(17), QN => n418, RN => n198);
3042 
   output_fcs_reg_13 : DFA port map( C => phi2, D => input_fcs(18), Q =>
3043 
                           output_fcs(18), QN => n419, RN => n206);
3044 
   output_fcs_reg_12 : DFA port map( C => phi2, D => input_fcs(19), Q =>
3045 
                           output_fcs(19), QN => n420, RN => n206);
3046 
   output_fcs_reg_11 : DFA port map( C => phi2, D => input_fcs(20), Q =>
3047 
                           output_fcs(20), QN => n421, RN => n206);
3048 
   output_fcs_reg_10 : DFA port map( C => phi2, D => input_fcs(21), Q =>
3049 
                           output_fcs(21), QN => n422, RN => n206);
3050 
   output_fcs_reg_9 : DFA port map( C => phi2, D => input_fcs(22), Q =>
3051 
                           output_fcs(22), QN => n423, RN => n206);
3052 
   output_fcs_reg_8 : DFA port map( C => phi2, D => input_fcs(23), Q =>
3053 
                           output_fcs(23), QN => n424, RN => n206);
3054 
   output_fcs_reg_7 : DFA port map( C => phi2, D => input_fcs(24), Q =>
3055 
                           output_fcs(24), QN => n425, RN => n206);
3056 
   output_fcs_reg_6 : DFA port map( C => phi2, D => input_fcs(25), Q =>
3057 
                           output_fcs(25), QN => n426, RN => n198);
3058 
   output_fcs_reg_5 : DFA port map( C => phi2, D => input_fcs(26), Q =>
3059 
                           output_fcs(26), QN => n427, RN => n206);
3060 
   output_fcs_reg_4 : DFA port map( C => phi2, D => input_fcs(27), Q =>
3061 
                           output_fcs(27), QN => n428, RN => n206);
3062 
   output_fcs_reg_3 : DFA port map( C => phi2, D => input_fcs(28), Q =>
3063 
                           output_fcs(28), QN => n429, RN => n206);
3064 
   output_fcs_reg_2 : DFA port map( C => phi2, D => input_fcs(29), Q =>
3065 
                           output_fcs(29), QN => n430, RN => n198);
3066 
   output_fcs_reg_1 : DFA port map( C => phi2, D => input_fcs(30), Q =>
3067 
                           output_fcs(30), QN => n431, RN => n206);
3068 
   output_fcs_reg_0 : DFA port map( C => phi2, D => input_fcs(31), Q =>
3069 
                           output_fcs(31), QN => n432, RN => n206);
3070 
   U147 : BU4 port map( A => n198, Q => n206);
3071 
   U148 : BU4 port map( A => n198, Q => n202);
3072 
   output_wip_reg_15 : DFA port map( C => phi2, D => input_wip(16), Q =>
3073 
                           output_wip(16), QN => n433, RN => n198);
3074 
   output_wip_reg_10 : DFA port map( C => phi2, D => input_wip(21), Q =>
3075 
                           output_wip(21), QN => n434, RN => n198);
3076 
   output_wip_reg_2 : DFA port map( C => phi2, D => input_wip(29), Q =>
3077 
                           output_wip(29), QN => n435, RN => n198);
3078 
   output_wip_reg_21 : DFA port map( C => phi2, D => input_wip(10), Q =>
3079 
                           output_wip(10), QN => n436, RN => n198);
3080 
   output_wip_reg_31 : DFA port map( C => phi2, D => input_wip(0), Q =>
3081 
                           output_wip(0), QN => n437, RN => n198);
3082 
   output_fcs_reg_30 : DFA port map( C => phi2, D => input_fcs(1), Q =>
3083 
                           output_fcs(1), QN => n438, RN => n206);
3084 
   U149 : BU2 port map( A => reset, Q => n198);
3085 
   U150 : IN4 port map( A => n210, Q => output_fcs(11));
3086 
   U151 : IN4 port map( A => n218, Q => output_fcs(12));
3087 
   output_fcs_reg_28 : DFA port map( C => phi2, D => input_fcs(3), Q =>
3088 
                           output_fcs(3), QN => n439, RN => n206);
3089 
   output_fcs_reg_26 : DFA port map( C => phi2, D => input_fcs(5), Q =>
3090 
                           output_fcs(5), QN => n440, RN => n202);
3091 
   U152 : IN4 port map( A => n242, Q => output_fcs(8));
3092 
   U153 : IN4 port map( A => n246, Q => output_fcs(7));
3093 
   U154 : IN4 port map( A => n250, Q => output_fcs(6));
3094 
   U155 : IN4 port map( A => n234, Q => output_fcs(10));
3095 
   U156 : IN4 port map( A => n238, Q => output_fcs(9));
3096 
   output_fcs_reg_29 : DFA2 port map( C => phi2, D => input_fcs(2), Q =>
3097 
                           output_fcs(2), QN => n441, RN => n202);
3098 
   output_fcs_reg_18 : DFA2 port map( C => phi2, D => input_fcs(13), Q =>
3099 
                           output_fcs(13), QN => n442, RN => n202);
3100 
   output_wip_reg_30 : DFA2 port map( C => phi2, D => input_wip(1), Q =>
3101 
                           output_wip(1), QN => n443, RN => n206);
3102 
   output_wip_reg_23 : DFA2 port map( C => phi2, D => input_wip(8), Q =>
3103 
                           output_wip(8), QN => n444, RN => n206);
3104 
   output_wip_reg_19 : DFA2 port map( C => phi2, D => input_wip(12), Q =>
3105 
                           output_wip(12), QN => n445, RN => n206);
3106 
   output_wip_reg_17 : DFA2 port map( C => phi2, D => input_wip(14), Q =>
3107 
                           output_wip(14), QN => n446, RN => n206);
3108 
   output_wip_reg_16 : DFA2 port map( C => phi2, D => input_wip(15), Q =>
3109 
                           output_wip(15), QN => n447, RN => n206);
3110 
   output_wip_reg_13 : DFA2 port map( C => phi2, D => input_wip(18), Q =>
3111 
                           output_wip(18), QN => n448, RN => n206);
3112 
   output_wip_reg_11 : DFA2 port map( C => phi2, D => input_wip(20), Q =>
3113 
                           output_wip(20), QN => n449, RN => n206);
3114 
   output_wip_reg_8 : DFA2 port map( C => phi2, D => input_wip(23), Q =>
3115 
                           output_wip(23), QN => n450, RN => n206);
3116 
   output_wip_reg_6 : DFA2 port map( C => phi2, D => input_wip(25), Q =>
3117 
                           output_wip(25), QN => n451, RN => n206);
3118 
   output_fcs_reg_19 : DFA2 port map( C => phi2, D => input_fcs(12), Q => n452,
3119 
                           QN => n218, RN => n202);
3120 
   output_fcs_reg_20 : DFA2 port map( C => phi2, D => input_fcs(11), Q => n453,
3121 
                           QN => n210, RN => n202);
3122 
   output_fcs_reg_21 : DFA2 port map( C => phi2, D => input_fcs(10), Q => n454,
3123 
                           QN => n234, RN => n202);
3124 
   output_fcs_reg_22 : DFA2 port map( C => phi2, D => input_fcs(9), Q => n455,
3125 
                           QN => n238, RN => n198);
3126 
   output_fcs_reg_23 : DFA2 port map( C => phi2, D => input_fcs(8), Q => n456,
3127 
                           QN => n242, RN => n202);
3128 
   output_fcs_reg_24 : DFA2 port map( C => phi2, D => input_fcs(7), Q => n457,
3129 
                           QN => n246, RN => n202);
3130 
   output_fcs_reg_25 : DFA2 port map( C => phi2, D => input_fcs(6), Q => n458,
3131 
                           QN => n250, RN => n202);
3132 
 
3133 
end SYN_behavior_1;
3134 
 
3135 
library IEEE;
3136 
library csx_HRDLIB;
3137 
library csx_IOLIB_3M;
3138 
 
3139 
use IEEE.std_logic_1164.all;
3140 
use IEEE.std_logic_arith.all;
3141 
use csx_HRDLIB.Vcomponents.all;
3142 
use csx_IOLIB_3M.Vcomponents.all;
3143 
 
3144 
entity gf_phi2_register_2 is
3145 
 
3146 
   port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
3147 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
3148 
         std_logic_vector (0 to 31));
3149 
 
3150 
end gf_phi2_register_2;
3151 
 
3152 
architecture SYN_behavior_2 of gf_phi2_register_2 is
3153 
 
3154 
   component DFA
3155 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
3156 
   end component;
3157 
 
3158 
   component DFA2
3159 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
3160 
   end component;
3161 
 
3162 
   component BU8
3163 
      port( A : in std_logic;  Q : out std_logic);
3164 
   end component;
3165 
 
3166 
   component BU4
3167 
      port( A : in std_logic;  Q : out std_logic);
3168 
   end component;
3169 
 
3170 
   signal n240, n248, n377, n378, n379, n380, n381, n382, n383, n384, n385,
3171 
      n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
3172 
      n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
3173 
      n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421,
3174 
      n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433,
3175 
      n434, n435, n436, n437, n438, n439, n440 : std_logic;
3176 
 
3177 
begin
3178 
 
3179 
   output_fcs_reg_16 : DFA port map( C => phi2, D => input_fcs(15), Q =>
3180 
                           output_fcs(15), QN => n377, RN => n240);
3181 
   output_wip_reg_12 : DFA port map( C => phi2, D => input_wip(19), Q =>
3182 
                           output_wip(19), QN => n378, RN => n248);
3183 
   output_fcs_reg_31 : DFA2 port map( C => phi2, D => input_fcs(0), Q =>
3184 
                           output_fcs(0), QN => n379, RN => n248);
3185 
   output_fcs_reg_30 : DFA2 port map( C => phi2, D => input_fcs(1), Q =>
3186 
                           output_fcs(1), QN => n380, RN => n248);
3187 
   output_fcs_reg_29 : DFA2 port map( C => phi2, D => input_fcs(2), Q =>
3188 
                           output_fcs(2), QN => n381, RN => n240);
3189 
   output_fcs_reg_28 : DFA2 port map( C => phi2, D => input_fcs(3), Q =>
3190 
                           output_fcs(3), QN => n382, RN => n240);
3191 
   output_fcs_reg_27 : DFA2 port map( C => phi2, D => input_fcs(4), Q =>
3192 
                           output_fcs(4), QN => n383, RN => n240);
3193 
   output_fcs_reg_26 : DFA2 port map( C => phi2, D => input_fcs(5), Q =>
3194 
                           output_fcs(5), QN => n384, RN => n248);
3195 
   output_fcs_reg_25 : DFA2 port map( C => phi2, D => input_fcs(6), Q =>
3196 
                           output_fcs(6), QN => n385, RN => n240);
3197 
   output_fcs_reg_24 : DFA2 port map( C => phi2, D => input_fcs(7), Q =>
3198 
                           output_fcs(7), QN => n386, RN => n240);
3199 
   output_fcs_reg_23 : DFA2 port map( C => phi2, D => input_fcs(8), Q =>
3200 
                           output_fcs(8), QN => n387, RN => n248);
3201 
   output_fcs_reg_22 : DFA2 port map( C => phi2, D => input_fcs(9), Q =>
3202 
                           output_fcs(9), QN => n388, RN => n248);
3203 
   output_fcs_reg_21 : DFA2 port map( C => phi2, D => input_fcs(10), Q =>
3204 
                           output_fcs(10), QN => n389, RN => n248);
3205 
   output_fcs_reg_20 : DFA2 port map( C => phi2, D => input_fcs(11), Q =>
3206 
                           output_fcs(11), QN => n390, RN => n240);
3207 
   output_fcs_reg_15 : DFA2 port map( C => phi2, D => input_fcs(16), Q =>
3208 
                           output_fcs(16), QN => n391, RN => n240);
3209 
   output_fcs_reg_14 : DFA2 port map( C => phi2, D => input_fcs(17), Q =>
3210 
                           output_fcs(17), QN => n392, RN => n248);
3211 
   output_fcs_reg_13 : DFA2 port map( C => phi2, D => input_fcs(18), Q =>
3212 
                           output_fcs(18), QN => n393, RN => n248);
3213 
   output_fcs_reg_12 : DFA2 port map( C => phi2, D => input_fcs(19), Q =>
3214 
                           output_fcs(19), QN => n394, RN => n240);
3215 
   output_fcs_reg_11 : DFA2 port map( C => phi2, D => input_fcs(20), Q =>
3216 
                           output_fcs(20), QN => n395, RN => n248);
3217 
   output_fcs_reg_10 : DFA2 port map( C => phi2, D => input_fcs(21), Q =>
3218 
                           output_fcs(21), QN => n396, RN => n248);
3219 
   output_fcs_reg_9 : DFA2 port map( C => phi2, D => input_fcs(22), Q =>
3220 
                           output_fcs(22), QN => n397, RN => n248);
3221 
   output_fcs_reg_8 : DFA2 port map( C => phi2, D => input_fcs(23), Q =>
3222 
                           output_fcs(23), QN => n398, RN => n240);
3223 
   output_fcs_reg_7 : DFA2 port map( C => phi2, D => input_fcs(24), Q =>
3224 
                           output_fcs(24), QN => n399, RN => n240);
3225 
   output_fcs_reg_6 : DFA2 port map( C => phi2, D => input_fcs(25), Q =>
3226 
                           output_fcs(25), QN => n400, RN => n248);
3227 
   output_fcs_reg_5 : DFA2 port map( C => phi2, D => input_fcs(26), Q =>
3228 
                           output_fcs(26), QN => n401, RN => n240);
3229 
   output_fcs_reg_4 : DFA2 port map( C => phi2, D => input_fcs(27), Q =>
3230 
                           output_fcs(27), QN => n402, RN => n240);
3231 
   output_fcs_reg_3 : DFA2 port map( C => phi2, D => input_fcs(28), Q =>
3232 
                           output_fcs(28), QN => n403, RN => n240);
3233 
   output_fcs_reg_2 : DFA2 port map( C => phi2, D => input_fcs(29), Q =>
3234 
                           output_fcs(29), QN => n404, RN => n248);
3235 
   output_fcs_reg_1 : DFA2 port map( C => phi2, D => input_fcs(30), Q =>
3236 
                           output_fcs(30), QN => n405, RN => n248);
3237 
   output_fcs_reg_0 : DFA2 port map( C => phi2, D => input_fcs(31), Q =>
3238 
                           output_fcs(31), QN => n406, RN => n248);
3239 
   output_wip_reg_31 : DFA port map( C => phi2, D => input_wip(0), Q =>
3240 
                           output_wip(0), QN => n407, RN => n240);
3241 
   output_wip_reg_30 : DFA port map( C => phi2, D => input_wip(1), Q =>
3242 
                           output_wip(1), QN => n408, RN => n240);
3243 
   output_wip_reg_29 : DFA port map( C => phi2, D => input_wip(2), Q =>
3244 
                           output_wip(2), QN => n409, RN => n240);
3245 
   output_wip_reg_28 : DFA port map( C => phi2, D => input_wip(3), Q =>
3246 
                           output_wip(3), QN => n410, RN => n240);
3247 
   output_wip_reg_27 : DFA port map( C => phi2, D => input_wip(4), Q =>
3248 
                           output_wip(4), QN => n411, RN => n240);
3249 
   output_wip_reg_26 : DFA port map( C => phi2, D => input_wip(5), Q =>
3250 
                           output_wip(5), QN => n412, RN => n240);
3251 
   output_wip_reg_25 : DFA port map( C => phi2, D => input_wip(6), Q =>
3252 
                           output_wip(6), QN => n413, RN => n240);
3253 
   output_wip_reg_24 : DFA port map( C => phi2, D => input_wip(7), Q =>
3254 
                           output_wip(7), QN => n414, RN => n240);
3255 
   output_wip_reg_23 : DFA port map( C => phi2, D => input_wip(8), Q =>
3256 
                           output_wip(8), QN => n415, RN => n240);
3257 
   output_wip_reg_22 : DFA port map( C => phi2, D => input_wip(9), Q =>
3258 
                           output_wip(9), QN => n416, RN => n240);
3259 
   output_wip_reg_21 : DFA port map( C => phi2, D => input_wip(10), Q =>
3260 
                           output_wip(10), QN => n417, RN => n240);
3261 
   output_wip_reg_20 : DFA port map( C => phi2, D => input_wip(11), Q =>
3262 
                           output_wip(11), QN => n418, RN => n240);
3263 
   output_wip_reg_19 : DFA port map( C => phi2, D => input_wip(12), Q =>
3264 
                           output_wip(12), QN => n419, RN => n240);
3265 
   output_wip_reg_18 : DFA port map( C => phi2, D => input_wip(13), Q =>
3266 
                           output_wip(13), QN => n420, RN => n240);
3267 
   output_wip_reg_17 : DFA port map( C => phi2, D => input_wip(14), Q =>
3268 
                           output_wip(14), QN => n421, RN => n240);
3269 
   output_wip_reg_16 : DFA port map( C => phi2, D => input_wip(15), Q =>
3270 
                           output_wip(15), QN => n422, RN => n240);
3271 
   output_wip_reg_15 : DFA port map( C => phi2, D => input_wip(16), Q =>
3272 
                           output_wip(16), QN => n423, RN => n240);
3273 
   output_wip_reg_11 : DFA port map( C => phi2, D => input_wip(20), Q =>
3274 
                           output_wip(20), QN => n424, RN => n240);
3275 
   output_wip_reg_10 : DFA port map( C => phi2, D => input_wip(21), Q =>
3276 
                           output_wip(21), QN => n425, RN => n240);
3277 
   output_wip_reg_9 : DFA port map( C => phi2, D => input_wip(22), Q =>
3278 
                           output_wip(22), QN => n426, RN => n240);
3279 
   output_wip_reg_8 : DFA port map( C => phi2, D => input_wip(23), Q =>
3280 
                           output_wip(23), QN => n427, RN => n240);
3281 
   output_wip_reg_7 : DFA port map( C => phi2, D => input_wip(24), Q =>
3282 
                           output_wip(24), QN => n428, RN => n240);
3283 
   output_wip_reg_1 : DFA port map( C => phi2, D => input_wip(30), Q =>
3284 
                           output_wip(30), QN => n429, RN => n240);
3285 
   output_wip_reg_0 : DFA port map( C => phi2, D => input_wip(31), Q =>
3286 
                           output_wip(31), QN => n430, RN => n240);
3287 
   U147 : BU8 port map( A => reset, Q => n240);
3288 
   U148 : BU4 port map( A => n240, Q => n248);
3289 
   output_wip_reg_4 : DFA port map( C => phi2, D => input_wip(27), Q =>
3290 
                           output_wip(27), QN => n431, RN => n240);
3291 
   output_wip_reg_2 : DFA port map( C => phi2, D => input_wip(29), Q =>
3292 
                           output_wip(29), QN => n432, RN => n240);
3293 
   output_wip_reg_5 : DFA port map( C => phi2, D => input_wip(26), Q =>
3294 
                           output_wip(26), QN => n433, RN => n240);
3295 
   output_wip_reg_14 : DFA port map( C => phi2, D => input_wip(17), Q =>
3296 
                           output_wip(17), QN => n434, RN => n240);
3297 
   output_wip_reg_13 : DFA port map( C => phi2, D => input_wip(18), Q =>
3298 
                           output_wip(18), QN => n435, RN => n240);
3299 
   output_wip_reg_3 : DFA port map( C => phi2, D => input_wip(28), Q =>
3300 
                           output_wip(28), QN => n436, RN => n240);
3301 
   output_wip_reg_6 : DFA port map( C => phi2, D => input_wip(25), Q =>
3302 
                           output_wip(25), QN => n437, RN => n240);
3303 
   output_fcs_reg_18 : DFA2 port map( C => phi2, D => input_fcs(13), Q =>
3304 
                           output_fcs(13), QN => n438, RN => n240);
3305 
   output_fcs_reg_19 : DFA2 port map( C => phi2, D => input_fcs(12), Q =>
3306 
                           output_fcs(12), QN => n439, RN => n248);
3307 
   output_fcs_reg_17 : DFA2 port map( C => phi2, D => input_fcs(14), Q =>
3308 
                           output_fcs(14), QN => n440, RN => n240);
3309 
 
3310 
end SYN_behavior_2;
3311 
 
3312 
library IEEE;
3313 
library csx_HRDLIB;
3314 
library csx_IOLIB_3M;
3315 
 
3316 
use IEEE.std_logic_1164.all;
3317 
use IEEE.std_logic_arith.all;
3318 
use csx_HRDLIB.Vcomponents.all;
3319 
use csx_IOLIB_3M.Vcomponents.all;
3320 
 
3321 
entity gf_phi2_register_3 is
3322 
 
3323 
   port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
3324 
         std_logic_vector (0 to 31);  output_wip, output_fcs : out
3325 
         std_logic_vector (0 to 31));
3326 
 
3327 
end gf_phi2_register_3;
3328 
 
3329 
architecture SYN_behavior_3 of gf_phi2_register_3 is
3330 
 
3331 
   component DFA
3332 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
3333 
   end component;
3334 
 
3335 
   component DFA2
3336 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
3337 
   end component;
3338 
 
3339 
   component BU4
3340 
      port( A : in std_logic;  Q : out std_logic);
3341 
   end component;
3342 
 
3343 
   component BU2
3344 
      port( A : in std_logic;  Q : out std_logic);
3345 
   end component;
3346 
 
3347 
   component IN4
3348 
      port( A : in std_logic;  Q : out std_logic);
3349 
   end component;
3350 
 
3351 
   signal n268, n272, n314, n316, n320, n324, n328, n467, n468, n469, n470,
3352 
      n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
3353 
      n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494,
3354 
      n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506,
3355 
      n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
3356 
      n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530 :
3357 
      std_logic;
3358 
 
3359 
begin
3360 
 
3361 
   output_wip_reg_13 : DFA port map( C => phi2, D => input_wip(18), Q =>
3362 
                           output_wip(18), QN => n467, RN => n314);
3363 
   output_wip_reg_12 : DFA port map( C => phi2, D => input_wip(19), Q =>
3364 
                           output_wip(19), QN => n468, RN => n314);
3365 
   output_wip_reg_11 : DFA port map( C => phi2, D => input_wip(20), Q =>
3366 
                           output_wip(20), QN => n469, RN => n268);
3367 
   output_wip_reg_8 : DFA port map( C => phi2, D => input_wip(23), Q =>
3368 
                           output_wip(23), QN => n470, RN => n268);
3369 
   output_wip_reg_7 : DFA port map( C => phi2, D => input_wip(24), Q =>
3370 
                           output_wip(24), QN => n471, RN => n268);
3371 
   output_wip_reg_6 : DFA port map( C => phi2, D => input_wip(25), Q =>
3372 
                           output_wip(25), QN => n472, RN => n314);
3373 
   output_wip_reg_4 : DFA port map( C => phi2, D => input_wip(27), Q =>
3374 
                           output_wip(27), QN => n473, RN => n314);
3375 
   output_wip_reg_3 : DFA port map( C => phi2, D => input_wip(28), Q =>
3376 
                           output_wip(28), QN => n474, RN => n272);
3377 
   output_wip_reg_1 : DFA port map( C => phi2, D => input_wip(30), Q =>
3378 
                           output_wip(30), QN => n475, RN => n268);
3379 
   output_wip_reg_15 : DFA port map( C => phi2, D => input_wip(16), Q =>
3380 
                           output_wip(16), QN => n476, RN => n314);
3381 
   output_wip_reg_14 : DFA port map( C => phi2, D => input_wip(17), Q =>
3382 
                           output_wip(17), QN => n477, RN => n314);
3383 
   output_wip_reg_9 : DFA port map( C => phi2, D => input_wip(22), Q =>
3384 
                           output_wip(22), QN => n478, RN => n268);
3385 
   output_wip_reg_5 : DFA port map( C => phi2, D => input_wip(26), Q =>
3386 
                           output_wip(26), QN => n479, RN => n314);
3387 
   output_wip_reg_2 : DFA port map( C => phi2, D => input_wip(29), Q =>
3388 
                           output_wip(29), QN => n480, RN => n314);
3389 
   output_fcs_reg_31 : DFA2 port map( C => phi2, D => input_fcs(0), Q =>
3390 
                           output_fcs(0), QN => n481, RN => n314);
3391 
   output_fcs_reg_30 : DFA2 port map( C => phi2, D => input_fcs(1), Q =>
3392 
                           output_fcs(1), QN => n482, RN => n272);
3393 
   output_fcs_reg_29 : DFA2 port map( C => phi2, D => input_fcs(2), Q =>
3394 
                           output_fcs(2), QN => n483, RN => n314);
3395 
   output_fcs_reg_28 : DFA2 port map( C => phi2, D => input_fcs(3), Q =>
3396 
                           output_fcs(3), QN => n484, RN => n268);
3397 
   output_fcs_reg_27 : DFA2 port map( C => phi2, D => input_fcs(4), Q =>
3398 
                           output_fcs(4), QN => n485, RN => n272);
3399 
   output_fcs_reg_26 : DFA2 port map( C => phi2, D => input_fcs(5), Q =>
3400 
                           output_fcs(5), QN => n486, RN => n314);
3401 
   output_fcs_reg_25 : DFA2 port map( C => phi2, D => input_fcs(6), Q =>
3402 
                           output_fcs(6), QN => n487, RN => n272);
3403 
   output_fcs_reg_24 : DFA2 port map( C => phi2, D => input_fcs(7), Q =>
3404 
                           output_fcs(7), QN => n488, RN => n314);
3405 
   output_fcs_reg_23 : DFA2 port map( C => phi2, D => input_fcs(8), Q =>
3406 
                           output_fcs(8), QN => n489, RN => n272);
3407 
   output_fcs_reg_15 : DFA2 port map( C => phi2, D => input_fcs(16), Q =>
3408 
                           output_fcs(16), QN => n490, RN => n314);
3409 
   output_fcs_reg_14 : DFA2 port map( C => phi2, D => input_fcs(17), Q =>
3410 
                           output_fcs(17), QN => n491, RN => n272);
3411 
   output_fcs_reg_13 : DFA2 port map( C => phi2, D => input_fcs(18), Q =>
3412 
                           output_fcs(18), QN => n492, RN => n268);
3413 
   output_fcs_reg_12 : DFA2 port map( C => phi2, D => input_fcs(19), Q =>
3414 
                           output_fcs(19), QN => n493, RN => n314);
3415 
   output_fcs_reg_11 : DFA2 port map( C => phi2, D => input_fcs(20), Q =>
3416 
                           output_fcs(20), QN => n494, RN => n272);
3417 
   output_fcs_reg_10 : DFA2 port map( C => phi2, D => input_fcs(21), Q =>
3418 
                           output_fcs(21), QN => n495, RN => n314);
3419 
   output_fcs_reg_9 : DFA2 port map( C => phi2, D => input_fcs(22), Q =>
3420 
                           output_fcs(22), QN => n496, RN => n314);
3421 
   output_fcs_reg_8 : DFA2 port map( C => phi2, D => input_fcs(23), Q =>
3422 
                           output_fcs(23), QN => n497, RN => n272);
3423 
   output_fcs_reg_6 : DFA2 port map( C => phi2, D => input_fcs(25), Q =>
3424 
                           output_fcs(25), QN => n498, RN => n272);
3425 
   output_fcs_reg_5 : DFA2 port map( C => phi2, D => input_fcs(26), Q =>
3426 
                           output_fcs(26), QN => n499, RN => n272);
3427 
   output_fcs_reg_4 : DFA2 port map( C => phi2, D => input_fcs(27), Q =>
3428 
                           output_fcs(27), QN => n500, RN => n268);
3429 
   output_fcs_reg_3 : DFA2 port map( C => phi2, D => input_fcs(28), Q =>
3430 
                           output_fcs(28), QN => n501, RN => n272);
3431 
   output_wip_reg_31 : DFA2 port map( C => phi2, D => input_wip(0), Q =>
3432 
                           output_wip(0), QN => n502, RN => n272);
3433 
   output_wip_reg_30 : DFA2 port map( C => phi2, D => input_wip(1), Q =>
3434 
                           output_wip(1), QN => n503, RN => n272);
3435 
   output_wip_reg_29 : DFA2 port map( C => phi2, D => input_wip(2), Q =>
3436 
                           output_wip(2), QN => n504, RN => n272);
3437 
   output_wip_reg_28 : DFA2 port map( C => phi2, D => input_wip(3), Q =>
3438 
                           output_wip(3), QN => n505, RN => n272);
3439 
   output_wip_reg_27 : DFA2 port map( C => phi2, D => input_wip(4), Q =>
3440 
                           output_wip(4), QN => n506, RN => n272);
3441 
   output_wip_reg_26 : DFA2 port map( C => phi2, D => input_wip(5), Q =>
3442 
                           output_wip(5), QN => n507, RN => n272);
3443 
   output_wip_reg_25 : DFA2 port map( C => phi2, D => input_wip(6), Q =>
3444 
                           output_wip(6), QN => n508, RN => n272);
3445 
   output_wip_reg_24 : DFA2 port map( C => phi2, D => input_wip(7), Q =>
3446 
                           output_wip(7), QN => n509, RN => n272);
3447 
   output_wip_reg_22 : DFA2 port map( C => phi2, D => input_wip(9), Q =>
3448 
                           output_wip(9), QN => n510, RN => n272);
3449 
   output_wip_reg_21 : DFA2 port map( C => phi2, D => input_wip(10), Q =>
3450 
                           output_wip(10), QN => n511, RN => n314);
3451 
   output_wip_reg_20 : DFA2 port map( C => phi2, D => input_wip(11), Q =>
3452 
                           output_wip(11), QN => n512, RN => n314);
3453 
   output_wip_reg_19 : DFA2 port map( C => phi2, D => input_wip(12), Q =>
3454 
                           output_wip(12), QN => n513, RN => n314);
3455 
   output_wip_reg_0 : DFA2 port map( C => phi2, D => input_wip(31), Q =>
3456 
                           output_wip(31), QN => n514, RN => n314);
3457 
   U147 : BU4 port map( A => n268, Q => n314);
3458 
   U148 : BU4 port map( A => n268, Q => n272);
3459 
   U149 : BU2 port map( A => reset, Q => n268);
3460 
   U150 : IN4 port map( A => n316, Q => output_fcs(12));
3461 
   output_wip_reg_10 : DFA port map( C => phi2, D => input_wip(21), Q =>
3462 
                           output_wip(21), QN => n515, RN => n272);
3463 
   output_fcs_reg_20 : DFA port map( C => phi2, D => input_fcs(11), Q =>
3464 
                           output_fcs(11), QN => n516, RN => n314);
3465 
   U151 : IN4 port map( A => n320, Q => output_fcs(14));
3466 
   U152 : IN4 port map( A => n324, Q => output_fcs(15));
3467 
   output_fcs_reg_21 : DFA2 port map( C => phi2, D => input_fcs(10), Q =>
3468 
                           output_fcs(10), QN => n517, RN => n314);
3469 
   U153 : IN4 port map( A => n328, Q => output_fcs(13));
3470 
   output_wip_reg_23 : DFA port map( C => phi2, D => input_wip(8), Q =>
3471 
                           output_wip(8), QN => n518, RN => n272);
3472 
   output_wip_reg_18 : DFA port map( C => phi2, D => input_wip(13), Q =>
3473 
                           output_wip(13), QN => n519, RN => n314);
3474 
   output_wip_reg_17 : DFA port map( C => phi2, D => input_wip(14), Q =>
3475 
                           output_wip(14), QN => n520, RN => n272);
3476 
   output_wip_reg_16 : DFA port map( C => phi2, D => input_wip(15), Q =>
3477 
                           output_wip(15), QN => n521, RN => n314);
3478 
   output_fcs_reg_7 : DFA port map( C => phi2, D => input_fcs(24), Q =>
3479 
                           output_fcs(24), QN => n522, RN => n314);
3480 
   output_fcs_reg_2 : DFA port map( C => phi2, D => input_fcs(29), Q =>
3481 
                           output_fcs(29), QN => n523, RN => n314);
3482 
   output_fcs_reg_1 : DFA port map( C => phi2, D => input_fcs(30), Q =>
3483 
                           output_fcs(30), QN => n524, RN => n272);
3484 
   output_fcs_reg_0 : DFA port map( C => phi2, D => input_fcs(31), Q =>
3485 
                           output_fcs(31), QN => n525, RN => n272);
3486 
   output_fcs_reg_22 : DFA2 port map( C => phi2, D => input_fcs(9), Q =>
3487 
                           output_fcs(9), QN => n526, RN => n314);
3488 
   output_fcs_reg_19 : DFA2 port map( C => phi2, D => input_fcs(12), Q => n527,
3489 
                           QN => n316, RN => n272);
3490 
   output_fcs_reg_17 : DFA2 port map( C => phi2, D => input_fcs(14), Q => n528,
3491 
                           QN => n320, RN => n314);
3492 
   output_fcs_reg_16 : DFA2 port map( C => phi2, D => input_fcs(15), Q => n529,
3493 
                           QN => n324, RN => n272);
3494 
   output_fcs_reg_18 : DFA2 port map( C => phi2, D => input_fcs(13), Q => n530,
3495 
                           QN => n328, RN => n268);
3496 
 
3497 
end SYN_behavior_3;
3498 
 
3499 
library IEEE;
3500 
library csx_HRDLIB;
3501 
library csx_IOLIB_3M;
3502 
 
3503 
use IEEE.std_logic_1164.all;
3504 
use IEEE.std_logic_arith.all;
3505 
use csx_HRDLIB.Vcomponents.all;
3506 
use csx_IOLIB_3M.Vcomponents.all;
3507 
 
3508 
entity gf_multiplier is
3509 
 
3510 
   port( reset, phi1, phi2 : in std_logic;  input : in std_logic_vector (0 to
3511 
         31);  output_fcs, output_xor : out std_logic_vector (0 to 15));
3512 
 
3513 
end gf_multiplier;
3514 
 
3515 
architecture SYN_structural_architecture2 of gf_multiplier is
3516 
 
3517 
   component gf_xor_input
3518 
      port( input_fcs : in std_logic_vector (0 to 31);  output_wip : out
3519 
            std_logic_vector (0 to 31));
3520 
   end component;
3521 
 
3522 
   component gf_xor_2x
3523 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3524 
            out std_logic_vector (0 to 31));
3525 
   end component;
3526 
 
3527 
   component gf_xor_3x
3528 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3529 
            out std_logic_vector (0 to 31));
3530 
   end component;
3531 
 
3532 
   component gf_xor_4x
3533 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3534 
            out std_logic_vector (0 to 31));
3535 
   end component;
3536 
 
3537 
   component gf_xor_5x
3538 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3539 
            out std_logic_vector (0 to 31));
3540 
   end component;
3541 
 
3542 
   component gf_xor_6x
3543 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3544 
            out std_logic_vector (0 to 31));
3545 
   end component;
3546 
 
3547 
   component gf_xor_7x
3548 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3549 
            out std_logic_vector (0 to 31));
3550 
   end component;
3551 
 
3552 
   component gf_xor_8x
3553 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3554 
            out std_logic_vector (0 to 31));
3555 
   end component;
3556 
 
3557 
   component gf_xor_9x
3558 
      port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip :
3559 
            out std_logic_vector (0 to 31));
3560 
   end component;
3561 
 
3562 
   component gf_phi1_register_out
3563 
      port( reset, phi1 : in std_logic;  input_wip : in std_logic_vector (0 to
3564 
            31);  output_final : out std_logic_vector (0 to 31));
3565 
   end component;
3566 
 
3567 
   component gf_phi1_register_0
3568 
      port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
3569 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3570 
            std_logic_vector (0 to 31));
3571 
   end component;
3572 
 
3573 
   component gf_phi1_register_1
3574 
      port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
3575 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3576 
            std_logic_vector (0 to 31));
3577 
   end component;
3578 
 
3579 
   component gf_phi1_register_2
3580 
      port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
3581 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3582 
            std_logic_vector (0 to 31));
3583 
   end component;
3584 
 
3585 
   component gf_phi1_register_3
3586 
      port( reset, phi1 : in std_logic;  input_wip, input_fcs : in
3587 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3588 
            std_logic_vector (0 to 31));
3589 
   end component;
3590 
 
3591 
   component gf_phi2_register_0
3592 
      port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
3593 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3594 
            std_logic_vector (0 to 31));
3595 
   end component;
3596 
 
3597 
   component gf_phi2_register_1
3598 
      port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
3599 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3600 
            std_logic_vector (0 to 31));
3601 
   end component;
3602 
 
3603 
   component gf_phi2_register_2
3604 
      port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
3605 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3606 
            std_logic_vector (0 to 31));
3607 
   end component;
3608 
 
3609 
   component gf_phi2_register_3
3610 
      port( reset, phi2 : in std_logic;  input_wip, input_fcs : in
3611 
            std_logic_vector (0 to 31);  output_wip, output_fcs : out
3612 
            std_logic_vector (0 to 31));
3613 
   end component;
3614 
 
3615 
   signal btw1x_2_7, btw2x_3_4, btw3_4_29, btw3_3x_14, btw6_7_7, btw7_8_0,
3616 
      btw7x_8_3, btw9_9x_31, btw9_9x_16, btw8x_9_26, btw7x_8_27, btw1x_2_20,
3617 
      btw4x_5_28, btw6x_7_21, btw7_7x_16, btw7_7x_31, btw2_3_23, btw3x_4_21,
3618 
      btw5_5x_14, btw8_9_26, btw4_4x_11, btw4_4x_2, btw6_6x_13, btw9_10_0,
3619 
      btw4x_5_7, btw5x_6_5, btw6x_7_6, btw9_10_10, btw5_6_11, btw7_8_12,
3620 
      btw9x_10_7, btw1x_2_29, btw2_3_6, btw3_4_15, btw3_4_0, btw4_5_13,
3621 
      btw4x_5_14, btw5_5x_28, btw8_9_5, btw2_2x_24, btw2_2x_11, btw2x_3_10,
3622 
      btw3_3x_28, btw5x_6_11, btw6_6x_2, btw3_3x_1, btw3x_4_0, btw6_7_13,
3623 
      btw8_8x_13, btw9_9x_4, btw9x_10_20, btw7_8_9, btw9x_10_15, btw2x_3_25,
3624 
      btw6_7_26, btw8_8x_26, btw4_5_26, btw5x_6_24, btw4x_5_21, btw6x_7_28,
3625 
      btw3_4_20, btw1x_2_15, btw2_3_31, btw2_3_16, btw3x_4_28, btw4_5_4,
3626 
      btw5_6_24, btw7_8_27, btw4_4x_24, btw6_6x_26, btw8x_9_3, btw9_10_25,
3627 
      btw4_4x_18, btw3_4_9, btw3x_4_14, btw9_10_19, btw9_10_9, btw7_7x_4,
3628 
      btw8_9_13, btw8_8x_2, btw5_5x_21, btw2_3_11, btw2_3_8, btw2_2x_18,
3629 
      btw2_2x_7, btw7_7x_23, btw2x_3_19, btw3_3x_8, btw5_6_18, btw6x_7_14,
3630 
      btw7x_8_12, btw3x_4_9, btw3_3x_21, btw5_6_4, btw5x_6_18, btw8x_9_13,
3631 
      btw5_6_3, btw5_5x_4, btw9x_10_29, btw8x_9_14, btw9_9x_23, btw3_3x_26,
3632 
      btw3x_4_13, btw5_5x_3, btw8_8x_5, btw9_9x_24, btw4x_5_9, btw6x_7_8,
3633 
      btw7x_8_15, btw9x_10_9, btw1x_2_12, btw2_2x_0, btw6x_7_13, btw7_7x_24,
3634 
      btw3_4_27, btw5_6_23, btw5_5x_26, btw7_7x_3, btw7x_8_29, btw8_9_14,
3635 
      btw1x_2_9, btw4_5_21, btw4x_5_26, btw7_7x_18, btw8_9_28, btw4_5_3,
3636 
      btw4_4x_23, btw6_6x_21, btw8x_9_4, btw9_10_22, btw7_8_20, btw2_3_1,
3637 
      btw2_2x_23, btw6_7_21, btw9_9x_18, btw2x_3_30, btw2x_3_22, btw5x_6_23,
3638 
      btw8x_9_28, btw9x_10_12, btw6_7_9, btw2x_3_17, btw3_3x_6, btw8_8x_21,
3639 
      btw3x_4_7, btw5x_6_31, btw8_8x_14, btw6_6x_5, btw5x_6_16, btw2_2x_31,
3640 
      btw2_2x_16, btw6_7_14, btw9_9x_3, btw9x_10_27, btw2_3_18, btw7_8_15,
3641 
      btw9x_10_0, btw2_2x_9, btw3_4_7, btw4_4x_31, btw4_4x_16, btw4x_5_0,
3642 
      btw9_10_30, btw4_4x_5, btw5x_6_2, btw9_10_17, btw6_6x_14, btw6x_7_1,
3643 
      btw9_10_7, btw4_5_14, btw5_6_31, btw8_9_2, btw4x_5_13, btw3_4_12,
3644 
      btw1x_2_27, btw4_5_28, btw5_6_16, btw5_5x_13, btw8_9_21, btw6x_7_26,
3645 
      btw7_7x_11, btw7x_8_20, btw1x_2_8, btw1x_2_0, btw2_3_24, btw7_8_29,
3646 
      btw2x_3_3, btw3x_4_26, btw6_7_28, btw6_6x_28, btw7_8_7, btw7x_8_4,
3647 
      btw9_9x_11, btw3_3x_13, btw8_8x_28, btw6_7_0, btw8x_9_21, btw2_2x_22,
3648 
      btw6_7_20, btw9_9x_19, btw9x_10_13, btw2x_3_23, btw5x_6_22, btw6_7_8,
3649 
      btw8x_9_29, btw5_6_22, btw7x_8_28, btw8_8x_20, btw1x_2_26, btw1x_2_13,
3650 
      btw2_3_10, btw3_4_26, btw3x_4_12, btw4_5_20, btw4x_5_27, btw7_7x_19,
3651 
      btw4_5_2, btw4_4x_22, btw6_6x_20, btw8_9_29, btw8x_9_5, btw9_10_23,
3652 
      btw7_8_21, btw6x_7_9, btw8_8x_4, btw2_2x_1, btw4x_5_8, btw7_7x_25,
3653 
      btw7x_8_14, btw9x_10_8, btw6x_7_12, btw1x_2_1, btw2_3_9, btw5_6_2,
3654 
      btw5_5x_27, btw7_7x_2, btw8_9_15, btw8x_9_15, btw2x_3_2, btw3_3x_27,
3655 
      btw5_5x_2, btw6_7_29, btw7_8_6, btw9_9x_25, btw7x_8_5, btw9_9x_10,
3656 
      btw3_3x_12, btw8_8x_29, btw4_5_29, btw6_7_1, btw8_9_20, btw8x_9_20,
3657 
      btw5_5x_12, btw6x_7_27, btw7_7x_10, btw7x_8_21, btw2_3_25, btw7_8_28,
3658 
      btw2_3_19, btw3x_4_27, btw4x_5_1, btw6_6x_29, btw7_8_14, btw9x_10_1,
3659 
      btw9_10_31, btw2_2x_8, btw3_4_6, btw4_5_15, btw4_4x_30, btw4_4x_17,
3660 
      btw9_10_16, btw4_4x_4, btw6_6x_15, btw9_10_6, btw5_6_30, btw5x_6_3,
3661 
      btw6x_7_0, btw4x_5_12, btw8_9_3, btw2_3_7, btw2_3_0, btw2x_3_16,
3662 
      btw3_4_13, btw3_3x_7, btw3x_4_6, btw5_6_17, btw5x_6_30, btw8_8x_15,
3663 
      btw2_2x_30, btw2_2x_17, btw2x_3_31, btw6_6x_4, btw5x_6_17, btw9x_10_26,
3664 
      btw6_7_15, btw9_9x_2, btw5x_6_10, btw6_6x_3, btw2_2x_10, btw2x_3_11,
3665 
      btw3_3x_29, btw3_3x_0, btw3x_4_1, btw6_7_12, btw8_8x_12, btw9_9x_5,
3666 
      btw3_4_14, btw4_4x_10, btw4_4x_3, btw5x_6_4, btw9x_10_21, btw6_6x_12,
3667 
      btw6x_7_7, btw9_10_1, btw9_10_11, btw4x_5_6, btw5_6_10, btw7_8_13,
3668 
      btw9x_10_6, btw3_4_28, btw3_4_1, btw4x_5_15, btw8_9_4, btw4_5_12,
3669 
      btw5_5x_29, btw7x_8_26, btw1x_2_28, btw1x_2_21, btw6x_7_20, btw7_7x_17,
3670 
      btw1x_2_14, btw1x_2_6, btw2_3_22, btw3x_4_20, btw4x_5_29, btw5_5x_15,
3671 
      btw7_7x_30, btw8_9_27, btw2x_3_5, btw2_3_30, btw2_3_17, btw2_2x_19,
3672 
      btw2x_3_18, btw3_3x_20, btw3_3x_15, btw6_7_6, btw7_8_1, btw7x_8_2,
3673 
      btw9_9x_30, btw9_9x_17, btw8x_9_27, btw3_3x_9, btw3x_4_8, btw5_6_5,
3674 
      btw5x_6_19, btw8x_9_12, btw9x_10_28, btw4_4x_19, btw5_5x_5, btw9_9x_22,
3675 
      btw9_10_18, btw3_4_8, btw3x_4_15, btw5_5x_20, btw8_8x_3, btw9_10_8,
3676 
      btw7_7x_5, btw8_9_12, btw2_2x_6, btw4_5_27, btw5_6_19, btw6x_7_15,
3677 
      btw7_7x_22, btw7x_8_13, btw4x_5_20, btw3_4_21, btw6x_7_29, btw5_6_25,
3678 
      btw1x_2_23, btw1x_2_4, btw2_2x_25, btw3x_4_29, btw4_5_5, btw4_4x_25,
3679 
      btw7_8_26, btw6_6x_27, btw8x_9_2, btw9_10_24, btw2x_3_24, btw6_7_27,
3680 
      btw7_8_8, btw9x_10_14, btw8_8x_27, btw2x_3_7, btw3_3x_30, btw3_3x_17,
3681 
      btw5x_6_25, btw6_7_4, btw8x_9_25, btw7_8_3, btw9_9x_15, btw7x_8_0,
3682 
      btw2_3_20, btw3x_4_22, btw8x_9_9, btw5_5x_17, btw8_9_25, btw7x_8_24,
3683 
      btw3_4_31, btw4x_5_17, btw5_5x_30, btw6x_7_22, btw7_7x_15, btw3_4_16,
3684 
      btw3_4_3, btw4_5_10, btw8_9_19, btw8_9_6, btw2_3_29, btw2_3_5, btw2_2x_12
3685 
      , btw4_4x_12, btw4x_5_30, btw5_6_12, btw7x_8_18, btw7_7x_29, btw4x_5_4,
3686 
      btw4_4x_1, btw5x_6_6, btw6_6x_10, btw7_8_11, btw9x_10_4, btw8_8x_8,
3687 
      btw6_7_10, btw6x_7_5, btw9_10_3, btw9_10_13, btw9_9x_7, btw9_9x_29,
3688 
      btw2x_3_13, btw9x_10_23, btw3_3x_2, btw3x_4_3, btw8_8x_10, btw8x_9_19,
3689 
      btw2_2x_27, btw2x_3_26, btw5x_6_27, btw5x_6_12, btw6_6x_1, btw8_8x_25,
3690 
      btw7x_8_9, btw9x_10_31, btw4_5_7, btw6_7_25, btw9x_10_16, btw6_6x_25,
3691 
      btw8x_9_0, btw9_10_26, btw7_8_24, btw4_4x_27, btw3_4_23, btw5_6_27,
3692 
      btw1x_2_31, btw4_5_25, btw4x_5_22, btw7_7x_20, btw2_2x_4, btw6x_7_17,
3693 
      btw1x_2_16, btw4_5_19, btw5_5x_22, btw7_7x_7, btw7x_8_11, btw8_9_10,
3694 
      btw6x_7_30, btw1x_2_11, btw2_3_15, btw3x_4_30, btw3x_4_17, btw4_4x_8,
3695 
      btw6_6x_19, btw8_8x_1, btw7_8_18, btw3_3x_25, btw3_3x_22, btw5_6_7,
3696 
      btw5_5x_7, btw6_7_19, btw9_9x_20, btw6_6x_8, btw8_8x_19, btw8x_9_10,
3697 
      btw5_5x_0, btw9_9x_9, btw9_9x_27, btw5_6_0, btw8x_9_30, btw8x_9_17,
3698 
      btw2_3_12, btw2_2x_3, btw3_4_18, btw4x_5_19, btw5_5x_25, btw7x_8_31,
3699 
      btw7_7x_0, btw8_9_17, btw8_9_8, btw7x_8_16, btw8_9_30, btw6x_7_10,
3700 
      btw7_7x_27, btw3x_4_10, btw4_5_22, btw4_5_0, btw4_4x_20, btw5x_6_8,
3701 
      btw8_8x_6, btw4x_5_25, btw6_6x_22, btw7_8_23, btw8x_9_7, btw9_10_21,
3702 
      btw5_5x_19, btw2_3_2, btw2_2x_20, btw2x_3_21, btw3_4_24, btw5_6_20,
3703 
      btw3_3x_19, btw5x_6_20, btw8_8x_22, btw6_7_22, btw9x_10_11, btw2_2x_15,
3704 
      btw2x_3_9, btw6_7_30, btw9x_10_24, btw5_5x_9, btw5x_6_15, btw6_7_17,
3705 
      btw9_9x_0, btw6_6x_6, btw2x_3_14, btw3_3x_5, btw3x_4_4, btw5_6_9,
3706 
      btw8_8x_30, btw8_8x_17, btw4_5_30, btw6x_7_19, btw5_6_15, btw3_4_11,
3707 
      btw3_4_4, btw7_7x_9, btw8_9_1, btw4_5_17, btw1x_2_18, btw4x_5_10,
3708 
      btw2_3_27, btw3x_4_25, btw3x_4_19, btw4_4x_6, btw9_10_14, btw9_10_4,
3709 
      btw5x_6_1, btw6x_7_2, btw4_4x_15, btw6_6x_30, btw6_6x_17, btw7_8_31,
3710 
      btw7_8_16, btw9x_10_3, btw4x_5_3, btw9_10_28, btw4_5_9, btw4_4x_29,
3711 
      btw5_6_29, btw6x_7_25, btw7_7x_12, btw7x_8_23, btw1x_2_24, btw5_5x_10,
3712 
      btw8_9_22, btw1x_2_3, btw2x_3_28, btw3_3x_10, btw5x_6_29, btw6_7_3,
3713 
      btw8x_9_22, btw2x_3_0, btw2_2x_29, btw7_8_4, btw7x_8_7, btw2_2x_21,
3714 
      btw2x_3_20, btw3_3x_18, btw9_9x_12, btw9x_10_18, btw5x_6_21, btw8_8x_23,
3715 
      btw6_7_23, btw2x_3_8, btw9x_10_10, btw3_4_25, btw4_5_23, btw4_5_1,
3716 
      btw4_4x_21, btw7_8_22, btw4x_5_24, btw6_6x_23, btw8x_9_6, btw9_10_20,
3717 
      btw5_5x_18, btw1x_2_10, btw4x_5_18, btw5_6_21, btw1x_2_2, btw2_3_13,
3718 
      btw2_2x_2, btw3_4_19, btw5_5x_24, btw7_7x_1, btw8_9_16, btw8_9_9,
3719 
      btw7x_8_30, btw7x_8_17, btw8_9_31, btw7_7x_26, btw6x_7_11, btw2x_3_29,
3720 
      btw3_3x_24, btw3x_4_11, btw5x_6_9, btw5_5x_1, btw8_8x_7, btw9_9x_26,
3721 
      btw9_9x_8, btw5_6_1, btw8x_9_31, btw5x_6_28, btw8x_9_16, btw6_7_2,
3722 
      btw8x_9_23, btw2x_3_1, btw3_3x_11, btw2_3_26, btw2_2x_28, btw9x_10_19,
3723 
      btw3x_4_24, btw7_8_5, btw7x_8_6, btw9_10_29, btw9_9x_13, btw4_5_8,
3724 
      btw4_4x_28, btw6x_7_24, btw7_7x_13, btw7x_8_22, btw1x_2_25, btw5_6_28,
3725 
      btw5_5x_11, btw8_9_23, btw3_4_10, btw4_5_31, btw6x_7_18, btw5_6_14,
3726 
      btw4_5_16, btw1x_2_19, btw3_4_5, btw7_7x_8, btw8_9_0, btw2_3_4, btw2_3_3,
3727 
      btw2_2x_14, btw3x_4_18, btw4x_5_11, btw7_8_30, btw9_10_15, btw4_4x_14,
3728 
      btw4_4x_7, btw5x_6_0, btw6_6x_16, btw4x_5_2, btw6_6x_31, btw6x_7_3,
3729 
      btw9_10_5, btw7_8_17, btw9x_10_2, btw6_7_31, btw5_5x_8, btw6_7_16,
3730 
      btw9x_10_25, btw9_9x_1, btw2_2x_13, btw2x_3_15, btw3_3x_4, btw5_6_8,
3731 
      btw5x_6_14, btw6_6x_7, btw8_8x_31, btw3x_4_5, btw8_8x_16, btw6_7_11,
3732 
      btw9_9x_28, btw9_9x_6, btw9x_10_22, btw2x_3_12, btw3_3x_3, btw3x_4_2,
3733 
      btw5x_6_13, btw6_6x_0, btw8_8x_11, btw8x_9_18, btw3_4_30, btw3_4_2,
3734 
      btw4x_5_16, btw8_9_18, btw8_9_7, btw4_5_11, btw1x_2_22, btw2_3_21,
3735 
      btw3_4_17, btw4_4x_13, btw4x_5_31, btw5_6_13, btw7x_8_19, btw7_7x_28,
3736 
      btw4_4x_0, btw4x_5_5, btw7_8_10, btw9x_10_5, btw9_10_2, btw5x_6_7,
3737 
      btw6_6x_11, btw6x_7_4, btw8_8x_9, btw9_10_12, btw3x_4_23, btw8x_9_8,
3738 
      btw5_5x_16, btw7x_8_25, btw8_9_24, btw1x_2_30, btw1x_2_5, btw2x_3_6,
3739 
      btw3_3x_31, btw3_3x_16, btw5_5x_31, btw6x_7_23, btw7_7x_14, btw8x_9_24,
3740 
      btw6_7_5, btw7_8_2, btw9_9x_14, btw7x_8_1, btw2_2x_5, btw3_3x_23,
3741 
      btw5_6_6, btw5_5x_6, btw6_7_18, btw6_6x_9, btw9_9x_21, btw8x_9_11,
3742 
      btw8_8x_18, btw6x_7_16, btw7_7x_21, btw1x_2_17, btw4_5_18, btw5_5x_23,
3743 
      btw7x_8_10, btw6x_7_31, btw7_7x_6, btw8_9_11, btw2_3_28, btw2_3_14,
3744 
      btw3x_4_31, btw3x_4_16, btw6_6x_18, btw8_8x_0, btw4_4x_9, btw7_8_19,
3745 
      btw4_5_6, btw6_6x_24, btw8x_9_1, btw9_10_27, btw4_4x_26, btw7_8_25,
3746 
      btw5_6_26, btw2_2x_26, btw2x_3_27, btw3_4_22, btw4_5_24, btw4x_5_23,
3747 
      btw5x_6_26, btw8_8x_24, btw9x_10_30, btw9x_10_17, btw6_7_24, btw7x_8_8 :
3748 
      std_logic;
3749 
 
3750 
begin
3751 
 
3752 
   GF1x : gf_xor_input port map( input_fcs(0) => input(0), input_fcs(1) =>
3753 
                           input(1), input_fcs(2) => input(2), input_fcs(3) =>
3754 
                           input(3), input_fcs(4) => input(4), input_fcs(5) =>
3755 
                           input(5), input_fcs(6) => input(6), input_fcs(7) =>
3756 
                           input(7), input_fcs(8) => input(8), input_fcs(9) =>
3757 
                           input(9), input_fcs(10) => input(10), input_fcs(11)
3758 
                           => input(11), input_fcs(12) => input(12),
3759 
                           input_fcs(13) => input(13), input_fcs(14) =>
3760 
                           input(14), input_fcs(15) => input(15), input_fcs(16)
3761 
                           => input(16), input_fcs(17) => input(17),
3762 
                           input_fcs(18) => input(18), input_fcs(19) =>
3763 
                           input(19), input_fcs(20) => input(20), input_fcs(21)
3764 
                           => input(21), input_fcs(22) => input(22),
3765 
                           input_fcs(23) => input(23), input_fcs(24) =>
3766 
                           input(24), input_fcs(25) => input(25), input_fcs(26)
3767 
                           => input(26), input_fcs(27) => input(27),
3768 
                           input_fcs(28) => input(28), input_fcs(29) =>
3769 
                           input(29), input_fcs(30) => input(30), input_fcs(31)
3770 
                           => input(31), output_wip(0) => btw1x_2_31,
3771 
                           output_wip(1) => btw1x_2_30, output_wip(2) =>
3772 
                           btw1x_2_29, output_wip(3) => btw1x_2_28,
3773 
                           output_wip(4) => btw1x_2_27, output_wip(5) =>
3774 
                           btw1x_2_26, output_wip(6) => btw1x_2_25,
3775 
                           output_wip(7) => btw1x_2_24, output_wip(8) =>
3776 
                           btw1x_2_23, output_wip(9) => btw1x_2_22,
3777 
                           output_wip(10) => btw1x_2_21, output_wip(11) =>
3778 
                           btw1x_2_20, output_wip(12) => btw1x_2_19,
3779 
                           output_wip(13) => btw1x_2_18, output_wip(14) =>
3780 
                           btw1x_2_17, output_wip(15) => btw1x_2_16,
3781 
                           output_wip(16) => btw1x_2_15, output_wip(17) =>
3782 
                           btw1x_2_14, output_wip(18) => btw1x_2_13,
3783 
                           output_wip(19) => btw1x_2_12, output_wip(20) =>
3784 
                           btw1x_2_11, output_wip(21) => btw1x_2_10,
3785 
                           output_wip(22) => btw1x_2_9, output_wip(23) =>
3786 
                           btw1x_2_8, output_wip(24) => btw1x_2_7,
3787 
                           output_wip(25) => btw1x_2_6, output_wip(26) =>
3788 
                           btw1x_2_5, output_wip(27) => btw1x_2_4,
3789 
                           output_wip(28) => btw1x_2_3, output_wip(29) =>
3790 
                           btw1x_2_2, output_wip(30) => btw1x_2_1,
3791 
                           output_wip(31) => btw1x_2_0);
3792 
   GF2x : gf_xor_2x port map( input_wip(0) => btw2_2x_31, input_wip(1) =>
3793 
                           btw2_2x_30, input_wip(2) => btw2_2x_29, input_wip(3)
3794 
                           => btw2_2x_28, input_wip(4) => btw2_2x_27,
3795 
                           input_wip(5) => btw2_2x_26, input_wip(6) =>
3796 
                           btw2_2x_25, input_wip(7) => btw2_2x_24, input_wip(8)
3797 
                           => btw2_2x_23, input_wip(9) => btw2_2x_22,
3798 
                           input_wip(10) => btw2_2x_21, input_wip(11) =>
3799 
                           btw2_2x_20, input_wip(12) => btw2_2x_19,
3800 
                           input_wip(13) => btw2_2x_18, input_wip(14) =>
3801 
                           btw2_2x_17, input_wip(15) => btw2_2x_16,
3802 
                           input_wip(16) => btw2_2x_15, input_wip(17) =>
3803 
                           btw2_2x_14, input_wip(18) => btw2_2x_13,
3804 
                           input_wip(19) => btw2_2x_12, input_wip(20) =>
3805 
                           btw2_2x_11, input_wip(21) => btw2_2x_10,
3806 
                           input_wip(22) => btw2_2x_9, input_wip(23) =>
3807 
                           btw2_2x_8, input_wip(24) => btw2_2x_7, input_wip(25)
3808 
                           => btw2_2x_6, input_wip(26) => btw2_2x_5,
3809 
                           input_wip(27) => btw2_2x_4, input_wip(28) =>
3810 
                           btw2_2x_3, input_wip(29) => btw2_2x_2, input_wip(30)
3811 
                           => btw2_2x_1, input_wip(31) => btw2_2x_0,
3812 
                           input_fcs(0) => btw2_3_31, input_fcs(1) => btw2_3_30
3813 
                           , input_fcs(2) => btw2_3_29, input_fcs(3) =>
3814 
                           btw2_3_28, input_fcs(4) => btw2_3_27, input_fcs(5)
3815 
                           => btw2_3_26, input_fcs(6) => btw2_3_25,
3816 
                           input_fcs(7) => btw2_3_24, input_fcs(8) => btw2_3_23
3817 
                           , input_fcs(9) => btw2_3_22, input_fcs(10) =>
3818 
                           btw2_3_21, input_fcs(11) => btw2_3_20, input_fcs(12)
3819 
                           => btw2_3_19, input_fcs(13) => btw2_3_18,
3820 
                           input_fcs(14) => btw2_3_17, input_fcs(15) =>
3821 
                           btw2_3_16, input_fcs(16) => btw2_3_15, input_fcs(17)
3822 
                           => btw2_3_14, input_fcs(18) => btw2_3_13,
3823 
                           input_fcs(19) => btw2_3_12, input_fcs(20) =>
3824 
                           btw2_3_11, input_fcs(21) => btw2_3_10, input_fcs(22)
3825 
                           => btw2_3_9, input_fcs(23) => btw2_3_8,
3826 
                           input_fcs(24) => btw2_3_7, input_fcs(25) => btw2_3_6
3827 
                           , input_fcs(26) => btw2_3_5, input_fcs(27) =>
3828 
                           btw2_3_4, input_fcs(28) => btw2_3_3, input_fcs(29)
3829 
                           => btw2_3_2, input_fcs(30) => btw2_3_1,
3830 
                           input_fcs(31) => btw2_3_0, output_wip(0) =>
3831 
                           btw2x_3_31, output_wip(1) => btw2x_3_30,
3832 
                           output_wip(2) => btw2x_3_29, output_wip(3) =>
3833 
                           btw2x_3_28, output_wip(4) => btw2x_3_27,
3834 
                           output_wip(5) => btw2x_3_26, output_wip(6) =>
3835 
                           btw2x_3_25, output_wip(7) => btw2x_3_24,
3836 
                           output_wip(8) => btw2x_3_23, output_wip(9) =>
3837 
                           btw2x_3_22, output_wip(10) => btw2x_3_21,
3838 
                           output_wip(11) => btw2x_3_20, output_wip(12) =>
3839 
                           btw2x_3_19, output_wip(13) => btw2x_3_18,
3840 
                           output_wip(14) => btw2x_3_17, output_wip(15) =>
3841 
                           btw2x_3_16, output_wip(16) => btw2x_3_15,
3842 
                           output_wip(17) => btw2x_3_14, output_wip(18) =>
3843 
                           btw2x_3_13, output_wip(19) => btw2x_3_12,
3844 
                           output_wip(20) => btw2x_3_11, output_wip(21) =>
3845 
                           btw2x_3_10, output_wip(22) => btw2x_3_9,
3846 
                           output_wip(23) => btw2x_3_8, output_wip(24) =>
3847 
                           btw2x_3_7, output_wip(25) => btw2x_3_6,
3848 
                           output_wip(26) => btw2x_3_5, output_wip(27) =>
3849 
                           btw2x_3_4, output_wip(28) => btw2x_3_3,
3850 
                           output_wip(29) => btw2x_3_2, output_wip(30) =>
3851 
                           btw2x_3_1, output_wip(31) => btw2x_3_0);
3852 
   GF6 : gf_phi1_register_3 port map( reset => reset, phi1 => phi1,
3853 
                           input_wip(0) => btw5x_6_31, input_wip(1) =>
3854 
                           btw5x_6_30, input_wip(2) => btw5x_6_29, input_wip(3)
3855 
                           => btw5x_6_28, input_wip(4) => btw5x_6_27,
3856 
                           input_wip(5) => btw5x_6_26, input_wip(6) =>
3857 
                           btw5x_6_25, input_wip(7) => btw5x_6_24, input_wip(8)
3858 
                           => btw5x_6_23, input_wip(9) => btw5x_6_22,
3859 
                           input_wip(10) => btw5x_6_21, input_wip(11) =>
3860 
                           btw5x_6_20, input_wip(12) => btw5x_6_19,
3861 
                           input_wip(13) => btw5x_6_18, input_wip(14) =>
3862 
                           btw5x_6_17, input_wip(15) => btw5x_6_16,
3863 
                           input_wip(16) => btw5x_6_15, input_wip(17) =>
3864 
                           btw5x_6_14, input_wip(18) => btw5x_6_13,
3865 
                           input_wip(19) => btw5x_6_12, input_wip(20) =>
3866 
                           btw5x_6_11, input_wip(21) => btw5x_6_10,
3867 
                           input_wip(22) => btw5x_6_9, input_wip(23) =>
3868 
                           btw5x_6_8, input_wip(24) => btw5x_6_7, input_wip(25)
3869 
                           => btw5x_6_6, input_wip(26) => btw5x_6_5,
3870 
                           input_wip(27) => btw5x_6_4, input_wip(28) =>
3871 
                           btw5x_6_3, input_wip(29) => btw5x_6_2, input_wip(30)
3872 
                           => btw5x_6_1, input_wip(31) => btw5x_6_0,
3873 
                           input_fcs(0) => btw5_6_31, input_fcs(1) => btw5_6_30
3874 
                           , input_fcs(2) => btw5_6_29, input_fcs(3) =>
3875 
                           btw5_6_28, input_fcs(4) => btw5_6_27, input_fcs(5)
3876 
                           => btw5_6_26, input_fcs(6) => btw5_6_25,
3877 
                           input_fcs(7) => btw5_6_24, input_fcs(8) => btw5_6_23
3878 
                           , input_fcs(9) => btw5_6_22, input_fcs(10) =>
3879 
                           btw5_6_21, input_fcs(11) => btw5_6_20, input_fcs(12)
3880 
                           => btw5_6_19, input_fcs(13) => btw5_6_18,
3881 
                           input_fcs(14) => btw5_6_17, input_fcs(15) =>
3882 
                           btw5_6_16, input_fcs(16) => btw5_6_15, input_fcs(17)
3883 
                           => btw5_6_14, input_fcs(18) => btw5_6_13,
3884 
                           input_fcs(19) => btw5_6_12, input_fcs(20) =>
3885 
                           btw5_6_11, input_fcs(21) => btw5_6_10, input_fcs(22)
3886 
                           => btw5_6_9, input_fcs(23) => btw5_6_8,
3887 
                           input_fcs(24) => btw5_6_7, input_fcs(25) => btw5_6_6
3888 
                           , input_fcs(26) => btw5_6_5, input_fcs(27) =>
3889 
                           btw5_6_4, input_fcs(28) => btw5_6_3, input_fcs(29)
3890 
                           => btw5_6_2, input_fcs(30) => btw5_6_1,
3891 
                           input_fcs(31) => btw5_6_0, output_wip(0) =>
3892 
                           btw6_6x_31, output_wip(1) => btw6_6x_30,
3893 
                           output_wip(2) => btw6_6x_29, output_wip(3) =>
3894 
                           btw6_6x_28, output_wip(4) => btw6_6x_27,
3895 
                           output_wip(5) => btw6_6x_26, output_wip(6) =>
3896 
                           btw6_6x_25, output_wip(7) => btw6_6x_24,
3897 
                           output_wip(8) => btw6_6x_23, output_wip(9) =>
3898 
                           btw6_6x_22, output_wip(10) => btw6_6x_21,
3899 
                           output_wip(11) => btw6_6x_20, output_wip(12) =>
3900 
                           btw6_6x_19, output_wip(13) => btw6_6x_18,
3901 
                           output_wip(14) => btw6_6x_17, output_wip(15) =>
3902 
                           btw6_6x_16, output_wip(16) => btw6_6x_15,
3903 
                           output_wip(17) => btw6_6x_14, output_wip(18) =>
3904 
                           btw6_6x_13, output_wip(19) => btw6_6x_12,
3905 
                           output_wip(20) => btw6_6x_11, output_wip(21) =>
3906 
                           btw6_6x_10, output_wip(22) => btw6_6x_9,
3907 
                           output_wip(23) => btw6_6x_8, output_wip(24) =>
3908 
                           btw6_6x_7, output_wip(25) => btw6_6x_6,
3909 
                           output_wip(26) => btw6_6x_5, output_wip(27) =>
3910 
                           btw6_6x_4, output_wip(28) => btw6_6x_3,
3911 
                           output_wip(29) => btw6_6x_2, output_wip(30) =>
3912 
                           btw6_6x_1, output_wip(31) => btw6_6x_0,
3913 
                           output_fcs(0) => btw6_7_31, output_fcs(1) =>
3914 
                           btw6_7_30, output_fcs(2) => btw6_7_29, output_fcs(3)
3915 
                           => btw6_7_28, output_fcs(4) => btw6_7_27,
3916 
                           output_fcs(5) => btw6_7_26, output_fcs(6) =>
3917 
                           btw6_7_25, output_fcs(7) => btw6_7_24, output_fcs(8)
3918 
                           => btw6_7_23, output_fcs(9) => btw6_7_22,
3919 
                           output_fcs(10) => btw6_7_21, output_fcs(11) =>
3920 
                           btw6_7_20, output_fcs(12) => btw6_7_19,
3921 
                           output_fcs(13) => btw6_7_18, output_fcs(14) =>
3922 
                           btw6_7_17, output_fcs(15) => btw6_7_16,
3923 
                           output_fcs(16) => btw6_7_15, output_fcs(17) =>
3924 
                           btw6_7_14, output_fcs(18) => btw6_7_13,
3925 
                           output_fcs(19) => btw6_7_12, output_fcs(20) =>
3926 
                           btw6_7_11, output_fcs(21) => btw6_7_10,
3927 
                           output_fcs(22) => btw6_7_9, output_fcs(23) =>
3928 
                           btw6_7_8, output_fcs(24) => btw6_7_7, output_fcs(25)
3929 
                           => btw6_7_6, output_fcs(26) => btw6_7_5,
3930 
                           output_fcs(27) => btw6_7_4, output_fcs(28) =>
3931 
                           btw6_7_3, output_fcs(29) => btw6_7_2, output_fcs(30)
3932 
                           => btw6_7_1, output_fcs(31) => btw6_7_0);
3933 
   GF8 : gf_phi1_register_2 port map( reset => reset, phi1 => phi1,
3934 
                           input_wip(0) => btw7x_8_31, input_wip(1) =>
3935 
                           btw7x_8_30, input_wip(2) => btw7x_8_29, input_wip(3)
3936 
                           => btw7x_8_28, input_wip(4) => btw7x_8_27,
3937 
                           input_wip(5) => btw7x_8_26, input_wip(6) =>
3938 
                           btw7x_8_25, input_wip(7) => btw7x_8_24, input_wip(8)
3939 
                           => btw7x_8_23, input_wip(9) => btw7x_8_22,
3940 
                           input_wip(10) => btw7x_8_21, input_wip(11) =>
3941 
                           btw7x_8_20, input_wip(12) => btw7x_8_19,
3942 
                           input_wip(13) => btw7x_8_18, input_wip(14) =>
3943 
                           btw7x_8_17, input_wip(15) => btw7x_8_16,
3944 
                           input_wip(16) => btw7x_8_15, input_wip(17) =>
3945 
                           btw7x_8_14, input_wip(18) => btw7x_8_13,
3946 
                           input_wip(19) => btw7x_8_12, input_wip(20) =>
3947 
                           btw7x_8_11, input_wip(21) => btw7x_8_10,
3948 
                           input_wip(22) => btw7x_8_9, input_wip(23) =>
3949 
                           btw7x_8_8, input_wip(24) => btw7x_8_7, input_wip(25)
3950 
                           => btw7x_8_6, input_wip(26) => btw7x_8_5,
3951 
                           input_wip(27) => btw7x_8_4, input_wip(28) =>
3952 
                           btw7x_8_3, input_wip(29) => btw7x_8_2, input_wip(30)
3953 
                           => btw7x_8_1, input_wip(31) => btw7x_8_0,
3954 
                           input_fcs(0) => btw7_8_31, input_fcs(1) => btw7_8_30
3955 
                           , input_fcs(2) => btw7_8_29, input_fcs(3) =>
3956 
                           btw7_8_28, input_fcs(4) => btw7_8_27, input_fcs(5)
3957 
                           => btw7_8_26, input_fcs(6) => btw7_8_25,
3958 
                           input_fcs(7) => btw7_8_24, input_fcs(8) => btw7_8_23
3959 
                           , input_fcs(9) => btw7_8_22, input_fcs(10) =>
3960 
                           btw7_8_21, input_fcs(11) => btw7_8_20, input_fcs(12)
3961 
                           => btw7_8_19, input_fcs(13) => btw7_8_18,
3962 
                           input_fcs(14) => btw7_8_17, input_fcs(15) =>
3963 
                           btw7_8_16, input_fcs(16) => btw7_8_15, input_fcs(17)
3964 
                           => btw7_8_14, input_fcs(18) => btw7_8_13,
3965 
                           input_fcs(19) => btw7_8_12, input_fcs(20) =>
3966 
                           btw7_8_11, input_fcs(21) => btw7_8_10, input_fcs(22)
3967 
                           => btw7_8_9, input_fcs(23) => btw7_8_8,
3968 
                           input_fcs(24) => btw7_8_7, input_fcs(25) => btw7_8_6
3969 
                           , input_fcs(26) => btw7_8_5, input_fcs(27) =>
3970 
                           btw7_8_4, input_fcs(28) => btw7_8_3, input_fcs(29)
3971 
                           => btw7_8_2, input_fcs(30) => btw7_8_1,
3972 
                           input_fcs(31) => btw7_8_0, output_wip(0) =>
3973 
                           btw8_8x_31, output_wip(1) => btw8_8x_30,
3974 
                           output_wip(2) => btw8_8x_29, output_wip(3) =>
3975 
                           btw8_8x_28, output_wip(4) => btw8_8x_27,
3976 
                           output_wip(5) => btw8_8x_26, output_wip(6) =>
3977 
                           btw8_8x_25, output_wip(7) => btw8_8x_24,
3978 
                           output_wip(8) => btw8_8x_23, output_wip(9) =>
3979 
                           btw8_8x_22, output_wip(10) => btw8_8x_21,
3980 
                           output_wip(11) => btw8_8x_20, output_wip(12) =>
3981 
                           btw8_8x_19, output_wip(13) => btw8_8x_18,
3982 
                           output_wip(14) => btw8_8x_17, output_wip(15) =>
3983 
                           btw8_8x_16, output_wip(16) => btw8_8x_15,
3984 
                           output_wip(17) => btw8_8x_14, output_wip(18) =>
3985 
                           btw8_8x_13, output_wip(19) => btw8_8x_12,
3986 
                           output_wip(20) => btw8_8x_11, output_wip(21) =>
3987 
                           btw8_8x_10, output_wip(22) => btw8_8x_9,
3988 
                           output_wip(23) => btw8_8x_8, output_wip(24) =>
3989 
                           btw8_8x_7, output_wip(25) => btw8_8x_6,
3990 
                           output_wip(26) => btw8_8x_5, output_wip(27) =>
3991 
                           btw8_8x_4, output_wip(28) => btw8_8x_3,
3992 
                           output_wip(29) => btw8_8x_2, output_wip(30) =>
3993 
                           btw8_8x_1, output_wip(31) => btw8_8x_0,
3994 
                           output_fcs(0) => btw8_9_31, output_fcs(1) =>
3995 
                           btw8_9_30, output_fcs(2) => btw8_9_29, output_fcs(3)
3996 
                           => btw8_9_28, output_fcs(4) => btw8_9_27,
3997 
                           output_fcs(5) => btw8_9_26, output_fcs(6) =>
3998 
                           btw8_9_25, output_fcs(7) => btw8_9_24, output_fcs(8)
3999 
                           => btw8_9_23, output_fcs(9) => btw8_9_22,
4000 
                           output_fcs(10) => btw8_9_21, output_fcs(11) =>
4001 
                           btw8_9_20, output_fcs(12) => btw8_9_19,
4002 
                           output_fcs(13) => btw8_9_18, output_fcs(14) =>
4003 
                           btw8_9_17, output_fcs(15) => btw8_9_16,
4004 
                           output_fcs(16) => btw8_9_15, output_fcs(17) =>
4005 
                           btw8_9_14, output_fcs(18) => btw8_9_13,
4006 
                           output_fcs(19) => btw8_9_12, output_fcs(20) =>
4007 
                           btw8_9_11, output_fcs(21) => btw8_9_10,
4008 
                           output_fcs(22) => btw8_9_9, output_fcs(23) =>
4009 
                           btw8_9_8, output_fcs(24) => btw8_9_7, output_fcs(25)
4010 
                           => btw8_9_6, output_fcs(26) => btw8_9_5,
4011 
                           output_fcs(27) => btw8_9_4, output_fcs(28) =>
4012 
                           btw8_9_3, output_fcs(29) => btw8_9_2, output_fcs(30)
4013 
                           => btw8_9_1, output_fcs(31) => btw8_9_0);
4014 
   GF6x : gf_xor_6x port map( input_wip(0) => btw6_6x_31, input_wip(1) =>
4015 
                           btw6_6x_30, input_wip(2) => btw6_6x_29, input_wip(3)
4016 
                           => btw6_6x_28, input_wip(4) => btw6_6x_27,
4017 
                           input_wip(5) => btw6_6x_26, input_wip(6) =>
4018 
                           btw6_6x_25, input_wip(7) => btw6_6x_24, input_wip(8)
4019 
                           => btw6_6x_23, input_wip(9) => btw6_6x_22,
4020 
                           input_wip(10) => btw6_6x_21, input_wip(11) =>
4021 
                           btw6_6x_20, input_wip(12) => btw6_6x_19,
4022 
                           input_wip(13) => btw6_6x_18, input_wip(14) =>
4023 
                           btw6_6x_17, input_wip(15) => btw6_6x_16,
4024 
                           input_wip(16) => btw6_6x_15, input_wip(17) =>
4025 
                           btw6_6x_14, input_wip(18) => btw6_6x_13,
4026 
                           input_wip(19) => btw6_6x_12, input_wip(20) =>
4027 
                           btw6_6x_11, input_wip(21) => btw6_6x_10,
4028 
                           input_wip(22) => btw6_6x_9, input_wip(23) =>
4029 
                           btw6_6x_8, input_wip(24) => btw6_6x_7, input_wip(25)
4030 
                           => btw6_6x_6, input_wip(26) => btw6_6x_5,
4031 
                           input_wip(27) => btw6_6x_4, input_wip(28) =>
4032 
                           btw6_6x_3, input_wip(29) => btw6_6x_2, input_wip(30)
4033 
                           => btw6_6x_1, input_wip(31) => btw6_6x_0,
4034 
                           input_fcs(0) => btw6_7_31, input_fcs(1) => btw6_7_30
4035 
                           , input_fcs(2) => btw6_7_29, input_fcs(3) =>
4036 
                           btw6_7_28, input_fcs(4) => btw6_7_27, input_fcs(5)
4037 
                           => btw6_7_26, input_fcs(6) => btw6_7_25,
4038 
                           input_fcs(7) => btw6_7_24, input_fcs(8) => btw6_7_23
4039 
                           , input_fcs(9) => btw6_7_22, input_fcs(10) =>
4040 
                           btw6_7_21, input_fcs(11) => btw6_7_20, input_fcs(12)
4041 
                           => btw6_7_19, input_fcs(13) => btw6_7_18,
4042 
                           input_fcs(14) => btw6_7_17, input_fcs(15) =>
4043 
                           btw6_7_16, input_fcs(16) => btw6_7_15, input_fcs(17)
4044 
                           => btw6_7_14, input_fcs(18) => btw6_7_13,
4045 
                           input_fcs(19) => btw6_7_12, input_fcs(20) =>
4046 
                           btw6_7_11, input_fcs(21) => btw6_7_10, input_fcs(22)
4047 
                           => btw6_7_9, input_fcs(23) => btw6_7_8,
4048 
                           input_fcs(24) => btw6_7_7, input_fcs(25) => btw6_7_6
4049 
                           , input_fcs(26) => btw6_7_5, input_fcs(27) =>
4050 
                           btw6_7_4, input_fcs(28) => btw6_7_3, input_fcs(29)
4051 
                           => btw6_7_2, input_fcs(30) => btw6_7_1,
4052 
                           input_fcs(31) => btw6_7_0, output_wip(0) =>
4053 
                           btw6x_7_31, output_wip(1) => btw6x_7_30,
4054 
                           output_wip(2) => btw6x_7_29, output_wip(3) =>
4055 
                           btw6x_7_28, output_wip(4) => btw6x_7_27,
4056 
                           output_wip(5) => btw6x_7_26, output_wip(6) =>
4057 
                           btw6x_7_25, output_wip(7) => btw6x_7_24,
4058 
                           output_wip(8) => btw6x_7_23, output_wip(9) =>
4059 
                           btw6x_7_22, output_wip(10) => btw6x_7_21,
4060 
                           output_wip(11) => btw6x_7_20, output_wip(12) =>
4061 
                           btw6x_7_19, output_wip(13) => btw6x_7_18,
4062 
                           output_wip(14) => btw6x_7_17, output_wip(15) =>
4063 
                           btw6x_7_16, output_wip(16) => btw6x_7_15,
4064 
                           output_wip(17) => btw6x_7_14, output_wip(18) =>
4065 
                           btw6x_7_13, output_wip(19) => btw6x_7_12,
4066 
                           output_wip(20) => btw6x_7_11, output_wip(21) =>
4067 
                           btw6x_7_10, output_wip(22) => btw6x_7_9,
4068 
                           output_wip(23) => btw6x_7_8, output_wip(24) =>
4069 
                           btw6x_7_7, output_wip(25) => btw6x_7_6,
4070 
                           output_wip(26) => btw6x_7_5, output_wip(27) =>
4071 
                           btw6x_7_4, output_wip(28) => btw6x_7_3,
4072 
                           output_wip(29) => btw6x_7_2, output_wip(30) =>
4073 
                           btw6x_7_1, output_wip(31) => btw6x_7_0);
4074 
   GF7 : gf_phi2_register_3 port map( reset => reset, phi2 => phi2,
4075 
                           input_wip(0) => btw6x_7_31, input_wip(1) =>
4076 
                           btw6x_7_30, input_wip(2) => btw6x_7_29, input_wip(3)
4077 
                           => btw6x_7_28, input_wip(4) => btw6x_7_27,
4078 
                           input_wip(5) => btw6x_7_26, input_wip(6) =>
4079 
                           btw6x_7_25, input_wip(7) => btw6x_7_24, input_wip(8)
4080 
                           => btw6x_7_23, input_wip(9) => btw6x_7_22,
4081 
                           input_wip(10) => btw6x_7_21, input_wip(11) =>
4082 
                           btw6x_7_20, input_wip(12) => btw6x_7_19,
4083 
                           input_wip(13) => btw6x_7_18, input_wip(14) =>
4084 
                           btw6x_7_17, input_wip(15) => btw6x_7_16,
4085 
                           input_wip(16) => btw6x_7_15, input_wip(17) =>
4086 
                           btw6x_7_14, input_wip(18) => btw6x_7_13,
4087 
                           input_wip(19) => btw6x_7_12, input_wip(20) =>
4088 
                           btw6x_7_11, input_wip(21) => btw6x_7_10,
4089 
                           input_wip(22) => btw6x_7_9, input_wip(23) =>
4090 
                           btw6x_7_8, input_wip(24) => btw6x_7_7, input_wip(25)
4091 
                           => btw6x_7_6, input_wip(26) => btw6x_7_5,
4092 
                           input_wip(27) => btw6x_7_4, input_wip(28) =>
4093 
                           btw6x_7_3, input_wip(29) => btw6x_7_2, input_wip(30)
4094 
                           => btw6x_7_1, input_wip(31) => btw6x_7_0,
4095 
                           input_fcs(0) => btw6_7_31, input_fcs(1) => btw6_7_30
4096 
                           , input_fcs(2) => btw6_7_29, input_fcs(3) =>
4097 
                           btw6_7_28, input_fcs(4) => btw6_7_27, input_fcs(5)
4098 
                           => btw6_7_26, input_fcs(6) => btw6_7_25,
4099 
                           input_fcs(7) => btw6_7_24, input_fcs(8) => btw6_7_23
4100 
                           , input_fcs(9) => btw6_7_22, input_fcs(10) =>
4101 
                           btw6_7_21, input_fcs(11) => btw6_7_20, input_fcs(12)
4102 
                           => btw6_7_19, input_fcs(13) => btw6_7_18,
4103 
                           input_fcs(14) => btw6_7_17, input_fcs(15) =>
4104 
                           btw6_7_16, input_fcs(16) => btw6_7_15, input_fcs(17)
4105 
                           => btw6_7_14, input_fcs(18) => btw6_7_13,
4106 
                           input_fcs(19) => btw6_7_12, input_fcs(20) =>
4107 
                           btw6_7_11, input_fcs(21) => btw6_7_10, input_fcs(22)
4108 
                           => btw6_7_9, input_fcs(23) => btw6_7_8,
4109 
                           input_fcs(24) => btw6_7_7, input_fcs(25) => btw6_7_6
4110 
                           , input_fcs(26) => btw6_7_5, input_fcs(27) =>
4111 
                           btw6_7_4, input_fcs(28) => btw6_7_3, input_fcs(29)
4112 
                           => btw6_7_2, input_fcs(30) => btw6_7_1,
4113 
                           input_fcs(31) => btw6_7_0, output_wip(0) =>
4114 
                           btw7_7x_31, output_wip(1) => btw7_7x_30,
4115 
                           output_wip(2) => btw7_7x_29, output_wip(3) =>
4116 
                           btw7_7x_28, output_wip(4) => btw7_7x_27,
4117 
                           output_wip(5) => btw7_7x_26, output_wip(6) =>
4118 
                           btw7_7x_25, output_wip(7) => btw7_7x_24,
4119 
                           output_wip(8) => btw7_7x_23, output_wip(9) =>
4120 
                           btw7_7x_22, output_wip(10) => btw7_7x_21,
4121 
                           output_wip(11) => btw7_7x_20, output_wip(12) =>
4122 
                           btw7_7x_19, output_wip(13) => btw7_7x_18,
4123 
                           output_wip(14) => btw7_7x_17, output_wip(15) =>
4124 
                           btw7_7x_16, output_wip(16) => btw7_7x_15,
4125 
                           output_wip(17) => btw7_7x_14, output_wip(18) =>
4126 
                           btw7_7x_13, output_wip(19) => btw7_7x_12,
4127 
                           output_wip(20) => btw7_7x_11, output_wip(21) =>
4128 
                           btw7_7x_10, output_wip(22) => btw7_7x_9,
4129 
                           output_wip(23) => btw7_7x_8, output_wip(24) =>
4130 
                           btw7_7x_7, output_wip(25) => btw7_7x_6,
4131 
                           output_wip(26) => btw7_7x_5, output_wip(27) =>
4132 
                           btw7_7x_4, output_wip(28) => btw7_7x_3,
4133 
                           output_wip(29) => btw7_7x_2, output_wip(30) =>
4134 
                           btw7_7x_1, output_wip(31) => btw7_7x_0,
4135 
                           output_fcs(0) => btw7_8_31, output_fcs(1) =>
4136 
                           btw7_8_30, output_fcs(2) => btw7_8_29, output_fcs(3)
4137 
                           => btw7_8_28, output_fcs(4) => btw7_8_27,
4138 
                           output_fcs(5) => btw7_8_26, output_fcs(6) =>
4139 
                           btw7_8_25, output_fcs(7) => btw7_8_24, output_fcs(8)
4140 
                           => btw7_8_23, output_fcs(9) => btw7_8_22,
4141 
                           output_fcs(10) => btw7_8_21, output_fcs(11) =>
4142 
                           btw7_8_20, output_fcs(12) => btw7_8_19,
4143 
                           output_fcs(13) => btw7_8_18, output_fcs(14) =>
4144 
                           btw7_8_17, output_fcs(15) => btw7_8_16,
4145 
                           output_fcs(16) => btw7_8_15, output_fcs(17) =>
4146 
                           btw7_8_14, output_fcs(18) => btw7_8_13,
4147 
                           output_fcs(19) => btw7_8_12, output_fcs(20) =>
4148 
                           btw7_8_11, output_fcs(21) => btw7_8_10,
4149 
                           output_fcs(22) => btw7_8_9, output_fcs(23) =>
4150 
                           btw7_8_8, output_fcs(24) => btw7_8_7, output_fcs(25)
4151 
                           => btw7_8_6, output_fcs(26) => btw7_8_5,
4152 
                           output_fcs(27) => btw7_8_4, output_fcs(28) =>
4153 
                           btw7_8_3, output_fcs(29) => btw7_8_2, output_fcs(30)
4154 
                           => btw7_8_1, output_fcs(31) => btw7_8_0);
4155 
   GF4x : gf_xor_4x port map( input_wip(0) => btw4_4x_31, input_wip(1) =>
4156 
                           btw4_4x_30, input_wip(2) => btw4_4x_29, input_wip(3)
4157 
                           => btw4_4x_28, input_wip(4) => btw4_4x_27,
4158 
                           input_wip(5) => btw4_4x_26, input_wip(6) =>
4159 
                           btw4_4x_25, input_wip(7) => btw4_4x_24, input_wip(8)
4160 
                           => btw4_4x_23, input_wip(9) => btw4_4x_22,
4161 
                           input_wip(10) => btw4_4x_21, input_wip(11) =>
4162 
                           btw4_4x_20, input_wip(12) => btw4_4x_19,
4163 
                           input_wip(13) => btw4_4x_18, input_wip(14) =>
4164 
                           btw4_4x_17, input_wip(15) => btw4_4x_16,
4165 
                           input_wip(16) => btw4_4x_15, input_wip(17) =>
4166 
                           btw4_4x_14, input_wip(18) => btw4_4x_13,
4167 
                           input_wip(19) => btw4_4x_12, input_wip(20) =>
4168 
                           btw4_4x_11, input_wip(21) => btw4_4x_10,
4169 
                           input_wip(22) => btw4_4x_9, input_wip(23) =>
4170 
                           btw4_4x_8, input_wip(24) => btw4_4x_7, input_wip(25)
4171 
                           => btw4_4x_6, input_wip(26) => btw4_4x_5,
4172 
                           input_wip(27) => btw4_4x_4, input_wip(28) =>
4173 
                           btw4_4x_3, input_wip(29) => btw4_4x_2, input_wip(30)
4174 
                           => btw4_4x_1, input_wip(31) => btw4_4x_0,
4175 
                           input_fcs(0) => btw4_5_31, input_fcs(1) => btw4_5_30
4176 
                           , input_fcs(2) => btw4_5_29, input_fcs(3) =>
4177 
                           btw4_5_28, input_fcs(4) => btw4_5_27, input_fcs(5)
4178 
                           => btw4_5_26, input_fcs(6) => btw4_5_25,
4179 
                           input_fcs(7) => btw4_5_24, input_fcs(8) => btw4_5_23
4180 
                           , input_fcs(9) => btw4_5_22, input_fcs(10) =>
4181 
                           btw4_5_21, input_fcs(11) => btw4_5_20, input_fcs(12)
4182 
                           => btw4_5_19, input_fcs(13) => btw4_5_18,
4183 
                           input_fcs(14) => btw4_5_17, input_fcs(15) =>
4184 
                           btw4_5_16, input_fcs(16) => btw4_5_15, input_fcs(17)
4185 
                           => btw4_5_14, input_fcs(18) => btw4_5_13,
4186 
                           input_fcs(19) => btw4_5_12, input_fcs(20) =>
4187 
                           btw4_5_11, input_fcs(21) => btw4_5_10, input_fcs(22)
4188 
                           => btw4_5_9, input_fcs(23) => btw4_5_8,
4189 
                           input_fcs(24) => btw4_5_7, input_fcs(25) => btw4_5_6
4190 
                           , input_fcs(26) => btw4_5_5, input_fcs(27) =>
4191 
                           btw4_5_4, input_fcs(28) => btw4_5_3, input_fcs(29)
4192 
                           => btw4_5_2, input_fcs(30) => btw4_5_1,
4193 
                           input_fcs(31) => btw4_5_0, output_wip(0) =>
4194 
                           btw4x_5_31, output_wip(1) => btw4x_5_30,
4195 
                           output_wip(2) => btw4x_5_29, output_wip(3) =>
4196 
                           btw4x_5_28, output_wip(4) => btw4x_5_27,
4197 
                           output_wip(5) => btw4x_5_26, output_wip(6) =>
4198 
                           btw4x_5_25, output_wip(7) => btw4x_5_24,
4199 
                           output_wip(8) => btw4x_5_23, output_wip(9) =>
4200 
                           btw4x_5_22, output_wip(10) => btw4x_5_21,
4201 
                           output_wip(11) => btw4x_5_20, output_wip(12) =>
4202 
                           btw4x_5_19, output_wip(13) => btw4x_5_18,
4203 
                           output_wip(14) => btw4x_5_17, output_wip(15) =>
4204 
                           btw4x_5_16, output_wip(16) => btw4x_5_15,
4205 
                           output_wip(17) => btw4x_5_14, output_wip(18) =>
4206 
                           btw4x_5_13, output_wip(19) => btw4x_5_12,
4207 
                           output_wip(20) => btw4x_5_11, output_wip(21) =>
4208 
                           btw4x_5_10, output_wip(22) => btw4x_5_9,
4209 
                           output_wip(23) => btw4x_5_8, output_wip(24) =>
4210 
                           btw4x_5_7, output_wip(25) => btw4x_5_6,
4211 
                           output_wip(26) => btw4x_5_5, output_wip(27) =>
4212 
                           btw4x_5_4, output_wip(28) => btw4x_5_3,
4213 
                           output_wip(29) => btw4x_5_2, output_wip(30) =>
4214 
                           btw4x_5_1, output_wip(31) => btw4x_5_0);
4215 
   GF9 : gf_phi2_register_2 port map( reset => reset, phi2 => phi2,
4216 
                           input_wip(0) => btw8x_9_31, input_wip(1) =>
4217 
                           btw8x_9_30, input_wip(2) => btw8x_9_29, input_wip(3)
4218 
                           => btw8x_9_28, input_wip(4) => btw8x_9_27,
4219 
                           input_wip(5) => btw8x_9_26, input_wip(6) =>
4220 
                           btw8x_9_25, input_wip(7) => btw8x_9_24, input_wip(8)
4221 
                           => btw8x_9_23, input_wip(9) => btw8x_9_22,
4222 
                           input_wip(10) => btw8x_9_21, input_wip(11) =>
4223 
                           btw8x_9_20, input_wip(12) => btw8x_9_19,
4224 
                           input_wip(13) => btw8x_9_18, input_wip(14) =>
4225 
                           btw8x_9_17, input_wip(15) => btw8x_9_16,
4226 
                           input_wip(16) => btw8x_9_15, input_wip(17) =>
4227 
                           btw8x_9_14, input_wip(18) => btw8x_9_13,
4228 
                           input_wip(19) => btw8x_9_12, input_wip(20) =>
4229 
                           btw8x_9_11, input_wip(21) => btw8x_9_10,
4230 
                           input_wip(22) => btw8x_9_9, input_wip(23) =>
4231 
                           btw8x_9_8, input_wip(24) => btw8x_9_7, input_wip(25)
4232 
                           => btw8x_9_6, input_wip(26) => btw8x_9_5,
4233 
                           input_wip(27) => btw8x_9_4, input_wip(28) =>
4234 
                           btw8x_9_3, input_wip(29) => btw8x_9_2, input_wip(30)
4235 
                           => btw8x_9_1, input_wip(31) => btw8x_9_0,
4236 
                           input_fcs(0) => btw8_9_31, input_fcs(1) => btw8_9_30
4237 
                           , input_fcs(2) => btw8_9_29, input_fcs(3) =>
4238 
                           btw8_9_28, input_fcs(4) => btw8_9_27, input_fcs(5)
4239 
                           => btw8_9_26, input_fcs(6) => btw8_9_25,
4240 
                           input_fcs(7) => btw8_9_24, input_fcs(8) => btw8_9_23
4241 
                           , input_fcs(9) => btw8_9_22, input_fcs(10) =>
4242 
                           btw8_9_21, input_fcs(11) => btw8_9_20, input_fcs(12)
4243 
                           => btw8_9_19, input_fcs(13) => btw8_9_18,
4244 
                           input_fcs(14) => btw8_9_17, input_fcs(15) =>
4245 
                           btw8_9_16, input_fcs(16) => btw8_9_15, input_fcs(17)
4246 
                           => btw8_9_14, input_fcs(18) => btw8_9_13,
4247 
                           input_fcs(19) => btw8_9_12, input_fcs(20) =>
4248 
                           btw8_9_11, input_fcs(21) => btw8_9_10, input_fcs(22)
4249 
                           => btw8_9_9, input_fcs(23) => btw8_9_8,
4250 
                           input_fcs(24) => btw8_9_7, input_fcs(25) => btw8_9_6
4251 
                           , input_fcs(26) => btw8_9_5, input_fcs(27) =>
4252 
                           btw8_9_4, input_fcs(28) => btw8_9_3, input_fcs(29)
4253 
                           => btw8_9_2, input_fcs(30) => btw8_9_1,
4254 
                           input_fcs(31) => btw8_9_0, output_wip(0) =>
4255 
                           btw9_9x_31, output_wip(1) => btw9_9x_30,
4256 
                           output_wip(2) => btw9_9x_29, output_wip(3) =>
4257 
                           btw9_9x_28, output_wip(4) => btw9_9x_27,
4258 
                           output_wip(5) => btw9_9x_26, output_wip(6) =>
4259 
                           btw9_9x_25, output_wip(7) => btw9_9x_24,
4260 
                           output_wip(8) => btw9_9x_23, output_wip(9) =>
4261 
                           btw9_9x_22, output_wip(10) => btw9_9x_21,
4262 
                           output_wip(11) => btw9_9x_20, output_wip(12) =>
4263 
                           btw9_9x_19, output_wip(13) => btw9_9x_18,
4264 
                           output_wip(14) => btw9_9x_17, output_wip(15) =>
4265 
                           btw9_9x_16, output_wip(16) => btw9_9x_15,
4266 
                           output_wip(17) => btw9_9x_14, output_wip(18) =>
4267 
                           btw9_9x_13, output_wip(19) => btw9_9x_12,
4268 
                           output_wip(20) => btw9_9x_11, output_wip(21) =>
4269 
                           btw9_9x_10, output_wip(22) => btw9_9x_9,
4270 
                           output_wip(23) => btw9_9x_8, output_wip(24) =>
4271 
                           btw9_9x_7, output_wip(25) => btw9_9x_6,
4272 
                           output_wip(26) => btw9_9x_5, output_wip(27) =>
4273 
                           btw9_9x_4, output_wip(28) => btw9_9x_3,
4274 
                           output_wip(29) => btw9_9x_2, output_wip(30) =>
4275 
                           btw9_9x_1, output_wip(31) => btw9_9x_0,
4276 
                           output_fcs(0) => btw9_10_31, output_fcs(1) =>
4277 
                           btw9_10_30, output_fcs(2) => btw9_10_29,
4278 
                           output_fcs(3) => btw9_10_28, output_fcs(4) =>
4279 
                           btw9_10_27, output_fcs(5) => btw9_10_26,
4280 
                           output_fcs(6) => btw9_10_25, output_fcs(7) =>
4281 
                           btw9_10_24, output_fcs(8) => btw9_10_23,
4282 
                           output_fcs(9) => btw9_10_22, output_fcs(10) =>
4283 
                           btw9_10_21, output_fcs(11) => btw9_10_20,
4284 
                           output_fcs(12) => btw9_10_19, output_fcs(13) =>
4285 
                           btw9_10_18, output_fcs(14) => btw9_10_17,
4286 
                           output_fcs(15) => btw9_10_16, output_fcs(16) =>
4287 
                           btw9_10_15, output_fcs(17) => btw9_10_14,
4288 
                           output_fcs(18) => btw9_10_13, output_fcs(19) =>
4289 
                           btw9_10_12, output_fcs(20) => btw9_10_11,
4290 
                           output_fcs(21) => btw9_10_10, output_fcs(22) =>
4291 
                           btw9_10_9, output_fcs(23) => btw9_10_8,
4292 
                           output_fcs(24) => btw9_10_7, output_fcs(25) =>
4293 
                           btw9_10_6, output_fcs(26) => btw9_10_5,
4294 
                           output_fcs(27) => btw9_10_4, output_fcs(28) =>
4295 
                           btw9_10_3, output_fcs(29) => btw9_10_2,
4296 
                           output_fcs(30) => btw9_10_1, output_fcs(31) =>
4297 
                           btw9_10_0);
4298 
   GF9x : gf_xor_9x port map( input_wip(0) => btw9_9x_31, input_wip(1) =>
4299 
                           btw9_9x_30, input_wip(2) => btw9_9x_29, input_wip(3)
4300 
                           => btw9_9x_28, input_wip(4) => btw9_9x_27,
4301 
                           input_wip(5) => btw9_9x_26, input_wip(6) =>
4302 
                           btw9_9x_25, input_wip(7) => btw9_9x_24, input_wip(8)
4303 
                           => btw9_9x_23, input_wip(9) => btw9_9x_22,
4304 
                           input_wip(10) => btw9_9x_21, input_wip(11) =>
4305 
                           btw9_9x_20, input_wip(12) => btw9_9x_19,
4306 
                           input_wip(13) => btw9_9x_18, input_wip(14) =>
4307 
                           btw9_9x_17, input_wip(15) => btw9_9x_16,
4308 
                           input_wip(16) => btw9_9x_15, input_wip(17) =>
4309 
                           btw9_9x_14, input_wip(18) => btw9_9x_13,
4310 
                           input_wip(19) => btw9_9x_12, input_wip(20) =>
4311 
                           btw9_9x_11, input_wip(21) => btw9_9x_10,
4312 
                           input_wip(22) => btw9_9x_9, input_wip(23) =>
4313 
                           btw9_9x_8, input_wip(24) => btw9_9x_7, input_wip(25)
4314 
                           => btw9_9x_6, input_wip(26) => btw9_9x_5,
4315 
                           input_wip(27) => btw9_9x_4, input_wip(28) =>
4316 
                           btw9_9x_3, input_wip(29) => btw9_9x_2, input_wip(30)
4317 
                           => btw9_9x_1, input_wip(31) => btw9_9x_0,
4318 
                           input_fcs(0) => btw9_10_31, input_fcs(1) =>
4319 
                           btw9_10_30, input_fcs(2) => btw9_10_29, input_fcs(3)
4320 
                           => btw9_10_28, input_fcs(4) => btw9_10_27,
4321 
                           input_fcs(5) => btw9_10_26, input_fcs(6) =>
4322 
                           btw9_10_25, input_fcs(7) => btw9_10_24, input_fcs(8)
4323 
                           => btw9_10_23, input_fcs(9) => btw9_10_22,
4324 
                           input_fcs(10) => btw9_10_21, input_fcs(11) =>
4325 
                           btw9_10_20, input_fcs(12) => btw9_10_19,
4326 
                           input_fcs(13) => btw9_10_18, input_fcs(14) =>
4327 
                           btw9_10_17, input_fcs(15) => btw9_10_16,
4328 
                           input_fcs(16) => btw9_10_15, input_fcs(17) =>
4329 
                           btw9_10_14, input_fcs(18) => btw9_10_13,
4330 
                           input_fcs(19) => btw9_10_12, input_fcs(20) =>
4331 
                           btw9_10_11, input_fcs(21) => btw9_10_10,
4332 
                           input_fcs(22) => btw9_10_9, input_fcs(23) =>
4333 
                           btw9_10_8, input_fcs(24) => btw9_10_7, input_fcs(25)
4334 
                           => btw9_10_6, input_fcs(26) => btw9_10_5,
4335 
                           input_fcs(27) => btw9_10_4, input_fcs(28) =>
4336 
                           btw9_10_3, input_fcs(29) => btw9_10_2, input_fcs(30)
4337 
                           => btw9_10_1, input_fcs(31) => btw9_10_0,
4338 
                           output_wip(0) => btw9x_10_31, output_wip(1) =>
4339 
                           btw9x_10_30, output_wip(2) => btw9x_10_29,
4340 
                           output_wip(3) => btw9x_10_28, output_wip(4) =>
4341 
                           btw9x_10_27, output_wip(5) => btw9x_10_26,
4342 
                           output_wip(6) => btw9x_10_25, output_wip(7) =>
4343 
                           btw9x_10_24, output_wip(8) => btw9x_10_23,
4344 
                           output_wip(9) => btw9x_10_22, output_wip(10) =>
4345 
                           btw9x_10_21, output_wip(11) => btw9x_10_20,
4346 
                           output_wip(12) => btw9x_10_19, output_wip(13) =>
4347 
                           btw9x_10_18, output_wip(14) => btw9x_10_17,
4348 
                           output_wip(15) => btw9x_10_16, output_wip(16) =>
4349 
                           btw9x_10_15, output_wip(17) => btw9x_10_14,
4350 
                           output_wip(18) => btw9x_10_13, output_wip(19) =>
4351 
                           btw9x_10_12, output_wip(20) => btw9x_10_11,
4352 
                           output_wip(21) => btw9x_10_10, output_wip(22) =>
4353 
                           btw9x_10_9, output_wip(23) => btw9x_10_8,
4354 
                           output_wip(24) => btw9x_10_7, output_wip(25) =>
4355 
                           btw9x_10_6, output_wip(26) => btw9x_10_5,
4356 
                           output_wip(27) => btw9x_10_4, output_wip(28) =>
4357 
                           btw9x_10_3, output_wip(29) => btw9x_10_2,
4358 
                           output_wip(30) => btw9x_10_1, output_wip(31) =>
4359 
                           btw9x_10_0);
4360 
   GF5x : gf_xor_5x port map( input_wip(0) => btw5_5x_31, input_wip(1) =>
4361 
                           btw5_5x_30, input_wip(2) => btw5_5x_29, input_wip(3)
4362 
                           => btw5_5x_28, input_wip(4) => btw5_5x_27,
4363 
                           input_wip(5) => btw5_5x_26, input_wip(6) =>
4364 
                           btw5_5x_25, input_wip(7) => btw5_5x_24, input_wip(8)
4365 
                           => btw5_5x_23, input_wip(9) => btw5_5x_22,
4366 
                           input_wip(10) => btw5_5x_21, input_wip(11) =>
4367 
                           btw5_5x_20, input_wip(12) => btw5_5x_19,
4368 
                           input_wip(13) => btw5_5x_18, input_wip(14) =>
4369 
                           btw5_5x_17, input_wip(15) => btw5_5x_16,
4370 
                           input_wip(16) => btw5_5x_15, input_wip(17) =>
4371 
                           btw5_5x_14, input_wip(18) => btw5_5x_13,
4372 
                           input_wip(19) => btw5_5x_12, input_wip(20) =>
4373 
                           btw5_5x_11, input_wip(21) => btw5_5x_10,
4374 
                           input_wip(22) => btw5_5x_9, input_wip(23) =>
4375 
                           btw5_5x_8, input_wip(24) => btw5_5x_7, input_wip(25)
4376 
                           => btw5_5x_6, input_wip(26) => btw5_5x_5,
4377 
                           input_wip(27) => btw5_5x_4, input_wip(28) =>
4378 
                           btw5_5x_3, input_wip(29) => btw5_5x_2, input_wip(30)
4379 
                           => btw5_5x_1, input_wip(31) => btw5_5x_0,
4380 
                           input_fcs(0) => btw5_6_31, input_fcs(1) => btw5_6_30
4381 
                           , input_fcs(2) => btw5_6_29, input_fcs(3) =>
4382 
                           btw5_6_28, input_fcs(4) => btw5_6_27, input_fcs(5)
4383 
                           => btw5_6_26, input_fcs(6) => btw5_6_25,
4384 
                           input_fcs(7) => btw5_6_24, input_fcs(8) => btw5_6_23
4385 
                           , input_fcs(9) => btw5_6_22, input_fcs(10) =>
4386 
                           btw5_6_21, input_fcs(11) => btw5_6_20, input_fcs(12)
4387 
                           => btw5_6_19, input_fcs(13) => btw5_6_18,
4388 
                           input_fcs(14) => btw5_6_17, input_fcs(15) =>
4389 
                           btw5_6_16, input_fcs(16) => btw5_6_15, input_fcs(17)
4390 
                           => btw5_6_14, input_fcs(18) => btw5_6_13,
4391 
                           input_fcs(19) => btw5_6_12, input_fcs(20) =>
4392 
                           btw5_6_11, input_fcs(21) => btw5_6_10, input_fcs(22)
4393 
                           => btw5_6_9, input_fcs(23) => btw5_6_8,
4394 
                           input_fcs(24) => btw5_6_7, input_fcs(25) => btw5_6_6
4395 
                           , input_fcs(26) => btw5_6_5, input_fcs(27) =>
4396 
                           btw5_6_4, input_fcs(28) => btw5_6_3, input_fcs(29)
4397 
                           => btw5_6_2, input_fcs(30) => btw5_6_1,
4398 
                           input_fcs(31) => btw5_6_0, output_wip(0) =>
4399 
                           btw5x_6_31, output_wip(1) => btw5x_6_30,
4400 
                           output_wip(2) => btw5x_6_29, output_wip(3) =>
4401 
                           btw5x_6_28, output_wip(4) => btw5x_6_27,
4402 
                           output_wip(5) => btw5x_6_26, output_wip(6) =>
4403 
                           btw5x_6_25, output_wip(7) => btw5x_6_24,
4404 
                           output_wip(8) => btw5x_6_23, output_wip(9) =>
4405 
                           btw5x_6_22, output_wip(10) => btw5x_6_21,
4406 
                           output_wip(11) => btw5x_6_20, output_wip(12) =>
4407 
                           btw5x_6_19, output_wip(13) => btw5x_6_18,
4408 
                           output_wip(14) => btw5x_6_17, output_wip(15) =>
4409 
                           btw5x_6_16, output_wip(16) => btw5x_6_15,
4410 
                           output_wip(17) => btw5x_6_14, output_wip(18) =>
4411 
                           btw5x_6_13, output_wip(19) => btw5x_6_12,
4412 
                           output_wip(20) => btw5x_6_11, output_wip(21) =>
4413 
                           btw5x_6_10, output_wip(22) => btw5x_6_9,
4414 
                           output_wip(23) => btw5x_6_8, output_wip(24) =>
4415 
                           btw5x_6_7, output_wip(25) => btw5x_6_6,
4416 
                           output_wip(26) => btw5x_6_5, output_wip(27) =>
4417 
                           btw5x_6_4, output_wip(28) => btw5x_6_3,
4418 
                           output_wip(29) => btw5x_6_2, output_wip(30) =>
4419 
                           btw5x_6_1, output_wip(31) => btw5x_6_0);
4420 
   GF2 : gf_phi1_register_1 port map( reset => reset, phi1 => phi1,
4421 
                           input_wip(0) => btw1x_2_31, input_wip(1) =>
4422 
                           btw1x_2_30, input_wip(2) => btw1x_2_29, input_wip(3)
4423 
                           => btw1x_2_28, input_wip(4) => btw1x_2_27,
4424 
                           input_wip(5) => btw1x_2_26, input_wip(6) =>
4425 
                           btw1x_2_25, input_wip(7) => btw1x_2_24, input_wip(8)
4426 
                           => btw1x_2_23, input_wip(9) => btw1x_2_22,
4427 
                           input_wip(10) => btw1x_2_21, input_wip(11) =>
4428 
                           btw1x_2_20, input_wip(12) => btw1x_2_19,
4429 
                           input_wip(13) => btw1x_2_18, input_wip(14) =>
4430 
                           btw1x_2_17, input_wip(15) => btw1x_2_16,
4431 
                           input_wip(16) => btw1x_2_15, input_wip(17) =>
4432 
                           btw1x_2_14, input_wip(18) => btw1x_2_13,
4433 
                           input_wip(19) => btw1x_2_12, input_wip(20) =>
4434 
                           btw1x_2_11, input_wip(21) => btw1x_2_10,
4435 
                           input_wip(22) => btw1x_2_9, input_wip(23) =>
4436 
                           btw1x_2_8, input_wip(24) => btw1x_2_7, input_wip(25)
4437 
                           => btw1x_2_6, input_wip(26) => btw1x_2_5,
4438 
                           input_wip(27) => btw1x_2_4, input_wip(28) =>
4439 
                           btw1x_2_3, input_wip(29) => btw1x_2_2, input_wip(30)
4440 
                           => btw1x_2_1, input_wip(31) => btw1x_2_0,
4441 
                           input_fcs(0) => input(0), input_fcs(1) => input(1),
4442 
                           input_fcs(2) => input(2), input_fcs(3) => input(3),
4443 
                           input_fcs(4) => input(4), input_fcs(5) => input(5),
4444 
                           input_fcs(6) => input(6), input_fcs(7) => input(7),
4445 
                           input_fcs(8) => input(8), input_fcs(9) => input(9),
4446 
                           input_fcs(10) => input(10), input_fcs(11) =>
4447 
                           input(11), input_fcs(12) => input(12), input_fcs(13)
4448 
                           => input(13), input_fcs(14) => input(14),
4449 
                           input_fcs(15) => input(15), input_fcs(16) =>
4450 
                           input(16), input_fcs(17) => input(17), input_fcs(18)
4451 
                           => input(18), input_fcs(19) => input(19),
4452 
                           input_fcs(20) => input(20), input_fcs(21) =>
4453 
                           input(21), input_fcs(22) => input(22), input_fcs(23)
4454 
                           => input(23), input_fcs(24) => input(24),
4455 
                           input_fcs(25) => input(25), input_fcs(26) =>
4456 
                           input(26), input_fcs(27) => input(27), input_fcs(28)
4457 
                           => input(28), input_fcs(29) => input(29),
4458 
                           input_fcs(30) => input(30), input_fcs(31) =>
4459 
                           input(31), output_wip(0) => btw2_2x_31,
4460 
                           output_wip(1) => btw2_2x_30, output_wip(2) =>
4461 
                           btw2_2x_29, output_wip(3) => btw2_2x_28,
4462 
                           output_wip(4) => btw2_2x_27, output_wip(5) =>
4463 
                           btw2_2x_26, output_wip(6) => btw2_2x_25,
4464 
                           output_wip(7) => btw2_2x_24, output_wip(8) =>
4465 
                           btw2_2x_23, output_wip(9) => btw2_2x_22,
4466 
                           output_wip(10) => btw2_2x_21, output_wip(11) =>
4467 
                           btw2_2x_20, output_wip(12) => btw2_2x_19,
4468 
                           output_wip(13) => btw2_2x_18, output_wip(14) =>
4469 
                           btw2_2x_17, output_wip(15) => btw2_2x_16,
4470 
                           output_wip(16) => btw2_2x_15, output_wip(17) =>
4471 
                           btw2_2x_14, output_wip(18) => btw2_2x_13,
4472 
                           output_wip(19) => btw2_2x_12, output_wip(20) =>
4473 
                           btw2_2x_11, output_wip(21) => btw2_2x_10,
4474 
                           output_wip(22) => btw2_2x_9, output_wip(23) =>
4475 
                           btw2_2x_8, output_wip(24) => btw2_2x_7,
4476 
                           output_wip(25) => btw2_2x_6, output_wip(26) =>
4477 
                           btw2_2x_5, output_wip(27) => btw2_2x_4,
4478 
                           output_wip(28) => btw2_2x_3, output_wip(29) =>
4479 
                           btw2_2x_2, output_wip(30) => btw2_2x_1,
4480 
                           output_wip(31) => btw2_2x_0, output_fcs(0) =>
4481 
                           btw2_3_31, output_fcs(1) => btw2_3_30, output_fcs(2)
4482 
                           => btw2_3_29, output_fcs(3) => btw2_3_28,
4483 
                           output_fcs(4) => btw2_3_27, output_fcs(5) =>
4484 
                           btw2_3_26, output_fcs(6) => btw2_3_25, output_fcs(7)
4485 
                           => btw2_3_24, output_fcs(8) => btw2_3_23,
4486 
                           output_fcs(9) => btw2_3_22, output_fcs(10) =>
4487 
                           btw2_3_21, output_fcs(11) => btw2_3_20,
4488 
                           output_fcs(12) => btw2_3_19, output_fcs(13) =>
4489 
                           btw2_3_18, output_fcs(14) => btw2_3_17,
4490 
                           output_fcs(15) => btw2_3_16, output_fcs(16) =>
4491 
                           btw2_3_15, output_fcs(17) => btw2_3_14,
4492 
                           output_fcs(18) => btw2_3_13, output_fcs(19) =>
4493 
                           btw2_3_12, output_fcs(20) => btw2_3_11,
4494 
                           output_fcs(21) => btw2_3_10, output_fcs(22) =>
4495 
                           btw2_3_9, output_fcs(23) => btw2_3_8, output_fcs(24)
4496 
                           => btw2_3_7, output_fcs(25) => btw2_3_6,
4497 
                           output_fcs(26) => btw2_3_5, output_fcs(27) =>
4498 
                           btw2_3_4, output_fcs(28) => btw2_3_3, output_fcs(29)
4499 
                           => btw2_3_2, output_fcs(30) => btw2_3_1,
4500 
                           output_fcs(31) => btw2_3_0);
4501 
   GF3 : gf_phi2_register_1 port map( reset => reset, phi2 => phi2,
4502 
                           input_wip(0) => btw2x_3_31, input_wip(1) =>
4503 
                           btw2x_3_30, input_wip(2) => btw2x_3_29, input_wip(3)
4504 
                           => btw2x_3_28, input_wip(4) => btw2x_3_27,
4505 
                           input_wip(5) => btw2x_3_26, input_wip(6) =>
4506 
                           btw2x_3_25, input_wip(7) => btw2x_3_24, input_wip(8)
4507 
                           => btw2x_3_23, input_wip(9) => btw2x_3_22,
4508 
                           input_wip(10) => btw2x_3_21, input_wip(11) =>
4509 
                           btw2x_3_20, input_wip(12) => btw2x_3_19,
4510 
                           input_wip(13) => btw2x_3_18, input_wip(14) =>
4511 
                           btw2x_3_17, input_wip(15) => btw2x_3_16,
4512 
                           input_wip(16) => btw2x_3_15, input_wip(17) =>
4513 
                           btw2x_3_14, input_wip(18) => btw2x_3_13,
4514 
                           input_wip(19) => btw2x_3_12, input_wip(20) =>
4515 
                           btw2x_3_11, input_wip(21) => btw2x_3_10,
4516 
                           input_wip(22) => btw2x_3_9, input_wip(23) =>
4517 
                           btw2x_3_8, input_wip(24) => btw2x_3_7, input_wip(25)
4518 
                           => btw2x_3_6, input_wip(26) => btw2x_3_5,
4519 
                           input_wip(27) => btw2x_3_4, input_wip(28) =>
4520 
                           btw2x_3_3, input_wip(29) => btw2x_3_2, input_wip(30)
4521 
                           => btw2x_3_1, input_wip(31) => btw2x_3_0,
4522 
                           input_fcs(0) => btw2_3_31, input_fcs(1) => btw2_3_30
4523 
                           , input_fcs(2) => btw2_3_29, input_fcs(3) =>
4524 
                           btw2_3_28, input_fcs(4) => btw2_3_27, input_fcs(5)
4525 
                           => btw2_3_26, input_fcs(6) => btw2_3_25,
4526 
                           input_fcs(7) => btw2_3_24, input_fcs(8) => btw2_3_23
4527 
                           , input_fcs(9) => btw2_3_22, input_fcs(10) =>
4528 
                           btw2_3_21, input_fcs(11) => btw2_3_20, input_fcs(12)
4529 
                           => btw2_3_19, input_fcs(13) => btw2_3_18,
4530 
                           input_fcs(14) => btw2_3_17, input_fcs(15) =>
4531 
                           btw2_3_16, input_fcs(16) => btw2_3_15, input_fcs(17)
4532 
                           => btw2_3_14, input_fcs(18) => btw2_3_13,
4533 
                           input_fcs(19) => btw2_3_12, input_fcs(20) =>
4534 
                           btw2_3_11, input_fcs(21) => btw2_3_10, input_fcs(22)
4535 
                           => btw2_3_9, input_fcs(23) => btw2_3_8,
4536 
                           input_fcs(24) => btw2_3_7, input_fcs(25) => btw2_3_6
4537 
                           , input_fcs(26) => btw2_3_5, input_fcs(27) =>
4538 
                           btw2_3_4, input_fcs(28) => btw2_3_3, input_fcs(29)
4539 
                           => btw2_3_2, input_fcs(30) => btw2_3_1,
4540 
                           input_fcs(31) => btw2_3_0, output_wip(0) =>
4541 
                           btw3_3x_31, output_wip(1) => btw3_3x_30,
4542 
                           output_wip(2) => btw3_3x_29, output_wip(3) =>
4543 
                           btw3_3x_28, output_wip(4) => btw3_3x_27,
4544 
                           output_wip(5) => btw3_3x_26, output_wip(6) =>
4545 
                           btw3_3x_25, output_wip(7) => btw3_3x_24,
4546 
                           output_wip(8) => btw3_3x_23, output_wip(9) =>
4547 
                           btw3_3x_22, output_wip(10) => btw3_3x_21,
4548 
                           output_wip(11) => btw3_3x_20, output_wip(12) =>
4549 
                           btw3_3x_19, output_wip(13) => btw3_3x_18,
4550 
                           output_wip(14) => btw3_3x_17, output_wip(15) =>
4551 
                           btw3_3x_16, output_wip(16) => btw3_3x_15,
4552 
                           output_wip(17) => btw3_3x_14, output_wip(18) =>
4553 
                           btw3_3x_13, output_wip(19) => btw3_3x_12,
4554 
                           output_wip(20) => btw3_3x_11, output_wip(21) =>
4555 
                           btw3_3x_10, output_wip(22) => btw3_3x_9,
4556 
                           output_wip(23) => btw3_3x_8, output_wip(24) =>
4557 
                           btw3_3x_7, output_wip(25) => btw3_3x_6,
4558 
                           output_wip(26) => btw3_3x_5, output_wip(27) =>
4559 
                           btw3_3x_4, output_wip(28) => btw3_3x_3,
4560 
                           output_wip(29) => btw3_3x_2, output_wip(30) =>
4561 
                           btw3_3x_1, output_wip(31) => btw3_3x_0,
4562 
                           output_fcs(0) => btw3_4_31, output_fcs(1) =>
4563 
                           btw3_4_30, output_fcs(2) => btw3_4_29, output_fcs(3)
4564 
                           => btw3_4_28, output_fcs(4) => btw3_4_27,
4565 
                           output_fcs(5) => btw3_4_26, output_fcs(6) =>
4566 
                           btw3_4_25, output_fcs(7) => btw3_4_24, output_fcs(8)
4567 
                           => btw3_4_23, output_fcs(9) => btw3_4_22,
4568 
                           output_fcs(10) => btw3_4_21, output_fcs(11) =>
4569 
                           btw3_4_20, output_fcs(12) => btw3_4_19,
4570 
                           output_fcs(13) => btw3_4_18, output_fcs(14) =>
4571 
                           btw3_4_17, output_fcs(15) => btw3_4_16,
4572 
                           output_fcs(16) => btw3_4_15, output_fcs(17) =>
4573 
                           btw3_4_14, output_fcs(18) => btw3_4_13,
4574 
                           output_fcs(19) => btw3_4_12, output_fcs(20) =>
4575 
                           btw3_4_11, output_fcs(21) => btw3_4_10,
4576 
                           output_fcs(22) => btw3_4_9, output_fcs(23) =>
4577 
                           btw3_4_8, output_fcs(24) => btw3_4_7, output_fcs(25)
4578 
                           => btw3_4_6, output_fcs(26) => btw3_4_5,
4579 
                           output_fcs(27) => btw3_4_4, output_fcs(28) =>
4580 
                           btw3_4_3, output_fcs(29) => btw3_4_2, output_fcs(30)
4581 
                           => btw3_4_1, output_fcs(31) => btw3_4_0);
4582 
   GF3x : gf_xor_3x port map( input_wip(0) => btw3_3x_31, input_wip(1) =>
4583 
                           btw3_3x_30, input_wip(2) => btw3_3x_29, input_wip(3)
4584 
                           => btw3_3x_28, input_wip(4) => btw3_3x_27,
4585 
                           input_wip(5) => btw3_3x_26, input_wip(6) =>
4586 
                           btw3_3x_25, input_wip(7) => btw3_3x_24, input_wip(8)
4587 
                           => btw3_3x_23, input_wip(9) => btw3_3x_22,
4588 
                           input_wip(10) => btw3_3x_21, input_wip(11) =>
4589 
                           btw3_3x_20, input_wip(12) => btw3_3x_19,
4590 
                           input_wip(13) => btw3_3x_18, input_wip(14) =>
4591 
                           btw3_3x_17, input_wip(15) => btw3_3x_16,
4592 
                           input_wip(16) => btw3_3x_15, input_wip(17) =>
4593 
                           btw3_3x_14, input_wip(18) => btw3_3x_13,
4594 
                           input_wip(19) => btw3_3x_12, input_wip(20) =>
4595 
                           btw3_3x_11, input_wip(21) => btw3_3x_10,
4596 
                           input_wip(22) => btw3_3x_9, input_wip(23) =>
4597 
                           btw3_3x_8, input_wip(24) => btw3_3x_7, input_wip(25)
4598 
                           => btw3_3x_6, input_wip(26) => btw3_3x_5,
4599 
                           input_wip(27) => btw3_3x_4, input_wip(28) =>
4600 
                           btw3_3x_3, input_wip(29) => btw3_3x_2, input_wip(30)
4601 
                           => btw3_3x_1, input_wip(31) => btw3_3x_0,
4602 
                           input_fcs(0) => btw3_4_31, input_fcs(1) => btw3_4_30
4603 
                           , input_fcs(2) => btw3_4_29, input_fcs(3) =>
4604 
                           btw3_4_28, input_fcs(4) => btw3_4_27, input_fcs(5)
4605 
                           => btw3_4_26, input_fcs(6) => btw3_4_25,
4606 
                           input_fcs(7) => btw3_4_24, input_fcs(8) => btw3_4_23
4607 
                           , input_fcs(9) => btw3_4_22, input_fcs(10) =>
4608 
                           btw3_4_21, input_fcs(11) => btw3_4_20, input_fcs(12)
4609 
                           => btw3_4_19, input_fcs(13) => btw3_4_18,
4610 
                           input_fcs(14) => btw3_4_17, input_fcs(15) =>
4611 
                           btw3_4_16, input_fcs(16) => btw3_4_15, input_fcs(17)
4612 
                           => btw3_4_14, input_fcs(18) => btw3_4_13,
4613 
                           input_fcs(19) => btw3_4_12, input_fcs(20) =>
4614 
                           btw3_4_11, input_fcs(21) => btw3_4_10, input_fcs(22)
4615 
                           => btw3_4_9, input_fcs(23) => btw3_4_8,
4616 
                           input_fcs(24) => btw3_4_7, input_fcs(25) => btw3_4_6
4617 
                           , input_fcs(26) => btw3_4_5, input_fcs(27) =>
4618 
                           btw3_4_4, input_fcs(28) => btw3_4_3, input_fcs(29)
4619 
                           => btw3_4_2, input_fcs(30) => btw3_4_1,
4620 
                           input_fcs(31) => btw3_4_0, output_wip(0) =>
4621 
                           btw3x_4_31, output_wip(1) => btw3x_4_30,
4622 
                           output_wip(2) => btw3x_4_29, output_wip(3) =>
4623 
                           btw3x_4_28, output_wip(4) => btw3x_4_27,
4624 
                           output_wip(5) => btw3x_4_26, output_wip(6) =>
4625 
                           btw3x_4_25, output_wip(7) => btw3x_4_24,
4626 
                           output_wip(8) => btw3x_4_23, output_wip(9) =>
4627 
                           btw3x_4_22, output_wip(10) => btw3x_4_21,
4628 
                           output_wip(11) => btw3x_4_20, output_wip(12) =>
4629 
                           btw3x_4_19, output_wip(13) => btw3x_4_18,
4630 
                           output_wip(14) => btw3x_4_17, output_wip(15) =>
4631 
                           btw3x_4_16, output_wip(16) => btw3x_4_15,
4632 
                           output_wip(17) => btw3x_4_14, output_wip(18) =>
4633 
                           btw3x_4_13, output_wip(19) => btw3x_4_12,
4634 
                           output_wip(20) => btw3x_4_11, output_wip(21) =>
4635 
                           btw3x_4_10, output_wip(22) => btw3x_4_9,
4636 
                           output_wip(23) => btw3x_4_8, output_wip(24) =>
4637 
                           btw3x_4_7, output_wip(25) => btw3x_4_6,
4638 
                           output_wip(26) => btw3x_4_5, output_wip(27) =>
4639 
                           btw3x_4_4, output_wip(28) => btw3x_4_3,
4640 
                           output_wip(29) => btw3x_4_2, output_wip(30) =>
4641 
                           btw3x_4_1, output_wip(31) => btw3x_4_0);
4642 
   GF5 : gf_phi2_register_0 port map( reset => reset, phi2 => phi2,
4643 
                           input_wip(0) => btw4x_5_31, input_wip(1) =>
4644 
                           btw4x_5_30, input_wip(2) => btw4x_5_29, input_wip(3)
4645 
                           => btw4x_5_28, input_wip(4) => btw4x_5_27,
4646 
                           input_wip(5) => btw4x_5_26, input_wip(6) =>
4647 
                           btw4x_5_25, input_wip(7) => btw4x_5_24, input_wip(8)
4648 
                           => btw4x_5_23, input_wip(9) => btw4x_5_22,
4649 
                           input_wip(10) => btw4x_5_21, input_wip(11) =>
4650 
                           btw4x_5_20, input_wip(12) => btw4x_5_19,
4651 
                           input_wip(13) => btw4x_5_18, input_wip(14) =>
4652 
                           btw4x_5_17, input_wip(15) => btw4x_5_16,
4653 
                           input_wip(16) => btw4x_5_15, input_wip(17) =>
4654 
                           btw4x_5_14, input_wip(18) => btw4x_5_13,
4655 
                           input_wip(19) => btw4x_5_12, input_wip(20) =>
4656 
                           btw4x_5_11, input_wip(21) => btw4x_5_10,
4657 
                           input_wip(22) => btw4x_5_9, input_wip(23) =>
4658 
                           btw4x_5_8, input_wip(24) => btw4x_5_7, input_wip(25)
4659 
                           => btw4x_5_6, input_wip(26) => btw4x_5_5,
4660 
                           input_wip(27) => btw4x_5_4, input_wip(28) =>
4661 
                           btw4x_5_3, input_wip(29) => btw4x_5_2, input_wip(30)
4662 
                           => btw4x_5_1, input_wip(31) => btw4x_5_0,
4663 
                           input_fcs(0) => btw4_5_31, input_fcs(1) => btw4_5_30
4664 
                           , input_fcs(2) => btw4_5_29, input_fcs(3) =>
4665 
                           btw4_5_28, input_fcs(4) => btw4_5_27, input_fcs(5)
4666 
                           => btw4_5_26, input_fcs(6) => btw4_5_25,
4667 
                           input_fcs(7) => btw4_5_24, input_fcs(8) => btw4_5_23
4668 
                           , input_fcs(9) => btw4_5_22, input_fcs(10) =>
4669 
                           btw4_5_21, input_fcs(11) => btw4_5_20, input_fcs(12)
4670 
                           => btw4_5_19, input_fcs(13) => btw4_5_18,
4671 
                           input_fcs(14) => btw4_5_17, input_fcs(15) =>
4672 
                           btw4_5_16, input_fcs(16) => btw4_5_15, input_fcs(17)
4673 
                           => btw4_5_14, input_fcs(18) => btw4_5_13,
4674 
                           input_fcs(19) => btw4_5_12, input_fcs(20) =>
4675 
                           btw4_5_11, input_fcs(21) => btw4_5_10, input_fcs(22)
4676 
                           => btw4_5_9, input_fcs(23) => btw4_5_8,
4677 
                           input_fcs(24) => btw4_5_7, input_fcs(25) => btw4_5_6
4678 
                           , input_fcs(26) => btw4_5_5, input_fcs(27) =>
4679 
                           btw4_5_4, input_fcs(28) => btw4_5_3, input_fcs(29)
4680 
                           => btw4_5_2, input_fcs(30) => btw4_5_1,
4681 
                           input_fcs(31) => btw4_5_0, output_wip(0) =>
4682 
                           btw5_5x_31, output_wip(1) => btw5_5x_30,
4683 
                           output_wip(2) => btw5_5x_29, output_wip(3) =>
4684 
                           btw5_5x_28, output_wip(4) => btw5_5x_27,
4685 
                           output_wip(5) => btw5_5x_26, output_wip(6) =>
4686 
                           btw5_5x_25, output_wip(7) => btw5_5x_24,
4687 
                           output_wip(8) => btw5_5x_23, output_wip(9) =>
4688 
                           btw5_5x_22, output_wip(10) => btw5_5x_21,
4689 
                           output_wip(11) => btw5_5x_20, output_wip(12) =>
4690 
                           btw5_5x_19, output_wip(13) => btw5_5x_18,
4691 
                           output_wip(14) => btw5_5x_17, output_wip(15) =>
4692 
                           btw5_5x_16, output_wip(16) => btw5_5x_15,
4693 
                           output_wip(17) => btw5_5x_14, output_wip(18) =>
4694 
                           btw5_5x_13, output_wip(19) => btw5_5x_12,
4695 
                           output_wip(20) => btw5_5x_11, output_wip(21) =>
4696 
                           btw5_5x_10, output_wip(22) => btw5_5x_9,
4697 
                           output_wip(23) => btw5_5x_8, output_wip(24) =>
4698 
                           btw5_5x_7, output_wip(25) => btw5_5x_6,
4699 
                           output_wip(26) => btw5_5x_5, output_wip(27) =>
4700 
                           btw5_5x_4, output_wip(28) => btw5_5x_3,
4701 
                           output_wip(29) => btw5_5x_2, output_wip(30) =>
4702 
                           btw5_5x_1, output_wip(31) => btw5_5x_0,
4703 
                           output_fcs(0) => btw5_6_31, output_fcs(1) =>
4704 
                           btw5_6_30, output_fcs(2) => btw5_6_29, output_fcs(3)
4705 
                           => btw5_6_28, output_fcs(4) => btw5_6_27,
4706 
                           output_fcs(5) => btw5_6_26, output_fcs(6) =>
4707 
                           btw5_6_25, output_fcs(7) => btw5_6_24, output_fcs(8)
4708 
                           => btw5_6_23, output_fcs(9) => btw5_6_22,
4709 
                           output_fcs(10) => btw5_6_21, output_fcs(11) =>
4710 
                           btw5_6_20, output_fcs(12) => btw5_6_19,
4711 
                           output_fcs(13) => btw5_6_18, output_fcs(14) =>
4712 
                           btw5_6_17, output_fcs(15) => btw5_6_16,
4713 
                           output_fcs(16) => btw5_6_15, output_fcs(17) =>
4714 
                           btw5_6_14, output_fcs(18) => btw5_6_13,
4715 
                           output_fcs(19) => btw5_6_12, output_fcs(20) =>
4716 
                           btw5_6_11, output_fcs(21) => btw5_6_10,
4717 
                           output_fcs(22) => btw5_6_9, output_fcs(23) =>
4718 
                           btw5_6_8, output_fcs(24) => btw5_6_7, output_fcs(25)
4719 
                           => btw5_6_6, output_fcs(26) => btw5_6_5,
4720 
                           output_fcs(27) => btw5_6_4, output_fcs(28) =>
4721 
                           btw5_6_3, output_fcs(29) => btw5_6_2, output_fcs(30)
4722 
                           => btw5_6_1, output_fcs(31) => btw5_6_0);
4723 
   GF8x : gf_xor_8x port map( input_wip(0) => btw8_8x_31, input_wip(1) =>
4724 
                           btw8_8x_30, input_wip(2) => btw8_8x_29, input_wip(3)
4725 
                           => btw8_8x_28, input_wip(4) => btw8_8x_27,
4726 
                           input_wip(5) => btw8_8x_26, input_wip(6) =>
4727 
                           btw8_8x_25, input_wip(7) => btw8_8x_24, input_wip(8)
4728 
                           => btw8_8x_23, input_wip(9) => btw8_8x_22,
4729 
                           input_wip(10) => btw8_8x_21, input_wip(11) =>
4730 
                           btw8_8x_20, input_wip(12) => btw8_8x_19,
4731 
                           input_wip(13) => btw8_8x_18, input_wip(14) =>
4732 
                           btw8_8x_17, input_wip(15) => btw8_8x_16,
4733 
                           input_wip(16) => btw8_8x_15, input_wip(17) =>
4734 
                           btw8_8x_14, input_wip(18) => btw8_8x_13,
4735 
                           input_wip(19) => btw8_8x_12, input_wip(20) =>
4736 
                           btw8_8x_11, input_wip(21) => btw8_8x_10,
4737 
                           input_wip(22) => btw8_8x_9, input_wip(23) =>
4738 
                           btw8_8x_8, input_wip(24) => btw8_8x_7, input_wip(25)
4739 
                           => btw8_8x_6, input_wip(26) => btw8_8x_5,
4740 
                           input_wip(27) => btw8_8x_4, input_wip(28) =>
4741 
                           btw8_8x_3, input_wip(29) => btw8_8x_2, input_wip(30)
4742 
                           => btw8_8x_1, input_wip(31) => btw8_8x_0,
4743 
                           input_fcs(0) => btw8_9_31, input_fcs(1) => btw8_9_30
4744 
                           , input_fcs(2) => btw8_9_29, input_fcs(3) =>
4745 
                           btw8_9_28, input_fcs(4) => btw8_9_27, input_fcs(5)
4746 
                           => btw8_9_26, input_fcs(6) => btw8_9_25,
4747 
                           input_fcs(7) => btw8_9_24, input_fcs(8) => btw8_9_23
4748 
                           , input_fcs(9) => btw8_9_22, input_fcs(10) =>
4749 
                           btw8_9_21, input_fcs(11) => btw8_9_20, input_fcs(12)
4750 
                           => btw8_9_19, input_fcs(13) => btw8_9_18,
4751 
                           input_fcs(14) => btw8_9_17, input_fcs(15) =>
4752 
                           btw8_9_16, input_fcs(16) => btw8_9_15, input_fcs(17)
4753 
                           => btw8_9_14, input_fcs(18) => btw8_9_13,
4754 
                           input_fcs(19) => btw8_9_12, input_fcs(20) =>
4755 
                           btw8_9_11, input_fcs(21) => btw8_9_10, input_fcs(22)
4756 
                           => btw8_9_9, input_fcs(23) => btw8_9_8,
4757 
                           input_fcs(24) => btw8_9_7, input_fcs(25) => btw8_9_6
4758 
                           , input_fcs(26) => btw8_9_5, input_fcs(27) =>
4759 
                           btw8_9_4, input_fcs(28) => btw8_9_3, input_fcs(29)
4760 
                           => btw8_9_2, input_fcs(30) => btw8_9_1,
4761 
                           input_fcs(31) => btw8_9_0, output_wip(0) =>
4762 
                           btw8x_9_31, output_wip(1) => btw8x_9_30,
4763 
                           output_wip(2) => btw8x_9_29, output_wip(3) =>
4764 
                           btw8x_9_28, output_wip(4) => btw8x_9_27,
4765 
                           output_wip(5) => btw8x_9_26, output_wip(6) =>
4766 
                           btw8x_9_25, output_wip(7) => btw8x_9_24,
4767 
                           output_wip(8) => btw8x_9_23, output_wip(9) =>
4768 
                           btw8x_9_22, output_wip(10) => btw8x_9_21,
4769 
                           output_wip(11) => btw8x_9_20, output_wip(12) =>
4770 
                           btw8x_9_19, output_wip(13) => btw8x_9_18,
4771 
                           output_wip(14) => btw8x_9_17, output_wip(15) =>
4772 
                           btw8x_9_16, output_wip(16) => btw8x_9_15,
4773 
                           output_wip(17) => btw8x_9_14, output_wip(18) =>
4774 
                           btw8x_9_13, output_wip(19) => btw8x_9_12,
4775 
                           output_wip(20) => btw8x_9_11, output_wip(21) =>
4776 
                           btw8x_9_10, output_wip(22) => btw8x_9_9,
4777 
                           output_wip(23) => btw8x_9_8, output_wip(24) =>
4778 
                           btw8x_9_7, output_wip(25) => btw8x_9_6,
4779 
                           output_wip(26) => btw8x_9_5, output_wip(27) =>
4780 
                           btw8x_9_4, output_wip(28) => btw8x_9_3,
4781 
                           output_wip(29) => btw8x_9_2, output_wip(30) =>
4782 
                           btw8x_9_1, output_wip(31) => btw8x_9_0);
4783 
   GF4 : gf_phi1_register_0 port map( reset => reset, phi1 => phi1,
4784 
                           input_wip(0) => btw3x_4_31, input_wip(1) =>
4785 
                           btw3x_4_30, input_wip(2) => btw3x_4_29, input_wip(3)
4786 
                           => btw3x_4_28, input_wip(4) => btw3x_4_27,
4787 
                           input_wip(5) => btw3x_4_26, input_wip(6) =>
4788 
                           btw3x_4_25, input_wip(7) => btw3x_4_24, input_wip(8)
4789 
                           => btw3x_4_23, input_wip(9) => btw3x_4_22,
4790 
                           input_wip(10) => btw3x_4_21, input_wip(11) =>
4791 
                           btw3x_4_20, input_wip(12) => btw3x_4_19,
4792 
                           input_wip(13) => btw3x_4_18, input_wip(14) =>
4793 
                           btw3x_4_17, input_wip(15) => btw3x_4_16,
4794 
                           input_wip(16) => btw3x_4_15, input_wip(17) =>
4795 
                           btw3x_4_14, input_wip(18) => btw3x_4_13,
4796 
                           input_wip(19) => btw3x_4_12, input_wip(20) =>
4797 
                           btw3x_4_11, input_wip(21) => btw3x_4_10,
4798 
                           input_wip(22) => btw3x_4_9, input_wip(23) =>
4799 
                           btw3x_4_8, input_wip(24) => btw3x_4_7, input_wip(25)
4800 
                           => btw3x_4_6, input_wip(26) => btw3x_4_5,
4801 
                           input_wip(27) => btw3x_4_4, input_wip(28) =>
4802 
                           btw3x_4_3, input_wip(29) => btw3x_4_2, input_wip(30)
4803 
                           => btw3x_4_1, input_wip(31) => btw3x_4_0,
4804 
                           input_fcs(0) => btw3_4_31, input_fcs(1) => btw3_4_30
4805 
                           , input_fcs(2) => btw3_4_29, input_fcs(3) =>
4806 
                           btw3_4_28, input_fcs(4) => btw3_4_27, input_fcs(5)
4807 
                           => btw3_4_26, input_fcs(6) => btw3_4_25,
4808 
                           input_fcs(7) => btw3_4_24, input_fcs(8) => btw3_4_23
4809 
                           , input_fcs(9) => btw3_4_22, input_fcs(10) =>
4810 
                           btw3_4_21, input_fcs(11) => btw3_4_20, input_fcs(12)
4811 
                           => btw3_4_19, input_fcs(13) => btw3_4_18,
4812 
                           input_fcs(14) => btw3_4_17, input_fcs(15) =>
4813 
                           btw3_4_16, input_fcs(16) => btw3_4_15, input_fcs(17)
4814 
                           => btw3_4_14, input_fcs(18) => btw3_4_13,
4815 
                           input_fcs(19) => btw3_4_12, input_fcs(20) =>
4816 
                           btw3_4_11, input_fcs(21) => btw3_4_10, input_fcs(22)
4817 
                           => btw3_4_9, input_fcs(23) => btw3_4_8,
4818 
                           input_fcs(24) => btw3_4_7, input_fcs(25) => btw3_4_6
4819 
                           , input_fcs(26) => btw3_4_5, input_fcs(27) =>
4820 
                           btw3_4_4, input_fcs(28) => btw3_4_3, input_fcs(29)
4821 
                           => btw3_4_2, input_fcs(30) => btw3_4_1,
4822 
                           input_fcs(31) => btw3_4_0, output_wip(0) =>
4823 
                           btw4_4x_31, output_wip(1) => btw4_4x_30,
4824 
                           output_wip(2) => btw4_4x_29, output_wip(3) =>
4825 
                           btw4_4x_28, output_wip(4) => btw4_4x_27,
4826 
                           output_wip(5) => btw4_4x_26, output_wip(6) =>
4827 
                           btw4_4x_25, output_wip(7) => btw4_4x_24,
4828 
                           output_wip(8) => btw4_4x_23, output_wip(9) =>
4829 
                           btw4_4x_22, output_wip(10) => btw4_4x_21,
4830 
                           output_wip(11) => btw4_4x_20, output_wip(12) =>
4831 
                           btw4_4x_19, output_wip(13) => btw4_4x_18,
4832 
                           output_wip(14) => btw4_4x_17, output_wip(15) =>
4833 
                           btw4_4x_16, output_wip(16) => btw4_4x_15,
4834 
                           output_wip(17) => btw4_4x_14, output_wip(18) =>
4835 
                           btw4_4x_13, output_wip(19) => btw4_4x_12,
4836 
                           output_wip(20) => btw4_4x_11, output_wip(21) =>
4837 
                           btw4_4x_10, output_wip(22) => btw4_4x_9,
4838 
                           output_wip(23) => btw4_4x_8, output_wip(24) =>
4839 
                           btw4_4x_7, output_wip(25) => btw4_4x_6,
4840 
                           output_wip(26) => btw4_4x_5, output_wip(27) =>
4841 
                           btw4_4x_4, output_wip(28) => btw4_4x_3,
4842 
                           output_wip(29) => btw4_4x_2, output_wip(30) =>
4843 
                           btw4_4x_1, output_wip(31) => btw4_4x_0,
4844 
                           output_fcs(0) => btw4_5_31, output_fcs(1) =>
4845 
                           btw4_5_30, output_fcs(2) => btw4_5_29, output_fcs(3)
4846 
                           => btw4_5_28, output_fcs(4) => btw4_5_27,
4847 
                           output_fcs(5) => btw4_5_26, output_fcs(6) =>
4848 
                           btw4_5_25, output_fcs(7) => btw4_5_24, output_fcs(8)
4849 
                           => btw4_5_23, output_fcs(9) => btw4_5_22,
4850 
                           output_fcs(10) => btw4_5_21, output_fcs(11) =>
4851 
                           btw4_5_20, output_fcs(12) => btw4_5_19,
4852 
                           output_fcs(13) => btw4_5_18, output_fcs(14) =>
4853 
                           btw4_5_17, output_fcs(15) => btw4_5_16,
4854 
                           output_fcs(16) => btw4_5_15, output_fcs(17) =>
4855 
                           btw4_5_14, output_fcs(18) => btw4_5_13,
4856 
                           output_fcs(19) => btw4_5_12, output_fcs(20) =>
4857 
                           btw4_5_11, output_fcs(21) => btw4_5_10,
4858 
                           output_fcs(22) => btw4_5_9, output_fcs(23) =>
4859 
                           btw4_5_8, output_fcs(24) => btw4_5_7, output_fcs(25)
4860 
                           => btw4_5_6, output_fcs(26) => btw4_5_5,
4861 
                           output_fcs(27) => btw4_5_4, output_fcs(28) =>
4862 
                           btw4_5_3, output_fcs(29) => btw4_5_2, output_fcs(30)
4863 
                           => btw4_5_1, output_fcs(31) => btw4_5_0);
4864 
   GF7x : gf_xor_7x port map( input_wip(0) => btw7_7x_31, input_wip(1) =>
4865 
                           btw7_7x_30, input_wip(2) => btw7_7x_29, input_wip(3)
4866 
                           => btw7_7x_28, input_wip(4) => btw7_7x_27,
4867 
                           input_wip(5) => btw7_7x_26, input_wip(6) =>
4868 
                           btw7_7x_25, input_wip(7) => btw7_7x_24, input_wip(8)
4869 
                           => btw7_7x_23, input_wip(9) => btw7_7x_22,
4870 
                           input_wip(10) => btw7_7x_21, input_wip(11) =>
4871 
                           btw7_7x_20, input_wip(12) => btw7_7x_19,
4872 
                           input_wip(13) => btw7_7x_18, input_wip(14) =>
4873 
                           btw7_7x_17, input_wip(15) => btw7_7x_16,
4874 
                           input_wip(16) => btw7_7x_15, input_wip(17) =>
4875 
                           btw7_7x_14, input_wip(18) => btw7_7x_13,
4876 
                           input_wip(19) => btw7_7x_12, input_wip(20) =>
4877 
                           btw7_7x_11, input_wip(21) => btw7_7x_10,
4878 
                           input_wip(22) => btw7_7x_9, input_wip(23) =>
4879 
                           btw7_7x_8, input_wip(24) => btw7_7x_7, input_wip(25)
4880 
                           => btw7_7x_6, input_wip(26) => btw7_7x_5,
4881 
                           input_wip(27) => btw7_7x_4, input_wip(28) =>
4882 
                           btw7_7x_3, input_wip(29) => btw7_7x_2, input_wip(30)
4883 
                           => btw7_7x_1, input_wip(31) => btw7_7x_0,
4884 
                           input_fcs(0) => btw7_8_31, input_fcs(1) => btw7_8_30
4885 
                           , input_fcs(2) => btw7_8_29, input_fcs(3) =>
4886 
                           btw7_8_28, input_fcs(4) => btw7_8_27, input_fcs(5)
4887 
                           => btw7_8_26, input_fcs(6) => btw7_8_25,
4888 
                           input_fcs(7) => btw7_8_24, input_fcs(8) => btw7_8_23
4889 
                           , input_fcs(9) => btw7_8_22, input_fcs(10) =>
4890 
                           btw7_8_21, input_fcs(11) => btw7_8_20, input_fcs(12)
4891 
                           => btw7_8_19, input_fcs(13) => btw7_8_18,
4892 
                           input_fcs(14) => btw7_8_17, input_fcs(15) =>
4893 
                           btw7_8_16, input_fcs(16) => btw7_8_15, input_fcs(17)
4894 
                           => btw7_8_14, input_fcs(18) => btw7_8_13,
4895 
                           input_fcs(19) => btw7_8_12, input_fcs(20) =>
4896 
                           btw7_8_11, input_fcs(21) => btw7_8_10, input_fcs(22)
4897 
                           => btw7_8_9, input_fcs(23) => btw7_8_8,
4898 
                           input_fcs(24) => btw7_8_7, input_fcs(25) => btw7_8_6
4899 
                           , input_fcs(26) => btw7_8_5, input_fcs(27) =>
4900 
                           btw7_8_4, input_fcs(28) => btw7_8_3, input_fcs(29)
4901 
                           => btw7_8_2, input_fcs(30) => btw7_8_1,
4902 
                           input_fcs(31) => btw7_8_0, output_wip(0) =>
4903 
                           btw7x_8_31, output_wip(1) => btw7x_8_30,
4904 
                           output_wip(2) => btw7x_8_29, output_wip(3) =>
4905 
                           btw7x_8_28, output_wip(4) => btw7x_8_27,
4906 
                           output_wip(5) => btw7x_8_26, output_wip(6) =>
4907 
                           btw7x_8_25, output_wip(7) => btw7x_8_24,
4908 
                           output_wip(8) => btw7x_8_23, output_wip(9) =>
4909 
                           btw7x_8_22, output_wip(10) => btw7x_8_21,
4910 
                           output_wip(11) => btw7x_8_20, output_wip(12) =>
4911 
                           btw7x_8_19, output_wip(13) => btw7x_8_18,
4912 
                           output_wip(14) => btw7x_8_17, output_wip(15) =>
4913 
                           btw7x_8_16, output_wip(16) => btw7x_8_15,
4914 
                           output_wip(17) => btw7x_8_14, output_wip(18) =>
4915 
                           btw7x_8_13, output_wip(19) => btw7x_8_12,
4916 
                           output_wip(20) => btw7x_8_11, output_wip(21) =>
4917 
                           btw7x_8_10, output_wip(22) => btw7x_8_9,
4918 
                           output_wip(23) => btw7x_8_8, output_wip(24) =>
4919 
                           btw7x_8_7, output_wip(25) => btw7x_8_6,
4920 
                           output_wip(26) => btw7x_8_5, output_wip(27) =>
4921 
                           btw7x_8_4, output_wip(28) => btw7x_8_3,
4922 
                           output_wip(29) => btw7x_8_2, output_wip(30) =>
4923 
                           btw7x_8_1, output_wip(31) => btw7x_8_0);
4924 
   GF10 : gf_phi1_register_out port map( reset => reset, phi1 => phi1,
4925 
                           input_wip(0) => btw9x_10_31, input_wip(1) =>
4926 
                           btw9x_10_30, input_wip(2) => btw9x_10_29,
4927 
                           input_wip(3) => btw9x_10_28, input_wip(4) =>
4928 
                           btw9x_10_27, input_wip(5) => btw9x_10_26,
4929 
                           input_wip(6) => btw9x_10_25, input_wip(7) =>
4930 
                           btw9x_10_24, input_wip(8) => btw9x_10_23,
4931 
                           input_wip(9) => btw9x_10_22, input_wip(10) =>
4932 
                           btw9x_10_21, input_wip(11) => btw9x_10_20,
4933 
                           input_wip(12) => btw9x_10_19, input_wip(13) =>
4934 
                           btw9x_10_18, input_wip(14) => btw9x_10_17,
4935 
                           input_wip(15) => btw9x_10_16, input_wip(16) =>
4936 
                           btw9x_10_15, input_wip(17) => btw9x_10_14,
4937 
                           input_wip(18) => btw9x_10_13, input_wip(19) =>
4938 
                           btw9x_10_12, input_wip(20) => btw9x_10_11,
4939 
                           input_wip(21) => btw9x_10_10, input_wip(22) =>
4940 
                           btw9x_10_9, input_wip(23) => btw9x_10_8,
4941 
                           input_wip(24) => btw9x_10_7, input_wip(25) =>
4942 
                           btw9x_10_6, input_wip(26) => btw9x_10_5,
4943 
                           input_wip(27) => btw9x_10_4, input_wip(28) =>
4944 
                           btw9x_10_3, input_wip(29) => btw9x_10_2,
4945 
                           input_wip(30) => btw9x_10_1, input_wip(31) =>
4946 
                           btw9x_10_0, output_final(0) => output_fcs(0),
4947 
                           output_final(1) => output_fcs(1), output_final(2) =>
4948 
                           output_fcs(2), output_final(3) => output_fcs(3),
4949 
                           output_final(4) => output_fcs(4), output_final(5) =>
4950 
                           output_fcs(5), output_final(6) => output_fcs(6),
4951 
                           output_final(7) => output_fcs(7), output_final(8) =>
4952 
                           output_fcs(8), output_final(9) => output_fcs(9),
4953 
                           output_final(10) => output_fcs(10), output_final(11)
4954 
                           => output_fcs(11), output_final(12) =>
4955 
                           output_fcs(12), output_final(13) => output_fcs(13),
4956 
                           output_final(14) => output_fcs(14), output_final(15)
4957 
                           => output_fcs(15), output_final(16) => output_xor(0)
4958 
                           , output_final(17) => output_xor(1),
4959 
                           output_final(18) => output_xor(2), output_final(19)
4960 
                           => output_xor(3), output_final(20) => output_xor(4),
4961 
                           output_final(21) => output_xor(5), output_final(22)
4962 
                           => output_xor(6), output_final(23) => output_xor(7),
4963 
                           output_final(24) => output_xor(8), output_final(25)
4964 
                           => output_xor(9), output_final(26) => output_xor(10)
4965 
                           , output_final(27) => output_xor(11),
4966 
                           output_final(28) => output_xor(12), output_final(29)
4967 
                           => output_xor(13), output_final(30) =>
4968 
                           output_xor(14), output_final(31) => output_xor(15));
4969 
 
4970 
end SYN_structural_architecture2;
4971 
 
4972 
library IEEE;
4973 
library csx_HRDLIB;
4974 
library csx_IOLIB_3M;
4975 
 
4976 
use IEEE.std_logic_1164.all;
4977 
use IEEE.std_logic_arith.all;
4978 
use csx_HRDLIB.Vcomponents.all;
4979 
use csx_IOLIB_3M.Vcomponents.all;
4980 
 
4981 
entity big_xor is
4982 
 
4983 
   port( reset, phi2 : in std_logic;  input_input, fcs_input, gf_input : in
4984 
         std_logic_vector (0 to 15);  output : out std_logic_vector (0 to 31));
4985 
 
4986 
end big_xor;
4987 
 
4988 
architecture SYN_behavior_architecture of big_xor is
4989 
 
4990 
   component DFA2
4991 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
4992 
   end component;
4993 
 
4994 
   component DFA
4995 
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
4996 
   end component;
4997 
 
4998 
   component DF9
4999 
      port( C, D : in std_logic;  Q, QN : out std_logic;  SN : in std_logic);
5000 
   end component;
5001 
 
5002 
   component DF92
5003 
      port( C, D : in std_logic;  Q, QN : out std_logic;  SN : in std_logic);
5004 
   end component;
5005 
 
5006 
   component BU4
5007 
      port( A : in std_logic;  Q : out std_logic);
5008 
   end component;
5009 
 
5010 
   component BU2
5011 
      port( A : in std_logic;  Q : out std_logic);
5012 
   end component;
5013 
 
5014 
   component IN4
5015 
      port( A : in std_logic;  Q : out std_logic);
5016 
   end component;
5017 
 
5018 
   component IN8
5019 
      port( A : in std_logic;  Q : out std_logic);
5020 
   end component;
5021 
 
5022 
   component EO1
5023 
      port( A, B : in std_logic;  Q : out std_logic);
5024 
   end component;
5025 
 
5026 
   signal output_xor_15, output_xor_12, output_xor_9, output_xor_7,
5027 
      output_xor_0, output_xor_14, output_xor_13, output_xor_8, output_xor_6,
5028 
      output_xor_1, output_xor_11, output_xor_10, output_xor_5, output_xor_4,
5029 
      output_xor_3, output_xor_2, n77, n78, n79, n81, n83, n85, n87, n89, n91,
5030 
      n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172,
5031 
      n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
5032 
      n185, n186, n187, n188, n189, n190, n191, n192 : std_logic;
5033 
 
5034 
begin
5035 
 
5036 
   output_reg_31 : DFA2 port map( C => phi2, D => fcs_input(0), Q => n161, QN
5037 
                           => n91, RN => n78);
5038 
   output_reg_20 : DFA port map( C => phi2, D => fcs_input(11), Q => output(11)
5039 
                           , QN => n162, RN => n78);
5040 
   output_reg_21 : DF9 port map( C => phi2, D => fcs_input(10), Q => output(10)
5041 
                           , QN => n163, SN => n78);
5042 
   output_reg_16 : DF92 port map( C => phi2, D => fcs_input(15), Q =>
5043 
                           output(15), QN => n164, SN => n78);
5044 
   output_reg_18 : DF92 port map( C => phi2, D => fcs_input(13), Q =>
5045 
                           output(13), QN => n165, SN => n78);
5046 
   output_reg_19 : DF92 port map( C => phi2, D => fcs_input(12), Q =>
5047 
                           output(12), QN => n166, SN => n78);
5048 
   output_reg_17 : DF92 port map( C => phi2, D => fcs_input(14), Q =>
5049 
                           output(14), QN => n167, SN => n78);
5050 
   U49 : BU4 port map( A => n77, Q => n78);
5051 
   U50 : BU2 port map( A => reset, Q => n77);
5052 
   U51 : IN4 port map( A => n79, Q => output(9));
5053 
   U52 : IN8 port map( A => n89, Q => output(3));
5054 
   U53 : IN8 port map( A => n83, Q => output(5));
5055 
   U54 : IN8 port map( A => n87, Q => output(2));
5056 
   U55 : IN8 port map( A => n81, Q => output(1));
5057 
   output_reg_3 : DF9 port map( C => phi2, D => output_xor_3, Q => output(28),
5058 
                           QN => n168, SN => n78);
5059 
   output_reg_13 : DF9 port map( C => phi2, D => output_xor_13, Q => output(18)
5060 
                           , QN => n169, SN => n78);
5061 
   output_reg_14 : DF9 port map( C => phi2, D => output_xor_14, Q => output(17)
5062 
                           , QN => n170, SN => n78);
5063 
   output_reg_0 : DF9 port map( C => phi2, D => output_xor_0, Q => output(31),
5064 
                           QN => n171, SN => n78);
5065 
   output_reg_10 : DF9 port map( C => phi2, D => output_xor_10, Q => output(21)
5066 
                           , QN => n172, SN => n78);
5067 
   output_reg_6 : DF9 port map( C => phi2, D => output_xor_6, Q => output(25),
5068 
                           QN => n173, SN => n78);
5069 
   output_reg_15 : DFA port map( C => phi2, D => output_xor_15, Q => output(16)
5070 
                           , QN => n174, RN => n78);
5071 
   output_reg_12 : DFA port map( C => phi2, D => output_xor_12, Q => output(19)
5072 
                           , QN => n175, RN => n78);
5073 
   output_reg_4 : DFA port map( C => phi2, D => output_xor_4, Q => output(27),
5074 
                           QN => n176, RN => n78);
5075 
   output_reg_5 : DFA port map( C => phi2, D => output_xor_5, Q => output(26),
5076 
                           QN => n177, RN => n78);
5077 
   output_reg_2 : DFA port map( C => phi2, D => output_xor_2, Q => output(29),
5078 
                           QN => n178, RN => n78);
5079 
   output_reg_9 : DFA port map( C => phi2, D => output_xor_9, Q => output(22),
5080 
                           QN => n179, RN => n78);
5081 
   output_reg_11 : DFA port map( C => phi2, D => output_xor_11, Q => output(20)
5082 
                           , QN => n180, RN => n78);
5083 
   output_reg_7 : DFA port map( C => phi2, D => output_xor_7, Q => output(24),
5084 
                           QN => n181, RN => n78);
5085 
   output_reg_1 : DFA port map( C => phi2, D => output_xor_1, Q => output(30),
5086 
                           QN => n182, RN => n78);
5087 
   output_reg_8 : DFA port map( C => phi2, D => output_xor_8, Q => output(23),
5088 
                           QN => n183, RN => n78);
5089 
   U56 : EO1 port map( A => gf_input(3), B => input_input(3), Q =>
5090 
                           output_xor_12);
5091 
   U57 : EO1 port map( A => gf_input(0), B => input_input(0), Q =>
5092 
                           output_xor_15);
5093 
   U58 : EO1 port map( A => gf_input(11), B => input_input(11), Q =>
5094 
                           output_xor_4);
5095 
   U59 : EO1 port map( A => gf_input(10), B => input_input(10), Q =>
5096 
                           output_xor_5);
5097 
   U60 : EO1 port map( A => gf_input(13), B => input_input(13), Q =>
5098 
                           output_xor_2);
5099 
   U61 : EO1 port map( A => gf_input(6), B => input_input(6), Q => output_xor_9
5100 
                           );
5101 
   U62 : EO1 port map( A => gf_input(4), B => input_input(4), Q =>
5102 
                           output_xor_11);
5103 
   U63 : EO1 port map( A => gf_input(8), B => input_input(8), Q => output_xor_7
5104 
                           );
5105 
   U64 : EO1 port map( A => gf_input(14), B => input_input(14), Q =>
5106 
                           output_xor_1);
5107 
   U65 : EO1 port map( A => gf_input(7), B => input_input(7), Q => output_xor_8
5108 
                           );
5109 
   U66 : EO1 port map( A => gf_input(12), B => input_input(12), Q =>
5110 
                           output_xor_3);
5111 
   U67 : EO1 port map( A => gf_input(2), B => input_input(2), Q =>
5112 
                           output_xor_13);
5113 
   U68 : EO1 port map( A => gf_input(1), B => input_input(1), Q =>
5114 
                           output_xor_14);
5115 
   U69 : EO1 port map( A => gf_input(15), B => input_input(15), Q =>
5116 
                           output_xor_0);
5117 
   U70 : EO1 port map( A => gf_input(5), B => input_input(5), Q =>
5118 
                           output_xor_10);
5119 
   U71 : EO1 port map( A => gf_input(9), B => input_input(9), Q => output_xor_6
5120 
                           );
5121 
   output_reg_30 : DF92 port map( C => phi2, D => fcs_input(1), Q => n184, QN
5122 
                           => n81, SN => n78);
5123 
   output_reg_26 : DF92 port map( C => phi2, D => fcs_input(5), Q => n185, QN
5124 
                           => n83, SN => n78);
5125 
   U72 : IN4 port map( A => n85, Q => output(4));
5126 
   output_reg_28 : DFA2 port map( C => phi2, D => fcs_input(3), Q => n186, QN
5127 
                           => n89, RN => n78);
5128 
   output_reg_29 : DFA2 port map( C => phi2, D => fcs_input(2), Q => n187, QN
5129 
                           => n87, RN => n78);
5130 
   U73 : IN8 port map( A => n91, Q => output(0));
5131 
   output_reg_23 : DF92 port map( C => phi2, D => fcs_input(8), Q => output(8),
5132 
                           QN => n188, SN => n78);
5133 
   output_reg_25 : DF92 port map( C => phi2, D => fcs_input(6), Q => output(6),
5134 
                           QN => n189, SN => n78);
5135 
   output_reg_22 : DFA2 port map( C => phi2, D => fcs_input(9), Q => n190, QN
5136 
                           => n79, RN => n78);
5137 
   output_reg_24 : DFA2 port map( C => phi2, D => fcs_input(7), Q => output(7),
5138 
                           QN => n191, RN => n78);
5139 
   output_reg_27 : DFA2 port map( C => phi2, D => fcs_input(4), Q => n192, QN
5140 
                           => n85, RN => n78);
5141 
 
5142 
end SYN_behavior_architecture;

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