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[/] [fast-crc/] [trunk/] [vhdl/] [crc_modif.vhd] - Blame information for rev 5

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1 2 trueno 
library IEEE;
2 
use IEEE.std_logic_1164.all;
3 
 
4 
entity CRC_top is
5 
 
6 
  port (
7 
    phi1    : in  std_logic;
8 
                                        -- We will use the two phase discipline
9 
                                        -- which we don't generate.
10 
    phi2    : in  std_logic;
11 
    reset   : in  std_logic;            -- #RESET
12 
    input   : in  std_logic_vector(15 downto 0);
13 
                                        -- The serial/parallel conversion has been made somewhere else
14 
    FCS_out : out std_logic_vector(31 downto 0));
15 
 
16 
end CRC_top;
17 
 
18 
architecture structural of CRC_top is
19 
 
20 
  -- Structural description of the CRC
21 
  -- We will describe all the pipelining steps as different components in
22 
  -- order to force a certain implementation in the synthesised circuit
23 
 
24 
  -- These first pipelining steps are the "waiting" steps. The data will flow
25 
  -- through the registers.
26 
 
27 
  -- The nomenclature can be explained in the following way:
28 
  -- Input<stage no.>_<clock phase>  => Registers in the "wait" region
29 
 
30 
  -- For the Galois Field multiplier:
31 
  -- GF<stage no.>_<clock phase>     => Registers of the GF multiplier
32 
  -- GF<stage no.>_xor_<clock phase> => Combinational logic of the GF mult.
33 
 
34 
  component Input1_2
35 
    port (
36 
      reset     : in  std_logic;
37 
      phi2      : in  std_logic;
38 
      input1_2  : in  std_logic_vector (15 downto 0);   -- Directly from the serial/parallel register
39 
      output1_2 : out std_logic_vector (15 downto 0));  -- To the next step
40 
  end component;
41 
 
42 
  component Input2_1
43 
    port (
44 
      reset     : in  std_logic;
45 
      phi1      : in  std_logic;
46 
      input2_1  : in  std_logic_vector (15 downto 0);
47 
      output2_1 : out std_logic_vector (15 downto 0));
48 
  end component;
49 
 
50 
  component Input3_2
51 
    port (
52 
      reset     : in  std_logic;
53 
      phi2      : in  std_logic;
54 
      input3_2  : in  std_logic_vector (15 downto 0);
55 
      output3_2 : out std_logic_vector (15 downto 0));
56 
  end component;
57 
 
58 
  component Input4_1
59 
    port (
60 
      reset     : in  std_logic;
61 
      phi1      : in  std_logic;
62 
      input4_1  : in  std_logic_vector (15 downto 0);
63 
      output4_1 : out std_logic_vector (15 downto 0));
64 
  end component;
65 
 
66 
  component Input5_2
67 
    port (
68 
      reset     : in  std_logic;
69 
      phi2      : in  std_logic;
70 
      input5_2  : in  std_logic_vector (15 downto 0);
71 
      output5_2 : out std_logic_vector (15 downto 0));
72 
  end component;
73 
 
74 
  component Input6_1
75 
    port (
76 
      reset     : in  std_logic;
77 
      phi1      : in  std_logic;
78 
      input6_1  : in  std_logic_vector (15 downto 0);
79 
      output6_1 : out std_logic_vector (15 downto 0));
80 
  end component;
81 
 
82 
  component Input7_2
83 
    port (
84 
      reset     : in  std_logic;
85 
      phi2      : in  std_logic;
86 
      input7_2  : in  std_logic_vector (15 downto 0);
87 
      output7_2 : out std_logic_vector (15 downto 0));
88 
  end component;
89 
 
90 
  component Input8_1
91 
    port (
92 
      reset     : in  std_logic;
93 
      phi1      : in  std_logic;
94 
      input8_1  : in  std_logic_vector (15 downto 0);
95 
      output8_1 : out std_logic_vector (15 downto 0));
96 
  end component;
97 
 
98 
  component Input9_2
99 
    port (
100 
      reset     : in  std_logic;
101 
      phi2      : in  std_logic;
102 
      input9_2  : in  std_logic_vector (15 downto 0);
103 
      output9_2 : out std_logic_vector (15 downto 0));
104 
  end component;
105 
 
106 
  component Input10_1
107 
    port (
108 
      reset      : in  std_logic;
109 
      phi1       : in  std_logic;
110 
      input10_1  : in  std_logic_vector (15 downto 0);
111 
      output10_1 : out std_logic_vector (15 downto 0));
112 
  end component;
113 
 
114 
  component Input11_2
115 
    port (
116 
      reset      : in  std_logic;
117 
      phi2       : in  std_logic;
118 
      input11_2  : in  std_logic_vector (15 downto 0);
119 
      output11_2 : out std_logic_vector (15 downto 0));
120 
  end component;
121 
 
122 
  component Input12_1
123 
    port (
124 
      reset      : in  std_logic;
125 
      phi1       : in  std_logic;
126 
      input12_1  : in  std_logic_vector (15 downto 0);
127 
      output12_1 : out std_logic_vector (15 downto 0));
128 
  end component;
129 
 
130 
  -- Galois Field pipelining registers and combinational stuff
131 
 
132 
  component GF1_xor_2
133 
    port (
134 
      input_gf1x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
135 
      output_gf1x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
136 
  end component;
137 
 
138 
  component GF2_1
139 
    port (
140 
      reset       : in  std_logic;
141 
      phi1        : in  std_logic;
142 
      input_gf2_1  : in  std_logic_vector (63 downto 0);
143 
      output_gf2_1 : out std_logic_vector (63 downto 0));
144 
  end component;
145 
 
146 
  component GF2_xor_1
147 
    port (
148 
      input_gf2x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
149 
      output_gf2x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
150 
  end component;
151 
 
152 
  component GF3_2
153 
    port (
154 
      reset       : in  std_logic;
155 
      phi2        : in  std_logic;
156 
      input_gf3_2  : in  std_logic_vector (63 downto 0);
157 
      output_gf3_2 : out std_logic_vector (63 downto 0));
158 
  end component;
159 
 
160 
  component GF3_xor_2
161 
    port (
162 
      input_gf3x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
163 
      output_gf3x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
164 
  end component;
165 
 
166 
  component GF4_1
167 
    port (
168 
      reset  : in  std_logic;
169 
      phi1   : in  std_logic;
170 
      input_gf4_1  : in  std_logic_vector (63 downto 0);
171 
      output_gf4_1 : out std_logic_vector (63 downto 0));
172 
  end component;
173 
 
174 
  component GF4_xor_1
175 
    port (
176 
      input_gf4x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
177 
      output_gf4x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
178 
  end component;
179 
 
180 
  component GF5_2
181 
    port (
182 
      reset       : in  std_logic;
183 
      phi2        : in  std_logic;
184 
      input_gf5_2  : in  std_logic_vector (63 downto 0);
185 
      output_gf5_2 : out std_logic_vector (63 downto 0));
186 
  end component;
187 
 
188 
  component GF5_xor_2
189 
    port (
190 
      input_gf5x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
191 
      output_gf5x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
192 
  end component;
193 
 
194 
  component GF6_1
195 
    port (
196 
      reset       : in  std_logic;
197 
      phi1        : in  std_logic;
198 
      input_gf6_1  : in  std_logic_vector (63 downto 0);
199 
      output_gf6_1 : out std_logic_vector (63 downto 0));
200 
  end component;
201 
 
202 
  component GF6_xor_1
203 
    port (
204 
      input_gf6x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
205 
      output_gf6x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
206 
  end component;
207 
 
208 
  component GF7_2
209 
    port (
210 
      reset       : in  std_logic;
211 
      phi2        : in  std_logic;
212 
      input_gf7_2  : in  std_logic_vector (63 downto 0);
213 
      output_gf7_2 : out std_logic_vector (63 downto 0));
214 
  end component;
215 
 
216 
  component GF7_xor_2
217 
    port (
218 
      input_gf7x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
219 
      output_gf7x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
220 
  end component;
221 
 
222 
  component GF8_1
223 
    port (
224 
      reset       : in  std_logic;
225 
      phi1        : in  std_logic;
226 
      input_gf8_1  : in  std_logic_vector (63 downto 0);
227 
      output_gf8_1 : out std_logic_vector (63 downto 0));
228 
  end component;
229 
 
230 
  component GF8_xor_1
231 
    port (
232 
      input_gf8x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
233 
      output_gf8x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
234 
  end component;
235 
 
236 
  component GF9_2
237 
    port (
238 
      reset       : in  std_logic;
239 
      phi2        : in  std_logic;
240 
      input_gf9_2  : in  std_logic_vector (63 downto 0);
241 
      output_gf9_2 : out std_logic_vector (63 downto 0));
242 
  end component;
243 
 
244 
  component GF9_xor_2
245 
    port (
246 
      input_gf9x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
247 
      output_gf9x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
248 
  end component;
249 
 
250 
  component GF10_1
251 
    port (
252 
      reset        : in  std_logic;
253 
      phi1         : in  std_logic;
254 
      input_gf10_1  : in  std_logic_vector (63 downto 0);
255 
      output_gf10_1 : out std_logic_vector (63 downto 0));
256 
  end component;
257 
 
258 
  component GF10_xor_1
259 
    port (
260 
      input_gf10x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
261 
      output_gf10x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
262 
  end component;
263 
 
264 
  component GF11_2
265 
    port (
266 
      reset        : in  std_logic;
267 
      phi2         : in  std_logic;
268 
      input_gf11_2  : in  std_logic_vector (63 downto 0);
269 
      output_gf11_2 : out std_logic_vector (63 downto 0));
270 
  end component;
271 
 
272 
--  component GF11_xor_2
273 
--    port (
274 
--      input_gf11x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
275 
--      output_gf11x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
276 
--  end component;
277 
 
278 
  component GF12_1
279 
    port (
280 
      reset         : in  std_logic;
281 
      phi1          : in  std_logic;
282 
      input_gf12_1  : in  std_logic_vector (31 downto 0);
283 
      output_gf12_1 : out std_logic_vector (31 downto 0));
284 
  end component;
285 
 
286 
  -- Big XOR and output register (FCS)
287 
 
288 
  component Big_XOR12_1
289 
    port (
290 
      input_bigx12_1  : in  std_logic_vector (15 downto 0);
291 
      output_bigx12_1 : out std_logic_vector (15 downto 0));
292 
  end component;
293 
 
294 
  component FCS_out13_2
295 
    port (
296 
      reset          : in std_logic;
297 
      phi2           : in std_logic;
298 
      input_fcs13_2  : in  std_logic_vector (31 downto 0);
299 
      output_fcs13_2 : out std_logic_vector (31 downto 0));  -- FCS_out and feedback to the GF multiplier
300 
 
301 
  end component;
302 
 
303 
begin
304 
 
305 
Input1 : Input1_2 port map (
306 
    reset     => reset,
307 
    phi2      => phi2,
308 
    input1_2  => input,
309 
    output1_2 => input2_1);
310 
 
311 
Input2 : Input2_1 port map (
312 
    reset     => reset,
313 
    phi1      => phi1,
314 
    input2_1  => output1_2,
315 
    output2_1 => input3_1);
316 
 
317 
Input3 : Input3_2 port map (
318 
    reset     => reset,
319 
    phi2      => phi2,
320 
    input3_2  => output2_1,
321 
    output3_2 => input4_1);
322 
 
323 
Input4 : Input4_1 port map (
324 
    reset     => reset,
325 
    phi1      => phi1,
326 
    input4_1  => output3_2,
327 
    output4_1 => input5_2);
328 
 
329 
Input5 : Input5_2 port map (
330 
    reset     => reset,
331 
    phi2      => phi2,
332 
    input5_2  => output4_1,
333 
    output5_2 => input6_1);
334 
 
335 
Input6 : Input6_1 port map (
336 
    reset     => reset,
337 
    phi1      => phi1,
338 
    input6_1  => output5_2,
339 
    output6_1 => input7_2);
340 
 
341 
Input7 : Input7_2 port map (
342 
    reset     => reset,
343 
    phi2      => phi2,
344 
    input7_2  => output6_1,
345 
    output7_2 => input8_1);
346 
 
347 
Input8 : Input8_1 port map (
348 
    reset     => reset,
349 
    phi1      => phi1,
350 
    input8_1  => output7_2,
351 
    output8_1 => input9_2);
352 
 
353 
Input9 : Input9_2 port map (
354 
    reset     => reset,
355 
    phi2      => phi2,
356 
    input9_2  => output8_1,
357 
    output9_2 => input10_1);
358 
 
359 
Input10 : Input10_2 port map (
360 
    reset     => reset,
361 
    phi1      => phi1,
362 
    input10_1  => output9_2,
363 
    output10_1 => input11_2);
364 
 
365 
Input11 : Input11_2 port map (
366 
    reset     => reset,
367 
    phi2      => phi2,
368 
    input11_2  => output10_1,
369 
    output11_2 => input12_1);
370 
 
371 
Input12 : Input12_1 port map (
372 
    reset     => reset,
373 
    phi1      => phi1,
374 
    input12_1  => output11_2,
375 
    output12_1 => input_bigx_1);        -- Big "final" XOR
376 
 
377 
 
378 
end structural;
379 
 
380 
-- Now it is time to define each component and the way they work
381 
 
382 
architecture Input1_2 of CRC_top is
383 
 
384 
begin  -- Input1_2
385 
 
386 
  if reset='0' then output1_2 <= X'00000000'
387 
     elsif phi2='1' and phi2'event then output1_2 <= input1_2;
388 
  end if;
389 
 
390 
end Input1_2;
391 
 
392 
 
393 
architecture Input2_1 of CRC_top is
394 
 
395 
begin  -- Input2_1
396 
 
397 
  if reset='0' then output2_1 <= X'00000000'
398 
     elsif phi1='1' and phi1'event then output2_1 <= input2_1;
399 
  end if;
400 
 
401 
end Input2_1;
402 
 
403 
 
404 
architecture Input3_2 of CRC_top is
405 
 
406 
begin  -- Input3_2
407 
 
408 
  if reset='0' then output3_2 <= X'00000000'
409 
     elsif phi2='1' and phi2'event then output3_2 <= input3_2;
410 
  end if;
411 
 
412 
end Input3_2;
413 
 
414 
 
415 
architecture Input4_1 of CRC_top is
416 
 
417 
begin  -- Input4_1
418 
 
419 
  if reset='0' then output4_1 <= X'00000000'
420 
     elsif phi1='1' and phi1'event then output4_1 <= input4_1;
421 
  end if;
422 
 
423 
end Input4_1;
424 
 
425 
 
426 
architecture Input5_2 of CRC_top is
427 
 
428 
begin  -- Input5_2
429 
 
430 
  if reset='0' then output5_2 <= X'00000000'
431 
     elsif phi2='1' and phi2'event then output5_2 <= input5_2;
432 
  end if;
433 
 
434 
end Input5_2;
435 
 
436 
 
437 
architecture Input6_1 of CRC_top is
438 
 
439 
begin  -- Input6_1
440 
 
441 
  if reset='0' then output6_1 <= X'00000000'
442 
     elsif phi1='1' and phi1'event then output6_1 <= input6_1;
443 
  end if;
444 
 
445 
end Input6_1;
446 
 
447 
 
448 
architecture Input7_2 of CRC_top is
449 
 
450 
begin  -- Input7_2
451 
 
452 
  if reset='0' then output7_2 <= X'00000000'
453 
     elsif phi2='1' and phi2'event then output7_2 <= input7_2;
454 
  end if;
455 
 
456 
end Input7_2;
457 
 
458 
 
459 
architecture Input8_1 of CRC_top is
460 
 
461 
begin  -- Input8_1
462 
 
463 
  if reset='0' then output8_1 <= X'00000000'
464 
     elsif phi1='1' and phi1'event then output8_1 <= input8_1;
465 
  end if;
466 
 
467 
end Input8_1;
468 
 
469 
 
470 
architecture Input9_2 of CRC_top is
471 
 
472 
begin  -- Input9_2
473 
 
474 
  if reset='0' then output9_2 <= X'00000000'
475 
     elsif phi2='1' and phi2'event then output9_2 <= input9_2;
476 
  end if;
477 
 
478 
end Input9_2;
479 
 
480 
 
481 
architecture Input10_1 of CRC_top is
482 
 
483 
begin  -- Input10_1
484 
 
485 
  if reset='0' then output10_1 <= X'00000000'
486 
     elsif phi1='1' and phi1'event then output10_1 <= input10_1;
487 
  end if;
488 
 
489 
end Input10_1;
490 
 
491 
 
492 
architecture Input11_2 of CRC_top is
493 
 
494 
begin  -- Input11_2
495 
 
496 
  if reset='0' then output11_2 <= X'00000000'
497 
     elsif phi2='1' and phi2'event then output11_2 <= input11_2;
498 
  end if;
499 
 
500 
end Input11_2;
501 
 
502 
 
503 
architecture Input12_1 of CRC_top is
504 
 
505 
begin  -- Input12_1
506 
 
507 
  if reset='0' then output12_1 <= X'00000000'
508 
     elsif phi1='1' and phi1'event then output12_1 <= input12_1;
509 
  end if;
510 
 
511 
end Input2_1;
512 
 
513 
-- Galois Field multiplier
514 
 
515 
architecture GF1_xor_2 of CRC_top is
516 
 
517 
begin  -- GF1_xor_2
518 
 
519 
  port map (
520 
    input_gf1x_2  => fcs_out13_2,
521 
    output_gf1x_2 => input_gf2_1 (31 downto 0));
522 
 
523 
  -- Some area optimizations could be done, since we don't use all
524 
  -- the 32 bits of the fcs
525 
 
526 
  output_gf1x_2 (31 => (input_gf1x_2(9) xor input_gf1x_2(15)),
527 
                 30 => (input_gf1x_2(8) xor input_gf1x_2(9)),
528 
                 29 => (input_gf1x_2(7) xor input_gf1x_2(8)),
529 
                 28 => (input_gf1x_2(6) xor input_gf1x_2(7)),
530 
                 27 => (input_gf1x_2(5) xor input_gf1x_2(6)),
531 
                 26 => (input_gf1x_2(4) xor input_gf1x_2(5)),
532 
                 25 => (input_gf1x_2(3) xor input_gf1x_2(4)),
533 
                 24 => (input_gf1x_2(2) xor input_gf1x_2(3)),
534 
                 23 => (input_gf1x_2(1) xor input_gf1x_2(1)),
535 
                 22 => (input_gf1x_2(0) xor input_gf1x_2(1)),
536 
                 21 => (input_gf1x_2(0) xor input_gf1x_2(1)),
537 
                 20 => (input_gf1x_2(0) xor input_gf1x_2(2)),
538 
                 19 => (input_gf1x_2(1) xor input_gf1x_2(2)),
539 
                 18 => (input_gf1x_2(0) xor input_gf1x_2(1)),
540 
                 17 => (input_gf1x_2(0) xor input_gf1x_2(1)),
541 
                 16 => (input_gf1x_2(0) xor input_gf1x_2(6)),
542 
                 15 => (input_gf1x_2(5) xor input_gf1x_2(6)),
543 
                 14 => (input_gf1x_2(4) xor input_gf1x_2(5)),
544 
                 13 => (input_gf1x_2(3) xor input_gf1x_2(4)),
545 
                 12 => (input_gf1x_2(2) xor input_gf1x_2(3)),
546 
                 11 => (input_gf1x_2(1) xor input_gf1x_2(2)),
547 
                 10 => (input_gf1x_2(0) xor input_gf1x_2(1)),
548 
                 9 => (input_gf1x_2(0) xor input_gf1x_2(1)),
549 
                 8 => (input_gf1x_2(0) xor input_gf1x_2(3)),
550 
                 7 => (input_gf1x_2(2) xor input_gf1x_2(3)),
551 
                 6 => (input_gf1x_2(1) xor input_gf1x_2(2)),
552 
                 5 => (input_gf1x_2(0) xor input_gf1x_2(1)),
553 
                 4 => (input_gf1x_2(0) xor input_gf1x_2(5)),
554 
                 3 => (input_gf1x_2(4) xor input_gf1x_2(7)),
555 
                 2 => (input_gf1x_2(3) xor input_gf1x_2(6)),
556 
                 1 => (input_gf1x_2(2) xor input_gf1x_2(5)),
557 
 
558 
 
559 
 
560 
end GF1_xor_2;
561 
 
562 
architecture GF2_1 of CRC_top is
563 
 
564 
begin  -- GF2_1
565 
 
566 
  port map (
567 
    reset                         => reset,
568 
    phi1                          => phi1,
569 
    input_gf2_1 (63 downto 32)    => fcs_13_2,
570 
    input_gf2_1 (31 downto 0)     => output_gf1x_2,
571 
    output_gf2_1 (63 downto 32)   => input_gf3_2,
572 
    output_gf2_1 (31 downto 0)    => input_gf2x_1);
573 
 
574 
  if reset='0' then output_gf2_1 <= X'0000000000000000'
575 
     elsif phi1='1' and phi1'event then output_gf2_1 <= input_gf2_1;
576 
  end if;
577 
 
578 
end GF2_1;
579 
 
580 
 
581 
architecture GF2_xor_1 of CRC_top is
582 
 
583 
begin  -- GF2_xor_1
584 
 
585 
  port map (
586 
    input_gf2x_1  => output_gf2_1 (31 downto 0),
587 
    output_gf2x_1 => input_gf3_2 (31 downto 0));
588 
 
589 
  -- Some area optimizations could be done, since we don't use all
590 
  -- the 32 bits of the fcs
591 
 
592 
  output_gf2x_1 (31 => input_gf2x_1(31),
593 
                 30 => (input_gf2x_1(30) xor output_gf2_1(14+32)),
594 
                 29 => (input_gf2x_1(29) xor output_gf2_1(9+32)),
595 
                 28 => (input_gf2x_1(28) xor output_gf2_1(8+32)),
596 
                 27 => (input_gf2x_1(27) xor output_gf2_1(7+32)),
597 
                 26 => (input_gf2x_1(26) xor output_gf2_1(6+32)),
598 
                 25 => (input_gf2x_1(25) xor output_gf2_1(5+32)),
599 
                 24 => (input_gf2x_1(24) xor output_gf2_1(4+32)),
600 
                 23 => (input_gf2x_1(23) xor output_gf2_1(3+32)),
601 
                 22 => (input_gf2x_1(22) xor output_gf2_1(2+32)),
602 
                 21 => (input_gf2x_1(21) xor output_gf2_1(3+32)),
603 
                 20 => (input_gf2x_1(20) xor output_gf2_1(3+32)),
604 
                 19 => (input_gf2x_1(19) xor output_gf2_1(3+32)),
605 
                 18 => (input_gf2x_1(18) xor output_gf2_1(2+32)),
606 
                 17 => (input_gf2x_1(17) xor output_gf2_1(7+32)),
607 
                 16 => (input_gf2x_1(16) xor output_gf2_1(7+32)),
608 
                 15 => (input_gf2x_1(15) xor output_gf2_1(7+32)),
609 
                 14 => (input_gf2x_1(14) xor output_gf2_1(6+32)),
610 
                 13 => (input_gf2x_1(13) xor output_gf2_1(5+32)),
611 
                 12 => (input_gf2x_1(12) xor output_gf2_1(4+32)),
612 
                 11 => (input_gf2x_1(11) xor output_gf2_1(3+32)),
613 
                 10 => (input_gf2x_1(10) xor output_gf2_1(2+32)),
614 
                 9 => (input_gf2x_1(9) xor output_gf2_1(4+32)),
615 
                 8 => (input_gf2x_1(8) xor output_gf2_1(4+32)),
616 
                 7 => (input_gf2x_1(7) xor output_gf2_1(8+32)),
617 
                 6 => (input_gf2x_1(6) xor output_gf2_1(7+32)),
618 
                 5 => (input_gf2x_1(5) xor output_gf2_1(6+32)),
619 
                 4 => (input_gf2x_1(4) xor output_gf2_1(8+32)),
620 
                 3 => (input_gf2x_1(3) xor output_gf2_1(9+32)),
621 
                 2 => (input_gf2x_1(2) xor output_gf2_1(8+32)),
622 
                 1 => (input_gf2x_1(1) xor output_gf2_1(7+32)),
623 
 
624 
 
625 
 
626 
end GF2_xor_1;
627 
 
628 
architecture GF3_2 of CRC_top is
629 
 
630 
begin  -- GF3_2
631 
 
632 
  port map (
633 
    reset                         => reset,
634 
    phi2                          => phi2,
635 
    input_gf3_2 (63 downto 32)    => output_gf2_1 (63 downto 32),
636 
    input_gf3_2 (31 downto 0)     => output_gf2x_1,
637 
    output_gf3_2 (63 downto 32)   => input_gf4_1,
638 
    output_gf3_2 (31 downto 0)    => input_gf3x_2);
639 
 
640 
  if reset='0' then output_gf3_2 <= X'0000000000000000'
641 
     elsif phi2='1' and phi2'event then output_gf3_2 <= input_gf3_2;
642 
  end if;
643 
 
644 
end GF3_2;
645 
 
646 
 
647 
architecture GF3_xor_2 of CRC_top is
648 
 
649 
begin  -- GF3_xor_2
650 
 
651 
  port map (
652 
    input_gf3x_2  => output_gf3_2 (31 downto 0),
653 
    output_gf3x_2 => input_gf4_1 (31 downto 0));
654 
 
655 
  -- Some area optimizations could be done, since we don't use all
656 
  -- the 32 bits of the fcs
657 
 
658 
  output_gf3x_2 (31 => input_gf3x_1(31),
659 
                 30 => (input_gf3x_1(30) xor output_gf3_2(15+32)),
660 
                 29 => (input_gf3x_1(29) xor output_gf3_2(13+32)),
661 
                 28 => (input_gf3x_1(28) xor output_gf3_2(12+32)),
662 
                 27 => (input_gf3x_1(27) xor output_gf3_2(9+32)),
663 
                 26 => (input_gf3x_1(26) xor output_gf3_2(8+32)),
664 
                 25 => (input_gf3x_1(25) xor output_gf3_2(7+32)),
665 
                 24 => (input_gf3x_1(24) xor output_gf3_2(6+32)),
666 
                 23 => (input_gf3x_1(23) xor output_gf3_2(5+32)),
667 
                 22 => (input_gf3x_1(22) xor output_gf3_2(4+32)),
668 
                 21 => (input_gf3x_1(21) xor output_gf3_2(4+32)),
669 
                 20 => (input_gf3x_1(20) xor output_gf3_2(4+32)),
670 
                 19 => (input_gf3x_1(19) xor output_gf3_2(9+32)),
671 
                 18 => (input_gf3x_1(18) xor output_gf3_2(8+32)),
672 
                 17 => (input_gf3x_1(17) xor output_gf3_2(8+32)),
673 
                 16 => (input_gf3x_1(16) xor output_gf3_2(8+32)),
674 
                 15 => (input_gf3x_1(15) xor output_gf3_2(10+32)),
675 
                 14 => (input_gf3x_1(14) xor output_gf3_2(9+32)),
676 
                 13 => (input_gf3x_1(13) xor output_gf3_2(8+32)),
677 
                 12 => (input_gf3x_1(12) xor output_gf3_2(7+32)),
678 
                 11 => (input_gf3x_1(11) xor output_gf3_2(6+32)),
679 
                 10 => (input_gf3x_1(10) xor output_gf3_2(5+32)),
680 
                 9 => (input_gf3x_1(9) xor output_gf3_2(5+32)),
681 
                 8 => (input_gf3x_1(8) xor output_gf3_2(9+32)),
682 
                 7 => (input_gf3x_1(7) xor output_gf3_2(13+32)),
683 
                 6 => (input_gf3x_1(6) xor output_gf3_2(12+32)),
684 
                 5 => (input_gf3x_1(5) xor output_gf3_2(9+32)),
685 
                 4 => (input_gf3x_1(4) xor output_gf3_2(10+32)),
686 
                 3 => (input_gf3x_1(3) xor output_gf3_2(10+32)),
687 
                 2 => (input_gf3x_1(2) xor output_gf3_2(9+32)),
688 
                 1 => (input_gf3x_1(1) xor output_gf3_2(8+32)),
689 
 
690 
 
691 
 
692 
end GF3_xor_2;
693 
 
694 
architecture GF4_1 of CRC_top is
695 
 
696 
begin  -- GF4_1
697 
 
698 
  port map (
699 
    reset                         => reset,
700 
    phi1                          => phi1,
701 
    input_gf4_1 (63 downto 32)    => output_gf3_2 (63 downto 32),
702 
    input_gf4_1 (31 downto 0)     => output_gf3x_2,
703 
    output_gf4_1 (63 downto 32)   => input_gf5_2,
704 
    output_gf4_1 (31 downto 0)    => input_gf4x_1);
705 
 
706 
  if reset='0' then output_gf4_1 <= X'0000000000000000'
707 
     elsif phi1='1' and phi1'event then output_gf4_1 <= input_gf4_1;
708 
  end if;
709 
 
710 
end GF4_1;
711 
 
712 
 
713 
architecture GF4_xor_1 of CRC_top is
714 
 
715 
begin  -- GF4_xor_1
716 
 
717 
  port map (
718 
    input_gf4x_1  => output_gf4_1 (31 downto 0),
719 
    output_gf4x_1 => input_gf5_2 (31 downto 0));
720 
 
721 
  -- Some area optimizations could be done, since we don't use all
722 
  -- the 32 bits of the fcs
723 
 
724 
  output_gfx4_1 (31 => input_gf4x_1(31),
725 
                 30 => input_gf4x_1(30),
726 
                 29 => (input_gf4x_1(29) xor output_gf4_1(14+32)),
727 
                 28 => (input_gf4x_1(28) xor output_gf4_1(13+32)),
728 
                 27 => (input_gf4x_1(27) xor output_gf4_1(11+32)),
729 
                 26 => (input_gf4x_1(26) xor output_gf4_1(9+32)),
730 
                 25 => (input_gf4x_1(25) xor output_gf4_1(8+32)),
731 
                 24 => (input_gf4x_1(24) xor output_gf4_1(7+32)),
732 
                 23 => (input_gf4x_1(23) xor output_gf4_1(6+32)),
733 
                 22 => (input_gf4x_1(22) xor output_gf4_1(5+32)),
734 
                 21 => (input_gf4x_1(21) xor output_gf4_1(5+32)),
735 
                 20 => (input_gf4x_1(20) xor output_gf4_1(11+32)),
736 
                 19 => (input_gf4x_1(19) xor output_gf4_1(10+32)),
737 
                 18 => (input_gf4x_1(18) xor output_gf4_1(9+32)),
738 
                 17 => (input_gf4x_1(17) xor output_gf4_1(9+32)),
739 
                 16 => (input_gf4x_1(16) xor output_gf4_1(10+32)),
740 
                 15 => (input_gf4x_1(15) xor output_gf4_1(11+32)),
741 
                 14 => (input_gf4x_1(14) xor output_gf4_1(10+32)),
742 
                 13 => (input_gf4x_1(13) xor output_gf4_1(9+32)),
743 
                 12 => (input_gf4x_1(12) xor output_gf4_1(8+32)),
744 
                 11 => (input_gf4x_1(11) xor output_gf4_1(7+32)),
745 
                 10 => (input_gf4x_1(10) xor output_gf4_1(6+32)),
746 
                 9 => (input_gf4x_1(9) xor output_gf4_1(15+32)),
747 
                 8 => (input_gf4x_1(8) xor output_gf4_1(14+32)),
748 
                 7 => (input_gf4x_1(7) xor output_gf4_1(14+32)),
749 
                 6 => (input_gf4x_1(6) xor output_gf4_1(13+32)),
750 
                 5 => (input_gf4x_1(5) xor output_gf4_1(11+32)),
751 
                 4 => (input_gf4x_1(4) xor output_gf4_1(11+32)),
752 
                 3 => (input_gf4x_1(3) xor output_gf4_1(13+32)),
753 
                 2 => (input_gf4x_1(2) xor output_gf4_1(12+32)),
754 
                 1 => (input_gf4x_1(1) xor output_gf4_1(11+32)),
755 
 
756 
 
757 
 
758 
end GF4_xor_1;
759 
 
760 
architecture GF5_2 of CRC_top is
761 
 
762 
begin  -- GF5_2
763 
 
764 
  port map (
765 
    reset                         => reset,
766 
    phi2                          => phi2,
767 
    input_gf5_2 (63 downto 32)    => output_gf4_1 (63 downto 32),
768 
    input_gf5_2 (31 downto 0)     => output_gf4x_1,
769 
    output_gf5_2 (63 downto 32)   => input_gf6_1 (63 downto 32),
770 
    output_gf5_2 (31 downto 0)    => input_gf5x_2);
771 
 
772 
  if reset='0' then output_gf5_2 <= X'0000000000000000'
773 
     elsif phi2='1' and phi2'event then output_gf5_2 <= input_gf5_2;
774 
  end if;
775 
 
776 
end GF5_2;
777 
 
778 
 
779 
architecture GF5_xor_2 of CRC_top is
780 
 
781 
begin  -- GF5_xor_2
782 
 
783 
  port map (
784 
    input_gf5x_2  => output_gf5_2 (31 downto 0),
785 
    output_gf5x_2 => input_gf6_1 (31 downto 0));
786 
 
787 
  -- Some area optimizations could be done, since we don't use all
788 
  -- the 32 bits of the fcs
789 
 
790 
  output_gf5x_2 (31 => input_gf5x_2(31),
791 
                 30 => input_gf5x_2(30),
792 
                 29 => (input_gf5x_2(29) xor output_gf5_2(15+32)),
793 
                 28 => (input_gf5x_2(28) xor output_gf5_2(14+32)),
794 
                 27 => (input_gf5x_2(27) xor output_gf5_2(12+32)),
795 
                 26 => (input_gf5x_2(26) xor output_gf5_2(10+32)),
796 
                 25 => (input_gf5x_2(25) xor output_gf5_2(9+32)),
797 
                 24 => (input_gf5x_2(24) xor output_gf5_2(8+32)),
798 
                 23 => (input_gf5x_2(23) xor output_gf5_2(7+32)),
799 
                 22 => (input_gf5x_2(22) xor output_gf5_2(6+32)),
800 
                 21 => (input_gf5x_2(21) xor output_gf5_2(10+32)),
801 
                 20 => (input_gf5x_2(20) xor output_gf5_2(12+32)),
802 
                 19 => (input_gf5x_2(19) xor output_gf5_2(11+32)),
803 
                 18 => (input_gf5x_2(18) xor output_gf5_2(10+32)),
804 
                 17 => (input_gf5x_2(17) xor output_gf5_2(11+32)),
805 
                 16 => (input_gf5x_2(16) xor output_gf5_2(11+32)),
806 
                 15 => (input_gf5x_2(15) xor output_gf5_2(15+32)),
807 
                 14 => (input_gf5x_2(14) xor output_gf5_2(14+32)),
808 
                 13 => (input_gf5x_2(13) xor output_gf5_2(13+32)),
809 
                 12 => (input_gf5x_2(12) xor output_gf5_2(12+32)),
810 
                 11 => (input_gf5x_2(11) xor output_gf5_2(11+32)),
811 
                 10 => (input_gf5x_2(10) xor output_gf5_2(10+32)),
812 
                 9 => (input_gf5x_2(9) xor output_gf5_2(25+32)),
813 
                 8 => (input_gf5x_2(8) xor output_gf5_2(15+32)),
814 
                 7 => (input_gf5x_2(7) xor output_gf5_2(23+32)),
815 
                 6 => (input_gf5x_2(6) xor output_gf5_2(22+32)),
816 
                 5 => (input_gf5x_2(5) xor output_gf5_2(12+32)),
817 
                 4 => (input_gf5x_2(4) xor output_gf5_2(14+32)),
818 
                 3 => (input_gf5x_2(3) xor output_gf5_2(19+32)),
819 
                 2 => (input_gf5x_2(2) xor output_gf5_2(18+32)),
820 
                 1 => (input_gf5x_2(1) xor output_gf5_2(17+32)),
821 
 
822 
 
823 
 
824 
end GF5_xor_2;
825 
 
826 
architecture GF6_1 of CRC_top is
827 
 
828 
begin  -- GF6_1
829 
 
830 
  port map (
831 
    reset                         => reset,
832 
    phi1                          => phi1,
833 
    input_gf6_1 (63 downto 32)    => output_gf5_2 (63 downto 32),
834 
    input_gf6_1 (31 downto 0)     => output_gf5x_2,
835 
    output_gf6_1 (63 downto 32)   => input_gf7_2 (63 downto 32),
836 
    output_gf6_1 (31 downto 0)    => input_gf6x_1);
837 
 
838 
  if reset='0' then output_gf6_1 <= X'0000000000000000'
839 
     elsif phi1='1' and phi1'event then output_gf6_1 <= input_gf6_1;
840 
  end if;
841 
 
842 
end GF6_1;
843 
 
844 
 
845 
architecture GF6_xor_1 of CRC_top is
846 
 
847 
begin  -- GF5_xor_1
848 
 
849 
  port map (
850 
    input_gf6x_1  => output_gf6_1 (31 downto 0),
851 
    output_gf6x_1 => input_gf7_2 (31 downto 0));
852 
 
853 
  -- Some area optimizations could be done, since we don't use all
854 
  -- the 32 bits of the fcs
855 
 
856 
  output_gf6x_1 (31 => input_gf6x_1(31),
857 
                 30 => input_gf6x_1(30),
858 
                 29 => input_gf6x_1(29),
859 
                 28 => input_gf6x_1(28),
860 
                 27 => (input_gf6x_1(27) xor output_gf6_1(13+32)),
861 
                 26 => (input_gf6x_1(26) xor output_gf6_1(11+32)),
862 
                 25 => (input_gf6x_1(25) xor output_gf6_1(10+32)),
863 
                 24 => (input_gf6x_1(24) xor output_gf6_1(10+32)),
864 
                 23 => (input_gf6x_1(23) xor output_gf6_1(11+32)),
865 
                 22 => (input_gf6x_1(22) xor output_gf6_1(10+32)),
866 
                 21 => (input_gf6x_1(21) xor output_gf6_1(12+32)),
867 
                 20 => (input_gf6x_1(20) xor output_gf6_1(14+32)),
868 
                 19 => (input_gf6x_1(19) xor output_gf6_1(13+32)),
869 
                 18 => (input_gf6x_1(18) xor output_gf6_1(12+32)),
870 
                 17 => (input_gf6x_1(17) xor output_gf6_1(12+32)),
871 
                 16 => (input_gf6x_1(16) xor output_gf6_1(12+32)),
872 
                 15 => (input_gf6x_1(15) xor output_gf6_1(31+32)),
873 
                 14 => (input_gf6x_1(14) xor output_gf6_1(30+32)),
874 
                 13 => (input_gf6x_1(13) xor output_gf6_1(29+32)),
875 
                 12 => (input_gf6x_1(12) xor output_gf6_1(28+32)),
876 
                 11 => (input_gf6x_1(11) xor output_gf6_1(27+32)),
877 
                 10 => (input_gf6x_1(10) xor output_gf6_1(26+32)),
878 
                 9 => (input_gf6x_1(9) xor '0'),
879 
                 8 => (input_gf6x_1(8) xor output_gf6_1(24+32)),
880 
                 7 => (input_gf6x_1(7) xor '0'),
881 
                 6 => (input_gf6x_1(6) xor '0'),
882 
                 5 => (input_gf6x_1(5) xor output_gf6_1(15+32)),
883 
                 4 => (input_gf6x_1(4) xor output_gf6_1(20+32)),
884 
                 3 => (input_gf6x_1(3) xor '0'),
885 
                 2 => (input_gf6x_1(2) xor '0'),
886 
                 1 => (input_gf6x_1(1) xor '0'),
887 
 
888 
 
889 
 
890 
end GF6_xor_1;
891 
 
892 
architecture GF7_2 of CRC_top is
893 
 
894 
begin  -- GF7_2
895 
 
896 
  port map (
897 
    reset                         => reset,
898 
    phi2                          => phi2,
899 
    input_gf7_2 (63 downto 32)    => output_gf6_1 (63 downto 32),
900 
    input_gf7_2 (31 downto 0)     => output_gf6x_1,
901 
    output_gf7_2 (63 downto 32)   => input_gf8_1 (63 downto 32),
902 
    output_gf7_2 (31 downto 0)    => input_gf7x_2);
903 
 
904 
  if reset='0' then output_gf7_2 <= X'0000000000000000'
905 
     elsif phi2='1' and phi2'event then output_gf7_2 <= input_gf7_2;
906 
  end if;
907 
 
908 
end GF7_2;
909 
 
910 
 
911 
architecture GF7_xor_2 of CRC_top is
912 
 
913 
begin  -- GF7_xor_2
914 
 
915 
  port map (
916 
    input_gf7x_2  => output_gf7_2 (31 downto 0),
917 
    output_gf7x_2 => input_gf8_1 (31 downto 0));
918 
 
919 
  -- Some area optimizations could be done, since we don't use all
920 
  -- the 32 bits of the fcs
921 
 
922 
  output_gf7x_2 (31 => input_gf7x_2(31),
923 
                 30 => input_gf7x_2(30),
924 
                 29 => input_gf7x_2(29),
925 
                 28 => input_gf7x_2(28),
926 
                 27 => (input_gf7x_2(27) xor output_gf7_2(15+32)),
927 
                 26 => (input_gf7x_2(26) xor output_gf7_2(12+32)),
928 
                 25 => (input_gf7x_2(25) xor output_gf7_2(11+32)),
929 
                 24 => (input_gf7x_2(24) xor output_gf7_2(12+32)),
930 
                 23 => (input_gf7x_2(23) xor output_gf7_2(12+32)),
931 
                 22 => (input_gf7x_2(22) xor output_gf7_2(11+32)),
932 
                 21 => (input_gf7x_2(21) xor output_gf7_2(13+32)),
933 
                 20 => (input_gf7x_2(20) xor output_gf7_2(15+32)),
934 
                 19 => (input_gf7x_2(19) xor output_gf7_2(14+32)),
935 
                 18 => (input_gf7x_2(18) xor output_gf7_2(13+32)),
936 
                 17 => (input_gf7x_2(17) xor output_gf7_2(13+32)),
937 
                 16 => (input_gf7x_2(16) xor '0'),
938 
                 15 => (input_gf7x_2(15) xor '0'),
939 
                 14 => (input_gf7x_2(14) xor '0'),
940 
                 13 => (input_gf7x_2(13) xor '0'),
941 
                 12 => (input_gf7x_2(12) xor '0'),
942 
                 11 => (input_gf7x_2(11) xor '0'),
943 
                 10 => (input_gf7x_2(10) xor '0'),
944 
                 9 => input_gf7x_2(9),
945 
                 8 => (input_gf7x_2(8) xor '0'),
946 
                 7 => input_gf7x_2(7),
947 
                 6 => input_gf7x_2(6),
948 
                 5 => (input_gf7x_2(5) xor '0'),
949 
                 4 => (input_gf7x_2(4) xor '0'),
950 
                 3 => input_gf7x_2(3),
951 
                 2 => input_gf7x_2(2),
952 
                 1 => input_gf7x_2(1),
953 
 
954 
 
955 
 
956 
end GF7_xor_2;
957 
 
958 
architecture GF8_1 of CRC_top is
959 
 
960 
begin  -- GF8_1
961 
 
962 
  port map (
963 
    reset                         => reset,
964 
    phi1                          => phi1,
965 
    input_gf8_1 (63 downto 32)    => output_gf7_2 (63 downto 32),
966 
    input_gf8_1 (31 downto 0)     => output_gf7x_2,
967 
    output_gf8_1 (63 downto 32)   => input_gf9_2 (63 downto 32),
968 
    output_gf8_1 (31 downto 0)    => input_gf8x_1);
969 
 
970 
  if reset='0' then output_gf8_1 <= X'0000000000000000'
971 
     elsif phi1='1' and phi1'event then output_gf8_1 <= input_gf8_1;
972 
  end if;
973 
 
974 
end GF8_1;
975 
 
976 
 
977 
architecture GF8_xor_1 of CRC_top is
978 
 
979 
begin  -- GF8_xor_1
980 
 
981 
  port map (
982 
    input_gf8x_1  => output_gf8_1 (31 downto 0),
983 
    output_gf8x_1 => input_gf9_2 (31 downto 0));
984 
 
985 
  -- Some area optimizations could be done, since we don't use all
986 
  -- the 32 bits of the fcs
987 
 
988 
  output_gf8x_1 (31 => input_gf8x_1(31),
989 
                 30 => input_gf8x_1(30),
990 
                 29 => input_gf8x_1(29),
991 
                 28 => input_gf8x_1(28),
992 
                 27 => input_gf8x_1(27),
993 
                 26 => (input_gf8x_1(26) xor output_gf8_1(14+32)),
994 
                 25 => (input_gf8x_1(25) xor output_gf8_1(13+32)),
995 
                 24 => (input_gf8x_1(24) xor output_gf8_1(13+32)),
996 
                 23 => (input_gf8x_1(23) xor output_gf8_1(14+32)),
997 
                 22 => (input_gf8x_1(22) xor output_gf8_1(13+32)),
998 
                 21 => (input_gf8x_1(21) xor output_gf8_1(15+32)),
999 
                 20 => input_gf8x_1(20),
1000 
                 19 => (input_gf8x_1(19) xor output_gf8_1(15+32)),
1001 
                 18 => (input_gf8x_1(18) xor output_gf8_1(14+32)),
1002 
                 17 => (input_gf8x_1(17) xor '0'),
1003 
                 16 => input_gf8x_1(16),
1004 
                 15 => input_gf8x_1(15),
1005 
                 14 => input_gf8x_1(14),
1006 
                 13 => input_gf8x_1(13),
1007 
                 12 => input_gf8x_1(12),
1008 
                 11 => input_gf8x_1(11),
1009 
                 10 => input_gf8x_1(10),
1010 
                 9 => input_gf8x_1(9),
1011 
                 8 => input_gf8x_1(8),
1012 
                 7 => input_gf8x_1(7),
1013 
                 6 => input_gf8x_1(6),
1014 
                 5 => input_gf8x_1(5),
1015 
                 4 => input_gf8x_1(4),
1016 
                 3 => input_gf8x_1(3),
1017 
                 2 => input_gf8x_1(2),
1018 
                 1 => input_gf8x_1(1),
1019 
 
1020 
 
1021 
 
1022 
end GF8_xor_1;
1023 
 
1024 
architecture GF9_2 of CRC_top is
1025 
 
1026 
begin  -- GF9_2
1027 
 
1028 
  port map (
1029 
    reset                         => reset,
1030 
    phi2                          => phi2,
1031 
    input_gf9_2 (63 downto 32)    => output_gf8_1 (63 downto 32),
1032 
    input_gf9_2 (31 downto 0)     => output_gf8x_1,
1033 
    output_gf9_2 (63 downto 32)   => input_gf10_1 (63 downto 32),
1034 
    output_gf9_2 (31 downto 0)    => input_gf9x_2);
1035 
 
1036 
  if reset='0' then output_gf9_2 <= X'0000000000000000'
1037 
     elsif phi2='1' and phi2'event then output_gf9_2 <= input_gf9_2;
1038 
  end if;
1039 
 
1040 
end GF9_2;
1041 
 
1042 
 
1043 
architecture GF9_xor_2 of CRC_top is
1044 
 
1045 
begin  -- GF9_xor_2
1046 
 
1047 
  port map (
1048 
    input_gf9x_2  => output_gf9_2 (31 downto 0),
1049 
    output_gf9x_2 => input_gf10_1 (31 downto 0));
1050 
 
1051 
  -- Some area optimizations could be done, since we don't use all
1052 
  -- the 32 bits of the fcs
1053 
 
1054 
  output_gf9x_2 (31 => input_gf9x_2(31),
1055 
                 30 => input_gf9x_2(30),
1056 
                 29 => input_gf9x_2(29),
1057 
                 28 => input_gf9x_2(28),
1058 
                 27 => input_gf9x_2(27),
1059 
                 26 => (input_gf9x_2(26) xor output_gf9_2(15+32)),
1060 
                 25 => (input_gf9x_2(25) xor output_gf9_2(14+32)),
1061 
                 24 => (input_gf9x_2(24) xor output_gf9_2(15+32)),
1062 
                 23 => (input_gf9x_2(23) xor output_gf9_2(15+32)),
1063 
                 22 => (input_gf9x_2(22) xor output_gf9_2(14+32)),
1064 
                 21 => (input_gf9x_2(21) xor '0'),
1065 
                 20 => input_gf9x_2(20),
1066 
                 19 => (input_gf9x_2(19) xor '0'),
1067 
                 18 => (input_gf9x_2(18) xor '0'),
1068 
                 17 => (input_gf9x_2(17) xor '0'),
1069 
                 16 => input_gf9x_2(16),
1070 
                 15 => input_gf9x_2(15),
1071 
                 14 => input_gf9x_2(14),
1072 
                 13 => input_gf9x_2(13),
1073 
                 12 => input_gf9x_2(12),
1074 
                 11 => input_gf9x_2(11),
1075 
                 10 => input_gf9x_2(10),
1076 
                 9 => input_gf9x_2(9),
1077 
                 8 => input_gf9x_2(8),
1078 
                 7 => input_gf9x_2(7),
1079 
                 6 => input_gf9x_2(6),
1080 
                 5 => input_gf9x_2(5),
1081 
                 4 => input_gf9x_2(4),
1082 
                 3 => input_gf9x_2(3),
1083 
                 2 => input_gf9x_2(2),
1084 
                 1 => input_gf9x_2(1),
1085 
 
1086 
 
1087 
 
1088 
end GF9_xor_2;
1089 
 
1090 
architecture GF10_1 of CRC_top is
1091 
 
1092 
begin  -- GF10_1
1093 
 
1094 
  port map (
1095 
    reset                          => reset,
1096 
    phi1                           => phi1,
1097 
    input_gf10_1 (63 downto 32)    => output_gf9_2 (63 downto 32),
1098 
    input_gf10_1 (31 downto 0)     => output_gf9x_2,
1099 
    output_gf10_1 (63 downto 32)   => input_gf11_2 (63 downto 32),
1100 
    output_gf10_1 (31 downto 0)    => input_gf10x_1);
1101 
 
1102 
  if reset='0' then output_gf10_1 <= X'0000000000000000'
1103 
     elsif phi1='1' and phi1'event then output_gf10_1 <= input_gf10_1;
1104 
  end if;
1105 
 
1106 
end GF10_1;
1107 
 
1108 
 
1109 
architecture GF10_xor_1 of CRC_top is
1110 
 
1111 
begin  -- GF10_xor_1
1112 
 
1113 
  port map (
1114 
    input_gf10x_1  => output_gf10_1 (31 downto 0),
1115 
    output_gf10x_1 => input_gf11_2 (31 downto 0));
1116 
 
1117 
  -- Some area optimizations could be done, since we don't use all
1118 
  -- the 32 bits of the fcs
1119 
 
1120 
  output_gf10x_1 (31 => input_gf10x_1(31),
1121 
                 30 => input_gf10x_1(30),
1122 
                 29 => input_gf10x_1(29),
1123 
                 28 => input_gf10x_1(28),
1124 
                 27 => input_gf10x_1(27),
1125 
                 26 => input_gf10x_1(26),
1126 
                 25 => input_gf10x_1(25),
1127 
                 24 => (input_gf10x_1(24) xor '0'),
1128 
                 23 => (input_gf10x_1(23) xor '0'),
1129 
                 22 => (input_gf10x_1(22) xor '0'),
1130 
                 21 => input_gf10x_1(21),
1131 
                 20 => input_gf10x_1(20),
1132 
                 19 => input_gf10x_1(19),
1133 
                 18 => input_gf10x_1(18),
1134 
                 17 => input_gf10x_1(17),
1135 
                 16 => input_gf10x_1(16),
1136 
                 15 => input_gf10x_1(15),
1137 
                 14 => input_gf10x_1(14),
1138 
                 13 => input_gf10x_1(13),
1139 
                 12 => input_gf10x_1(12),
1140 
                 11 => input_gf10x_1(11),
1141 
                 10 => input_gf10x_1(10),
1142 
                 9 => input_gf10x_1(9),
1143 
                 8 => input_gf10x_1(8),
1144 
                 7 => input_gf10x_1(7),
1145 
                 6 => input_gf10x_1(6),
1146 
                 5 => input_gf10x_1(5),
1147 
                 4 => input_gf10x_1(4),
1148 
                 3 => input_gf10x_1(3),
1149 
                 2 => input_gf10x_1(2),
1150 
                 1 => input_gf10x_1(1),
1151 
 
1152 
 
1153 
 
1154 
end GF10_xor_1;
1155 
 
1156 
architecture GF11_2 of CRC_top is
1157 
 
1158 
begin  -- GF11_2
1159 
 
1160 
  port map (
1161 
    reset         => reset,
1162 
    phi2          => phi2,
1163 
    input_gf11_2  => output_gf10x_1,
1164 
    output_gf11_2 => input_gf12_1;
1165 
 
1166 
  if reset='0' then output_gf11_2 <= X'0000000000000000'
1167 
     elsif phi2='1' and phi2'event then output_gf11_2 <= input_gf11_2;
1168 
  end if;
1169 
 
1170 
end GF11_2;
1171 
 
1172 
 
1173 
architecture GF12_1 of CRC_top is
1174 
 
1175 
begin  -- GF12_1
1176 
 
1177 
  port map (
1178 
    reset         => reset,
1179 
    phi1          => phi1,
1180 
    input_gf12_1  => output_gf11_2,
1181 
    output_gf12_1(15 downto 0) => input_bigx12_1,
1182 
    output_gf12_1(31 downto 16) => input_fcs13_2(31 downto 16);
1183 
 
1184 
  if reset='0' then output_gf12_1 <= X'0000000000000000'
1185 
     elsif phi1='1' and phi1'event then output_gf12_1 <= input_gf12_1;
1186 
  end if;
1187 
 
1188 
end GF12_1;
1189 
 
1190 
-- Final part of the circuit: XOR and output
1191 
 
1192 
architecture Big_XOR_12_1 of CRC_top is
1193 
 
1194 
begin  -- Big_XOR_12_1
1195 
 
1196 
  port map (
1197 
    input_bigx12_1  => input_bigx12_1,
1198 
    output_bigx12_1 => input_fcs13_2(15 downto 0));
1199 
 
1200 
  output_bigx12_1 (15 => (input_bigx12_1(15) xor output12_1(15)),
1201 
                   14 => (input_bigx12_1(14) xor output12_1(14)),
1202 
                   13 => (input_bigx12_1(13) xor output12_1(13)),
1203 
                   12 => (input_bigx12_1(12) xor output12_1(12)),
1204 
                   11 => (input_bigx12_1(11) xor output12_1(11)),
1205 
                   10 => (input_bigx12_1(10) xor output12_1(10)),
1206 
                    9 => (input_bigx12_1(9) xor output12_1(9)),
1207 
                    8 => (input_bigx12_1(8) xor output12_1(8)),
1208 
                    7 => (input_bigx12_1(7) xor output12_1(7)),
1209 
                    6 => (input_bigx12_1(6) xor output12_1(6)),
1210 
                    5 => (input_bigx12_1(5) xor output12_1(5)),
1211 
                    4 => (input_bigx12_1(4) xor output12_1(4)),
1212 
                    3 => (input_bigx12_1(3) xor output12_1(3)),
1213 
                    2 => (input_bigx12_1(2) xor output12_1(2)),
1214 
                    1 => (input_bigx12_1(1) xor output12_1(1)),
1215 
 
1216 
 
1217 
end Big_XOR_12_1;
1218 
 
1219 
architecture FCS_out_13_2 of CRC_top is
1220 
 
1221 
begin  -- FCS_out_13_2
1222 
 
1223 
  port map (
1224 
    reset                       => reset,
1225 
    phi2                        => phi2,
1226 
    input_fcs13_2(15 downto 0)  => output_bigx12_1,
1227 
    input_fcs13_2(31 downto 16) => output_gf12_1,
1228 
    output_fcs13_2              => input_gf1x_2, output_fcs13_2);
1229 
 
1230 
end FCS_out_13_2;

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