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trueno |
library IEEE;
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use IEEE.std_logic_1164.all;
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entity CRC_top is
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port (
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phi1 : in std_logic;
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-- We will use the two phase discipline
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-- which we don't generate.
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phi2 : in std_logic;
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reset : in std_logic; -- #RESET
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input : in std_logic_vector(15 downto 0);
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-- The serial/parallel conversion has been made somewhere else
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FCS_out : out std_logic_vector(31 downto 0));
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end CRC_top;
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architecture structural of CRC_top is
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begin -- Structural description of the CRC
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-- We will describe all the pipelining steps
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-- These first pipelining steps are the "waiting" steps. The data will flow
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-- through the registers.
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-- The nomenclature can be explained in the following way:
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-- Input<stage no.>_<clock phase> => Registers in the "wait" region
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-- For the Galois Field multiplier:
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-- GF<stage no.>_<clock phase> => Registers of the GF multiplier
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-- GF<stage no.>_xor_<clock phase> => Combinational logic of the GF mult.
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component Input1_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input1_2 : in std_logic_vector (15 downto 0); -- Directly from the serial/parallel register
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output1_2 : out std_logic_vector (15 downto 0)); -- To the next step
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end component;
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component Input2_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input2_1 : in std_logic_vector (15 downto 0);
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output2_1 : out std_logic_vector (15 downto 0));
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end component;
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component Input3_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input3_2 : in std_logic_vector (15 downto 0);
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output3_2 : out std_logic_vector (15 downto 0));
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end component;
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component Input4_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input4_1 : in std_logic_vector (15 downto 0);
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output4_1 : out std_logic_vector (15 downto 0));
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end component;
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component Input5_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input5_2 : in std_logic_vector (15 downto 0);
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output5_2 : out std_logic_vector (15 downto 0));
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end component;
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component Input6_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input6_1 : in std_logic_vector (15 downto 0);
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output6_1 : out std_logic_vector (15 downto 0));
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end component;
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component Input7_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input7_2 : in std_logic_vector (15 downto 0);
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output7_2 : out std_logic_vector (15 downto 0));
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end component;
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component Input8_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input8_1 : in std_logic_vector (15 downto 0);
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output8_1 : out std_logic_vector (15 downto 0));
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end component;
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component Input9_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input9_2 : in std_logic_vector (15 downto 0);
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output9_2 : out std_logic_vector (15 downto 0));
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end component;
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component Input10_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input10_1 : in std_logic_vector (15 downto 0);
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output10_1 : out std_logic_vector (15 downto 0));
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end component;
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component Input11_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input11_2 : in std_logic_vector (15 downto 0);
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output11_2 : out std_logic_vector (15 downto 0));
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end component;
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component Input12_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input12_1 : in std_logic_vector (15 downto 0);
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output12_1 : out std_logic_vector (15 downto 0));
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end component;
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-- Galois Field pipelining registers and combinational stuff
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component GF1_xor_2
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port (
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input_gf1x_2 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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output_gf1x_2 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF2_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input_gf2_1 : in std_logic_vector (63 downto 0);
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output_gf2_1 : out std_logic_vector (63 downto 0));
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end component;
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component GF2_xor_1
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port (
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input_gf2x_1 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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output_gf2x_1 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF3_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input_gf3_2 : in std_logic_vector (63 downto 0);
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output_gf3_2 : out std_logic_vector (63 downto 0));
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end component;
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component GF3_xor_2
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port (
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input_gf3x_2 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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output_gf3x_2 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF4_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input_gf4_1 : in std_logic_vector (63 downto 0);
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output_gf4_1 : out std_logic_vector (63 downto 0));
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end component;
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component GF4_xor_1
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port (
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input_gf4x_1 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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output_gf4x_1 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF5_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input_gf5_2 : in std_logic_vector (63 downto 0);
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output_gf5_2 : out std_logic_vector (63 downto 0));
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end component;
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component GF5_xor_2
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port (
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input_gf5x_2 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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output_gf5x_2 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF6_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input_gf6_1 : in std_logic_vector (63 downto 0);
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output_gf6_1 : out std_logic_vector (63 downto 0));
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end component;
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component GF6_xor_1
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port (
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input_gf6x_1 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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| 204 |
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output_gf6x_1 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF7_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input_gf7_2 : in std_logic_vector (63 downto 0);
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output_gf7_2 : out std_logic_vector (63 downto 0));
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| 213 |
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end component;
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component GF7_xor_2
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port (
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input_gf7x_2 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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output_gf7x_2 : out std_logic_vector (31 downto 0)); -- The new WIP
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end component;
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component GF8_1
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port (
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reset : in std_logic;
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phi1 : in std_logic;
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input_gf8_1 : in std_logic_vector (63 downto 0);
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output_gf8_1 : out std_logic_vector (63 downto 0));
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end component;
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component GF8_xor_1
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port (
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input_gf8x_1 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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| 232 |
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output_gf8x_1 : out std_logic_vector (31 downto 0)); -- The new WIP
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| 233 |
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end component;
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component GF9_2
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port (
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reset : in std_logic;
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phi2 : in std_logic;
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input_gf9_2 : in std_logic_vector (63 downto 0);
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| 240 |
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output_gf9_2 : out std_logic_vector (63 downto 0));
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end component;
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component GF9_xor_2
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| 244 |
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port (
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input_gf9x_2 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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| 246 |
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output_gf9x_2 : out std_logic_vector (31 downto 0)); -- The new WIP
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| 247 |
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end component;
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| 248 |
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component GF10_1
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| 250 |
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port (
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| 251 |
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reset : in std_logic;
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| 252 |
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phi1 : in std_logic;
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| 253 |
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input_gf10_1 : in std_logic_vector (63 downto 0);
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| 254 |
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output_gf10_1 : out std_logic_vector (63 downto 0));
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| 255 |
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end component;
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component GF10_xor_1
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| 258 |
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port (
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| 259 |
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input_gf10x_1 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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| 260 |
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output_gf10x_1 : out std_logic_vector (31 downto 0)); -- The new WIP
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| 261 |
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end component;
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component GF11_2
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| 264 |
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port (
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| 265 |
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reset : in std_logic;
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| 266 |
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phi2 : in std_logic;
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| 267 |
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input_gf11_2 : in std_logic_vector (63 downto 0);
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| 268 |
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output_gf11_2 : out std_logic_vector (63 downto 0));
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end component;
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-- component GF11_xor_2
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-- port (
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-- input_gf11x_2 : in std_logic_vector (31 downto 0); -- Inputs = WIP + "Original data"
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| 274 |
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-- output_gf11x_2 : out std_logic_vector (31 downto 0)); -- The new WIP
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| 275 |
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-- end component;
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| 276 |
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| 277 |
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component GF12_1
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| 278 |
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port (
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| 279 |
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reset : in std_logic;
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| 280 |
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phi1 : in std_logic;
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| 281 |
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input_gf12_1 : in std_logic_vector (31 downto 0);
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| 282 |
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output_gf12_1 : out std_logic_vector (31 downto 0));
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| 283 |
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end component;
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| 284 |
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| 285 |
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-- Big XOR and output register (FCS)
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| 286 |
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| 287 |
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component Big_XOR12_1
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| 288 |
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port (
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| 289 |
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input_bigx12_1 : in std_logic_vector (15 downto 0);
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| 290 |
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output_bigx12_1 : out std_logic_vector (15 downto 0));
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| 291 |
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end component;
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| 292 |
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| 293 |
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component FCS_out13_2
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| 294 |
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port (
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| 295 |
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reset : in std_logic;
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| 296 |
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phi2 : in std_logic;
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| 297 |
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input_fcs13_2 : in std_logic_vector (31 downto 0);
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| 298 |
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output_fcs13_2 : out std_logic_vector (31 downto 0)); -- FCS_out and feedback to the GF multiplier
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| 299 |
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end component;
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| 300 |
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| 301 |
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end structural;
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| 302 |
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| 303 |
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-- Now it is time to define each component and the way they work
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| 304 |
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| 305 |
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architecture Input1_2 of CRC_top is
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| 306 |
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| 307 |
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begin -- Input1_2
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| 308 |
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| 309 |
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port map (
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| 310 |
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reset => reset,
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| 311 |
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phi2 => phi2,
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| 312 |
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input1_2 => input,
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| 313 |
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output1_2 => input2_1);
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| 314 |
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| 315 |
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if reset='0' then output1_2 <= X'00000000'
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| 316 |
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elsif phi2='1' and phi2'event then output1_2 <= input1_2;
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| 317 |
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end if;
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| 318 |
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| 319 |
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end Input1_2;
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| 320 |
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| 321 |
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| 322 |
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architecture Input2_1 of CRC_top is
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| 323 |
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| 324 |
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begin -- Input2_1
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| 325 |
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| 326 |
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port map (
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| 327 |
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reset => reset,
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| 328 |
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phi1 => phi1,
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| 329 |
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input2_1 => output1_2,
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| 330 |
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output2_1 => input3_1);
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| 331 |
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| 332 |
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if reset='0' then output2_1 <= X'00000000'
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| 333 |
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elsif phi1='1' and phi1'event then output2_1 <= input2_1;
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| 334 |
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end if;
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| 335 |
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| 336 |
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end Input2_1;
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| 337 |
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| 338 |
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| 339 |
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architecture Input3_2 of CRC_top is
|
| 340 |
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| 341 |
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begin -- Input3_2
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| 342 |
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| 343 |
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port map (
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| 344 |
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reset => reset,
|
| 345 |
|
|
phi2 => phi2,
|
| 346 |
|
|
input3_2 => output2_1,
|
| 347 |
|
|
output3_2 => input4_1);
|
| 348 |
|
|
|
| 349 |
|
|
if reset='0' then output3_2 <= X'00000000'
|
| 350 |
|
|
elsif phi2='1' and phi2'event then output3_2 <= input3_2;
|
| 351 |
|
|
end if;
|
| 352 |
|
|
|
| 353 |
|
|
end Input3_2;
|
| 354 |
|
|
|
| 355 |
|
|
|
| 356 |
|
|
architecture Input4_1 of CRC_top is
|
| 357 |
|
|
|
| 358 |
|
|
begin -- Input4_1
|
| 359 |
|
|
|
| 360 |
|
|
port map (
|
| 361 |
|
|
reset => reset,
|
| 362 |
|
|
phi1 => phi1,
|
| 363 |
|
|
input4_1 => output3_2,
|
| 364 |
|
|
output4_1 => input5_2);
|
| 365 |
|
|
|
| 366 |
|
|
if reset='0' then output4_1 <= X'00000000'
|
| 367 |
|
|
elsif phi1='1' and phi1'event then output4_1 <= input4_1;
|
| 368 |
|
|
end if;
|
| 369 |
|
|
|
| 370 |
|
|
end Input4_1;
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
architecture Input5_2 of CRC_top is
|
| 374 |
|
|
|
| 375 |
|
|
begin -- Input5_2
|
| 376 |
|
|
|
| 377 |
|
|
port map (
|
| 378 |
|
|
reset => reset,
|
| 379 |
|
|
phi2 => phi2,
|
| 380 |
|
|
input5_2 => output4_1,
|
| 381 |
|
|
output5_2 => input6_1);
|
| 382 |
|
|
|
| 383 |
|
|
if reset='0' then output5_2 <= X'00000000'
|
| 384 |
|
|
elsif phi2='1' and phi2'event then output5_2 <= input5_2;
|
| 385 |
|
|
end if;
|
| 386 |
|
|
|
| 387 |
|
|
end Input5_2;
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
architecture Input6_1 of CRC_top is
|
| 391 |
|
|
|
| 392 |
|
|
begin -- Input6_1
|
| 393 |
|
|
|
| 394 |
|
|
port map (
|
| 395 |
|
|
reset => reset,
|
| 396 |
|
|
phi1 => phi1,
|
| 397 |
|
|
input6_1 => output5_2,
|
| 398 |
|
|
output6_1 => input7_2);
|
| 399 |
|
|
|
| 400 |
|
|
if reset='0' then output6_1 <= X'00000000'
|
| 401 |
|
|
elsif phi1='1' and phi1'event then output6_1 <= input6_1;
|
| 402 |
|
|
end if;
|
| 403 |
|
|
|
| 404 |
|
|
end Input6_1;
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
architecture Input7_2 of CRC_top is
|
| 408 |
|
|
|
| 409 |
|
|
begin -- Input7_2
|
| 410 |
|
|
|
| 411 |
|
|
port map (
|
| 412 |
|
|
reset => reset,
|
| 413 |
|
|
phi2 => phi2,
|
| 414 |
|
|
input7_2 => output6_1,
|
| 415 |
|
|
output7_2 => input8_1);
|
| 416 |
|
|
|
| 417 |
|
|
if reset='0' then output7_2 <= X'00000000'
|
| 418 |
|
|
elsif phi2='1' and phi2'event then output7_2 <= input7_2;
|
| 419 |
|
|
end if;
|
| 420 |
|
|
|
| 421 |
|
|
end Input7_2;
|
| 422 |
|
|
|
| 423 |
|
|
|
| 424 |
|
|
architecture Input8_1 of CRC_top is
|
| 425 |
|
|
|
| 426 |
|
|
begin -- Input8_1
|
| 427 |
|
|
|
| 428 |
|
|
port map (
|
| 429 |
|
|
reset => reset,
|
| 430 |
|
|
phi1 => phi1,
|
| 431 |
|
|
input8_1 => output7_2,
|
| 432 |
|
|
output8_1 => input9_2);
|
| 433 |
|
|
|
| 434 |
|
|
if reset='0' then output8_1 <= X'00000000'
|
| 435 |
|
|
elsif phi1='1' and phi1'event then output8_1 <= input8_1;
|
| 436 |
|
|
end if;
|
| 437 |
|
|
|
| 438 |
|
|
end Input8_1;
|
| 439 |
|
|
|
| 440 |
|
|
|
| 441 |
|
|
architecture Input9_2 of CRC_top is
|
| 442 |
|
|
|
| 443 |
|
|
begin -- Input9_2
|
| 444 |
|
|
|
| 445 |
|
|
port map (
|
| 446 |
|
|
reset => reset,
|
| 447 |
|
|
phi2 => phi2,
|
| 448 |
|
|
input9_2 => output8_1,
|
| 449 |
|
|
output9_2 => input10_1);
|
| 450 |
|
|
|
| 451 |
|
|
if reset='0' then output9_2 <= X'00000000'
|
| 452 |
|
|
elsif phi2='1' and phi2'event then output9_2 <= input9_2;
|
| 453 |
|
|
end if;
|
| 454 |
|
|
|
| 455 |
|
|
end Input9_2;
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
architecture Input10_1 of CRC_top is
|
| 459 |
|
|
|
| 460 |
|
|
begin -- Input10_1
|
| 461 |
|
|
|
| 462 |
|
|
port map (
|
| 463 |
|
|
reset => reset,
|
| 464 |
|
|
phi1 => phi1,
|
| 465 |
|
|
input10_1 => output9_2,
|
| 466 |
|
|
output10_1 => input11_2);
|
| 467 |
|
|
|
| 468 |
|
|
if reset='0' then output10_1 <= X'00000000'
|
| 469 |
|
|
elsif phi1='1' and phi1'event then output10_1 <= input10_1;
|
| 470 |
|
|
end if;
|
| 471 |
|
|
|
| 472 |
|
|
end Input10_1;
|
| 473 |
|
|
|
| 474 |
|
|
|
| 475 |
|
|
architecture Input11_2 of CRC_top is
|
| 476 |
|
|
|
| 477 |
|
|
begin -- Input11_2
|
| 478 |
|
|
|
| 479 |
|
|
port map (
|
| 480 |
|
|
reset => reset,
|
| 481 |
|
|
phi2 => phi2,
|
| 482 |
|
|
input11_2 => output10_1,
|
| 483 |
|
|
output11_2 => input12_1);
|
| 484 |
|
|
|
| 485 |
|
|
if reset='0' then output11_2 <= X'00000000'
|
| 486 |
|
|
elsif phi2='1' and phi2'event then output11_2 <= input11_2;
|
| 487 |
|
|
end if;
|
| 488 |
|
|
|
| 489 |
|
|
end Input11_2;
|
| 490 |
|
|
|
| 491 |
|
|
|
| 492 |
|
|
architecture Input12_1 of CRC_top is
|
| 493 |
|
|
|
| 494 |
|
|
begin -- Input12_1
|
| 495 |
|
|
|
| 496 |
|
|
port map (
|
| 497 |
|
|
reset => reset,
|
| 498 |
|
|
phi1 => phi1,
|
| 499 |
|
|
input12_1 => output11_2,
|
| 500 |
|
|
output12_1 => input_bigx_1); -- Big "final" XOR
|
| 501 |
|
|
|
| 502 |
|
|
if reset='0' then output12_1 <= X'00000000'
|
| 503 |
|
|
elsif phi1='1' and phi1'event then output12_1 <= input12_1;
|
| 504 |
|
|
end if;
|
| 505 |
|
|
|
| 506 |
|
|
end Input2_1;
|
| 507 |
|
|
|
| 508 |
|
|
-- Galois Field multiplier
|
| 509 |
|
|
|
| 510 |
|
|
architecture GF1_xor_2 of CRC_top is
|
| 511 |
|
|
|
| 512 |
|
|
begin -- GF1_xor_2
|
| 513 |
|
|
|
| 514 |
|
|
port map (
|
| 515 |
|
|
input_gf1x_2 => fcs_out13_2,
|
| 516 |
|
|
output_gf1x_2 => input_gf2_1 (31 downto 0));
|
| 517 |
|
|
|
| 518 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 519 |
|
|
-- the 32 bits of the fcs
|
| 520 |
|
|
|
| 521 |
|
|
output_gf1x_2 (31 => (input_gf1x_2(9) xor input_gf1x_2(15)),
|
| 522 |
|
|
30 => (input_gf1x_2(8) xor input_gf1x_2(9)),
|
| 523 |
|
|
29 => (input_gf1x_2(7) xor input_gf1x_2(8)),
|
| 524 |
|
|
28 => (input_gf1x_2(6) xor input_gf1x_2(7)),
|
| 525 |
|
|
27 => (input_gf1x_2(5) xor input_gf1x_2(6)),
|
| 526 |
|
|
26 => (input_gf1x_2(4) xor input_gf1x_2(5)),
|
| 527 |
|
|
25 => (input_gf1x_2(3) xor input_gf1x_2(4)),
|
| 528 |
|
|
24 => (input_gf1x_2(2) xor input_gf1x_2(3)),
|
| 529 |
|
|
23 => (input_gf1x_2(1) xor input_gf1x_2(1)),
|
| 530 |
|
|
22 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 531 |
|
|
21 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 532 |
|
|
20 => (input_gf1x_2(0) xor input_gf1x_2(2)),
|
| 533 |
|
|
19 => (input_gf1x_2(1) xor input_gf1x_2(2)),
|
| 534 |
|
|
18 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 535 |
|
|
17 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 536 |
|
|
16 => (input_gf1x_2(0) xor input_gf1x_2(6)),
|
| 537 |
|
|
15 => (input_gf1x_2(5) xor input_gf1x_2(6)),
|
| 538 |
|
|
14 => (input_gf1x_2(4) xor input_gf1x_2(5)),
|
| 539 |
|
|
13 => (input_gf1x_2(3) xor input_gf1x_2(4)),
|
| 540 |
|
|
12 => (input_gf1x_2(2) xor input_gf1x_2(3)),
|
| 541 |
|
|
11 => (input_gf1x_2(1) xor input_gf1x_2(2)),
|
| 542 |
|
|
10 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 543 |
|
|
9 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 544 |
|
|
8 => (input_gf1x_2(0) xor input_gf1x_2(3)),
|
| 545 |
|
|
7 => (input_gf1x_2(2) xor input_gf1x_2(3)),
|
| 546 |
|
|
6 => (input_gf1x_2(1) xor input_gf1x_2(2)),
|
| 547 |
|
|
5 => (input_gf1x_2(0) xor input_gf1x_2(1)),
|
| 548 |
|
|
4 => (input_gf1x_2(0) xor input_gf1x_2(5)),
|
| 549 |
|
|
3 => (input_gf1x_2(4) xor input_gf1x_2(7)),
|
| 550 |
|
|
2 => (input_gf1x_2(3) xor input_gf1x_2(6)),
|
| 551 |
|
|
1 => (input_gf1x_2(2) xor input_gf1x_2(5)),
|
| 552 |
|
|
|
| 553 |
|
|
|
| 554 |
|
|
|
| 555 |
|
|
end GF1_xor_2;
|
| 556 |
|
|
|
| 557 |
|
|
architecture GF2_1 of CRC_top is
|
| 558 |
|
|
|
| 559 |
|
|
begin -- GF2_1
|
| 560 |
|
|
|
| 561 |
|
|
port map (
|
| 562 |
|
|
reset => reset,
|
| 563 |
|
|
phi1 => phi1,
|
| 564 |
|
|
input_gf2_1 (63 downto 32) => fcs_13_2,
|
| 565 |
|
|
input_gf2_1 (31 downto 0) => output_gf1x_2,
|
| 566 |
|
|
output_gf2_1 (63 downto 32) => input_gf3_2,
|
| 567 |
|
|
output_gf2_1 (31 downto 0) => input_gf2x_1);
|
| 568 |
|
|
|
| 569 |
|
|
if reset='0' then output_gf2_1 <= X'0000000000000000'
|
| 570 |
|
|
elsif phi1='1' and phi1'event then output_gf2_1 <= input_gf2_1;
|
| 571 |
|
|
end if;
|
| 572 |
|
|
|
| 573 |
|
|
end GF2_1;
|
| 574 |
|
|
|
| 575 |
|
|
|
| 576 |
|
|
architecture GF2_xor_1 of CRC_top is
|
| 577 |
|
|
|
| 578 |
|
|
begin -- GF2_xor_1
|
| 579 |
|
|
|
| 580 |
|
|
port map (
|
| 581 |
|
|
input_gf2x_1 => output_gf2_1 (31 downto 0),
|
| 582 |
|
|
output_gf2x_1 => input_gf3_2 (31 downto 0));
|
| 583 |
|
|
|
| 584 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 585 |
|
|
-- the 32 bits of the fcs
|
| 586 |
|
|
|
| 587 |
|
|
output_gf2x_1 (31 => input_gf2x_1(31),
|
| 588 |
|
|
30 => (input_gf2x_1(30) xor output_gf2_1(14+32)),
|
| 589 |
|
|
29 => (input_gf2x_1(29) xor output_gf2_1(9+32)),
|
| 590 |
|
|
28 => (input_gf2x_1(28) xor output_gf2_1(8+32)),
|
| 591 |
|
|
27 => (input_gf2x_1(27) xor output_gf2_1(7+32)),
|
| 592 |
|
|
26 => (input_gf2x_1(26) xor output_gf2_1(6+32)),
|
| 593 |
|
|
25 => (input_gf2x_1(25) xor output_gf2_1(5+32)),
|
| 594 |
|
|
24 => (input_gf2x_1(24) xor output_gf2_1(4+32)),
|
| 595 |
|
|
23 => (input_gf2x_1(23) xor output_gf2_1(3+32)),
|
| 596 |
|
|
22 => (input_gf2x_1(22) xor output_gf2_1(2+32)),
|
| 597 |
|
|
21 => (input_gf2x_1(21) xor output_gf2_1(3+32)),
|
| 598 |
|
|
20 => (input_gf2x_1(20) xor output_gf2_1(3+32)),
|
| 599 |
|
|
19 => (input_gf2x_1(19) xor output_gf2_1(3+32)),
|
| 600 |
|
|
18 => (input_gf2x_1(18) xor output_gf2_1(2+32)),
|
| 601 |
|
|
17 => (input_gf2x_1(17) xor output_gf2_1(7+32)),
|
| 602 |
|
|
16 => (input_gf2x_1(16) xor output_gf2_1(7+32)),
|
| 603 |
|
|
15 => (input_gf2x_1(15) xor output_gf2_1(7+32)),
|
| 604 |
|
|
14 => (input_gf2x_1(14) xor output_gf2_1(6+32)),
|
| 605 |
|
|
13 => (input_gf2x_1(13) xor output_gf2_1(5+32)),
|
| 606 |
|
|
12 => (input_gf2x_1(12) xor output_gf2_1(4+32)),
|
| 607 |
|
|
11 => (input_gf2x_1(11) xor output_gf2_1(3+32)),
|
| 608 |
|
|
10 => (input_gf2x_1(10) xor output_gf2_1(2+32)),
|
| 609 |
|
|
9 => (input_gf2x_1(9) xor output_gf2_1(4+32)),
|
| 610 |
|
|
8 => (input_gf2x_1(8) xor output_gf2_1(4+32)),
|
| 611 |
|
|
7 => (input_gf2x_1(7) xor output_gf2_1(8+32)),
|
| 612 |
|
|
6 => (input_gf2x_1(6) xor output_gf2_1(7+32)),
|
| 613 |
|
|
5 => (input_gf2x_1(5) xor output_gf2_1(6+32)),
|
| 614 |
|
|
4 => (input_gf2x_1(4) xor output_gf2_1(8+32)),
|
| 615 |
|
|
3 => (input_gf2x_1(3) xor output_gf2_1(9+32)),
|
| 616 |
|
|
2 => (input_gf2x_1(2) xor output_gf2_1(8+32)),
|
| 617 |
|
|
1 => (input_gf2x_1(1) xor output_gf2_1(7+32)),
|
| 618 |
|
|
|
| 619 |
|
|
|
| 620 |
|
|
|
| 621 |
|
|
end GF2_xor_1;
|
| 622 |
|
|
|
| 623 |
|
|
architecture GF3_2 of CRC_top is
|
| 624 |
|
|
|
| 625 |
|
|
begin -- GF3_2
|
| 626 |
|
|
|
| 627 |
|
|
port map (
|
| 628 |
|
|
reset => reset,
|
| 629 |
|
|
phi2 => phi2,
|
| 630 |
|
|
input_gf3_2 (63 downto 32) => output_gf2_1 (63 downto 32),
|
| 631 |
|
|
input_gf3_2 (31 downto 0) => output_gf2x_1,
|
| 632 |
|
|
output_gf3_2 (63 downto 32) => input_gf4_1,
|
| 633 |
|
|
output_gf3_2 (31 downto 0) => input_gf3x_2);
|
| 634 |
|
|
|
| 635 |
|
|
if reset='0' then output_gf3_2 <= X'0000000000000000'
|
| 636 |
|
|
elsif phi2='1' and phi2'event then output_gf3_2 <= input_gf3_2;
|
| 637 |
|
|
end if;
|
| 638 |
|
|
|
| 639 |
|
|
end GF3_2;
|
| 640 |
|
|
|
| 641 |
|
|
|
| 642 |
|
|
architecture GF3_xor_2 of CRC_top is
|
| 643 |
|
|
|
| 644 |
|
|
begin -- GF3_xor_2
|
| 645 |
|
|
|
| 646 |
|
|
port map (
|
| 647 |
|
|
input_gf3x_2 => output_gf3_2 (31 downto 0),
|
| 648 |
|
|
output_gf3x_2 => input_gf4_1 (31 downto 0));
|
| 649 |
|
|
|
| 650 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 651 |
|
|
-- the 32 bits of the fcs
|
| 652 |
|
|
|
| 653 |
|
|
output_gf3x_2 (31 => input_gf3x_1(31),
|
| 654 |
|
|
30 => (input_gf3x_1(30) xor output_gf3_2(15+32)),
|
| 655 |
|
|
29 => (input_gf3x_1(29) xor output_gf3_2(13+32)),
|
| 656 |
|
|
28 => (input_gf3x_1(28) xor output_gf3_2(12+32)),
|
| 657 |
|
|
27 => (input_gf3x_1(27) xor output_gf3_2(9+32)),
|
| 658 |
|
|
26 => (input_gf3x_1(26) xor output_gf3_2(8+32)),
|
| 659 |
|
|
25 => (input_gf3x_1(25) xor output_gf3_2(7+32)),
|
| 660 |
|
|
24 => (input_gf3x_1(24) xor output_gf3_2(6+32)),
|
| 661 |
|
|
23 => (input_gf3x_1(23) xor output_gf3_2(5+32)),
|
| 662 |
|
|
22 => (input_gf3x_1(22) xor output_gf3_2(4+32)),
|
| 663 |
|
|
21 => (input_gf3x_1(21) xor output_gf3_2(4+32)),
|
| 664 |
|
|
20 => (input_gf3x_1(20) xor output_gf3_2(4+32)),
|
| 665 |
|
|
19 => (input_gf3x_1(19) xor output_gf3_2(9+32)),
|
| 666 |
|
|
18 => (input_gf3x_1(18) xor output_gf3_2(8+32)),
|
| 667 |
|
|
17 => (input_gf3x_1(17) xor output_gf3_2(8+32)),
|
| 668 |
|
|
16 => (input_gf3x_1(16) xor output_gf3_2(8+32)),
|
| 669 |
|
|
15 => (input_gf3x_1(15) xor output_gf3_2(10+32)),
|
| 670 |
|
|
14 => (input_gf3x_1(14) xor output_gf3_2(9+32)),
|
| 671 |
|
|
13 => (input_gf3x_1(13) xor output_gf3_2(8+32)),
|
| 672 |
|
|
12 => (input_gf3x_1(12) xor output_gf3_2(7+32)),
|
| 673 |
|
|
11 => (input_gf3x_1(11) xor output_gf3_2(6+32)),
|
| 674 |
|
|
10 => (input_gf3x_1(10) xor output_gf3_2(5+32)),
|
| 675 |
|
|
9 => (input_gf3x_1(9) xor output_gf3_2(5+32)),
|
| 676 |
|
|
8 => (input_gf3x_1(8) xor output_gf3_2(9+32)),
|
| 677 |
|
|
7 => (input_gf3x_1(7) xor output_gf3_2(13+32)),
|
| 678 |
|
|
6 => (input_gf3x_1(6) xor output_gf3_2(12+32)),
|
| 679 |
|
|
5 => (input_gf3x_1(5) xor output_gf3_2(9+32)),
|
| 680 |
|
|
4 => (input_gf3x_1(4) xor output_gf3_2(10+32)),
|
| 681 |
|
|
3 => (input_gf3x_1(3) xor output_gf3_2(10+32)),
|
| 682 |
|
|
2 => (input_gf3x_1(2) xor output_gf3_2(9+32)),
|
| 683 |
|
|
1 => (input_gf3x_1(1) xor output_gf3_2(8+32)),
|
| 684 |
|
|
|
| 685 |
|
|
|
| 686 |
|
|
|
| 687 |
|
|
end GF3_xor_2;
|
| 688 |
|
|
|
| 689 |
|
|
architecture GF4_1 of CRC_top is
|
| 690 |
|
|
|
| 691 |
|
|
begin -- GF4_1
|
| 692 |
|
|
|
| 693 |
|
|
port map (
|
| 694 |
|
|
reset => reset,
|
| 695 |
|
|
phi1 => phi1,
|
| 696 |
|
|
input_gf4_1 (63 downto 32) => output_gf3_2 (63 downto 32),
|
| 697 |
|
|
input_gf4_1 (31 downto 0) => output_gf3x_2,
|
| 698 |
|
|
output_gf4_1 (63 downto 32) => input_gf5_2,
|
| 699 |
|
|
output_gf4_1 (31 downto 0) => input_gf4x_1);
|
| 700 |
|
|
|
| 701 |
|
|
if reset='0' then output_gf4_1 <= X'0000000000000000'
|
| 702 |
|
|
elsif phi1='1' and phi1'event then output_gf4_1 <= input_gf4_1;
|
| 703 |
|
|
end if;
|
| 704 |
|
|
|
| 705 |
|
|
end GF4_1;
|
| 706 |
|
|
|
| 707 |
|
|
|
| 708 |
|
|
architecture GF4_xor_1 of CRC_top is
|
| 709 |
|
|
|
| 710 |
|
|
begin -- GF4_xor_1
|
| 711 |
|
|
|
| 712 |
|
|
port map (
|
| 713 |
|
|
input_gf4x_1 => output_gf4_1 (31 downto 0),
|
| 714 |
|
|
output_gf4x_1 => input_gf5_2 (31 downto 0));
|
| 715 |
|
|
|
| 716 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 717 |
|
|
-- the 32 bits of the fcs
|
| 718 |
|
|
|
| 719 |
|
|
output_gfx4_1 (31 => input_gf4x_1(31),
|
| 720 |
|
|
30 => input_gf4x_1(30),
|
| 721 |
|
|
29 => (input_gf4x_1(29) xor output_gf4_1(14+32)),
|
| 722 |
|
|
28 => (input_gf4x_1(28) xor output_gf4_1(13+32)),
|
| 723 |
|
|
27 => (input_gf4x_1(27) xor output_gf4_1(11+32)),
|
| 724 |
|
|
26 => (input_gf4x_1(26) xor output_gf4_1(9+32)),
|
| 725 |
|
|
25 => (input_gf4x_1(25) xor output_gf4_1(8+32)),
|
| 726 |
|
|
24 => (input_gf4x_1(24) xor output_gf4_1(7+32)),
|
| 727 |
|
|
23 => (input_gf4x_1(23) xor output_gf4_1(6+32)),
|
| 728 |
|
|
22 => (input_gf4x_1(22) xor output_gf4_1(5+32)),
|
| 729 |
|
|
21 => (input_gf4x_1(21) xor output_gf4_1(5+32)),
|
| 730 |
|
|
20 => (input_gf4x_1(20) xor output_gf4_1(11+32)),
|
| 731 |
|
|
19 => (input_gf4x_1(19) xor output_gf4_1(10+32)),
|
| 732 |
|
|
18 => (input_gf4x_1(18) xor output_gf4_1(9+32)),
|
| 733 |
|
|
17 => (input_gf4x_1(17) xor output_gf4_1(9+32)),
|
| 734 |
|
|
16 => (input_gf4x_1(16) xor output_gf4_1(10+32)),
|
| 735 |
|
|
15 => (input_gf4x_1(15) xor output_gf4_1(11+32)),
|
| 736 |
|
|
14 => (input_gf4x_1(14) xor output_gf4_1(10+32)),
|
| 737 |
|
|
13 => (input_gf4x_1(13) xor output_gf4_1(9+32)),
|
| 738 |
|
|
12 => (input_gf4x_1(12) xor output_gf4_1(8+32)),
|
| 739 |
|
|
11 => (input_gf4x_1(11) xor output_gf4_1(7+32)),
|
| 740 |
|
|
10 => (input_gf4x_1(10) xor output_gf4_1(6+32)),
|
| 741 |
|
|
9 => (input_gf4x_1(9) xor output_gf4_1(15+32)),
|
| 742 |
|
|
8 => (input_gf4x_1(8) xor output_gf4_1(14+32)),
|
| 743 |
|
|
7 => (input_gf4x_1(7) xor output_gf4_1(14+32)),
|
| 744 |
|
|
6 => (input_gf4x_1(6) xor output_gf4_1(13+32)),
|
| 745 |
|
|
5 => (input_gf4x_1(5) xor output_gf4_1(11+32)),
|
| 746 |
|
|
4 => (input_gf4x_1(4) xor output_gf4_1(11+32)),
|
| 747 |
|
|
3 => (input_gf4x_1(3) xor output_gf4_1(13+32)),
|
| 748 |
|
|
2 => (input_gf4x_1(2) xor output_gf4_1(12+32)),
|
| 749 |
|
|
1 => (input_gf4x_1(1) xor output_gf4_1(11+32)),
|
| 750 |
|
|
|
| 751 |
|
|
|
| 752 |
|
|
|
| 753 |
|
|
end GF4_xor_1;
|
| 754 |
|
|
|
| 755 |
|
|
architecture GF5_2 of CRC_top is
|
| 756 |
|
|
|
| 757 |
|
|
begin -- GF5_2
|
| 758 |
|
|
|
| 759 |
|
|
port map (
|
| 760 |
|
|
reset => reset,
|
| 761 |
|
|
phi2 => phi2,
|
| 762 |
|
|
input_gf5_2 (63 downto 32) => output_gf4_1 (63 downto 32),
|
| 763 |
|
|
input_gf5_2 (31 downto 0) => output_gf4x_1,
|
| 764 |
|
|
output_gf5_2 (63 downto 32) => input_gf6_1 (63 downto 32),
|
| 765 |
|
|
output_gf5_2 (31 downto 0) => input_gf5x_2);
|
| 766 |
|
|
|
| 767 |
|
|
if reset='0' then output_gf5_2 <= X'0000000000000000'
|
| 768 |
|
|
elsif phi2='1' and phi2'event then output_gf5_2 <= input_gf5_2;
|
| 769 |
|
|
end if;
|
| 770 |
|
|
|
| 771 |
|
|
end GF5_2;
|
| 772 |
|
|
|
| 773 |
|
|
|
| 774 |
|
|
architecture GF5_xor_2 of CRC_top is
|
| 775 |
|
|
|
| 776 |
|
|
begin -- GF5_xor_2
|
| 777 |
|
|
|
| 778 |
|
|
port map (
|
| 779 |
|
|
input_gf5x_2 => output_gf5_2 (31 downto 0),
|
| 780 |
|
|
output_gf5x_2 => input_gf6_1 (31 downto 0));
|
| 781 |
|
|
|
| 782 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 783 |
|
|
-- the 32 bits of the fcs
|
| 784 |
|
|
|
| 785 |
|
|
output_gf5x_2 (31 => input_gf5x_2(31),
|
| 786 |
|
|
30 => input_gf5x_2(30),
|
| 787 |
|
|
29 => (input_gf5x_2(29) xor output_gf5_2(15+32)),
|
| 788 |
|
|
28 => (input_gf5x_2(28) xor output_gf5_2(14+32)),
|
| 789 |
|
|
27 => (input_gf5x_2(27) xor output_gf5_2(12+32)),
|
| 790 |
|
|
26 => (input_gf5x_2(26) xor output_gf5_2(10+32)),
|
| 791 |
|
|
25 => (input_gf5x_2(25) xor output_gf5_2(9+32)),
|
| 792 |
|
|
24 => (input_gf5x_2(24) xor output_gf5_2(8+32)),
|
| 793 |
|
|
23 => (input_gf5x_2(23) xor output_gf5_2(7+32)),
|
| 794 |
|
|
22 => (input_gf5x_2(22) xor output_gf5_2(6+32)),
|
| 795 |
|
|
21 => (input_gf5x_2(21) xor output_gf5_2(10+32)),
|
| 796 |
|
|
20 => (input_gf5x_2(20) xor output_gf5_2(12+32)),
|
| 797 |
|
|
19 => (input_gf5x_2(19) xor output_gf5_2(11+32)),
|
| 798 |
|
|
18 => (input_gf5x_2(18) xor output_gf5_2(10+32)),
|
| 799 |
|
|
17 => (input_gf5x_2(17) xor output_gf5_2(11+32)),
|
| 800 |
|
|
16 => (input_gf5x_2(16) xor output_gf5_2(11+32)),
|
| 801 |
|
|
15 => (input_gf5x_2(15) xor output_gf5_2(15+32)),
|
| 802 |
|
|
14 => (input_gf5x_2(14) xor output_gf5_2(14+32)),
|
| 803 |
|
|
13 => (input_gf5x_2(13) xor output_gf5_2(13+32)),
|
| 804 |
|
|
12 => (input_gf5x_2(12) xor output_gf5_2(12+32)),
|
| 805 |
|
|
11 => (input_gf5x_2(11) xor output_gf5_2(11+32)),
|
| 806 |
|
|
10 => (input_gf5x_2(10) xor output_gf5_2(10+32)),
|
| 807 |
|
|
9 => (input_gf5x_2(9) xor output_gf5_2(25+32)),
|
| 808 |
|
|
8 => (input_gf5x_2(8) xor output_gf5_2(15+32)),
|
| 809 |
|
|
7 => (input_gf5x_2(7) xor output_gf5_2(23+32)),
|
| 810 |
|
|
6 => (input_gf5x_2(6) xor output_gf5_2(22+32)),
|
| 811 |
|
|
5 => (input_gf5x_2(5) xor output_gf5_2(12+32)),
|
| 812 |
|
|
4 => (input_gf5x_2(4) xor output_gf5_2(14+32)),
|
| 813 |
|
|
3 => (input_gf5x_2(3) xor output_gf5_2(19+32)),
|
| 814 |
|
|
2 => (input_gf5x_2(2) xor output_gf5_2(18+32)),
|
| 815 |
|
|
1 => (input_gf5x_2(1) xor output_gf5_2(17+32)),
|
| 816 |
|
|
|
| 817 |
|
|
|
| 818 |
|
|
|
| 819 |
|
|
end GF5_xor_2;
|
| 820 |
|
|
|
| 821 |
|
|
architecture GF6_1 of CRC_top is
|
| 822 |
|
|
|
| 823 |
|
|
begin -- GF6_1
|
| 824 |
|
|
|
| 825 |
|
|
port map (
|
| 826 |
|
|
reset => reset,
|
| 827 |
|
|
phi1 => phi1,
|
| 828 |
|
|
input_gf6_1 (63 downto 32) => output_gf5_2 (63 downto 32),
|
| 829 |
|
|
input_gf6_1 (31 downto 0) => output_gf5x_2,
|
| 830 |
|
|
output_gf6_1 (63 downto 32) => input_gf7_2 (63 downto 32),
|
| 831 |
|
|
output_gf6_1 (31 downto 0) => input_gf6x_1);
|
| 832 |
|
|
|
| 833 |
|
|
if reset='0' then output_gf6_1 <= X'0000000000000000'
|
| 834 |
|
|
elsif phi1='1' and phi1'event then output_gf6_1 <= input_gf6_1;
|
| 835 |
|
|
end if;
|
| 836 |
|
|
|
| 837 |
|
|
end GF6_1;
|
| 838 |
|
|
|
| 839 |
|
|
|
| 840 |
|
|
architecture GF6_xor_1 of CRC_top is
|
| 841 |
|
|
|
| 842 |
|
|
begin -- GF5_xor_1
|
| 843 |
|
|
|
| 844 |
|
|
port map (
|
| 845 |
|
|
input_gf6x_1 => output_gf6_1 (31 downto 0),
|
| 846 |
|
|
output_gf6x_1 => input_gf7_2 (31 downto 0));
|
| 847 |
|
|
|
| 848 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 849 |
|
|
-- the 32 bits of the fcs
|
| 850 |
|
|
|
| 851 |
|
|
output_gf6x_1 (31 => input_gf6x_1(31),
|
| 852 |
|
|
30 => input_gf6x_1(30),
|
| 853 |
|
|
29 => input_gf6x_1(29),
|
| 854 |
|
|
28 => input_gf6x_1(28),
|
| 855 |
|
|
27 => (input_gf6x_1(27) xor output_gf6_1(13+32)),
|
| 856 |
|
|
26 => (input_gf6x_1(26) xor output_gf6_1(11+32)),
|
| 857 |
|
|
25 => (input_gf6x_1(25) xor output_gf6_1(10+32)),
|
| 858 |
|
|
24 => (input_gf6x_1(24) xor output_gf6_1(10+32)),
|
| 859 |
|
|
23 => (input_gf6x_1(23) xor output_gf6_1(11+32)),
|
| 860 |
|
|
22 => (input_gf6x_1(22) xor output_gf6_1(10+32)),
|
| 861 |
|
|
21 => (input_gf6x_1(21) xor output_gf6_1(12+32)),
|
| 862 |
|
|
20 => (input_gf6x_1(20) xor output_gf6_1(14+32)),
|
| 863 |
|
|
19 => (input_gf6x_1(19) xor output_gf6_1(13+32)),
|
| 864 |
|
|
18 => (input_gf6x_1(18) xor output_gf6_1(12+32)),
|
| 865 |
|
|
17 => (input_gf6x_1(17) xor output_gf6_1(12+32)),
|
| 866 |
|
|
16 => (input_gf6x_1(16) xor output_gf6_1(12+32)),
|
| 867 |
|
|
15 => (input_gf6x_1(15) xor output_gf6_1(31+32)),
|
| 868 |
|
|
14 => (input_gf6x_1(14) xor output_gf6_1(30+32)),
|
| 869 |
|
|
13 => (input_gf6x_1(13) xor output_gf6_1(29+32)),
|
| 870 |
|
|
12 => (input_gf6x_1(12) xor output_gf6_1(28+32)),
|
| 871 |
|
|
11 => (input_gf6x_1(11) xor output_gf6_1(27+32)),
|
| 872 |
|
|
10 => (input_gf6x_1(10) xor output_gf6_1(26+32)),
|
| 873 |
|
|
9 => (input_gf6x_1(9) xor '0'),
|
| 874 |
|
|
8 => (input_gf6x_1(8) xor output_gf6_1(24+32)),
|
| 875 |
|
|
7 => (input_gf6x_1(7) xor '0'),
|
| 876 |
|
|
6 => (input_gf6x_1(6) xor '0'),
|
| 877 |
|
|
5 => (input_gf6x_1(5) xor output_gf6_1(15+32)),
|
| 878 |
|
|
4 => (input_gf6x_1(4) xor output_gf6_1(20+32)),
|
| 879 |
|
|
3 => (input_gf6x_1(3) xor '0'),
|
| 880 |
|
|
2 => (input_gf6x_1(2) xor '0'),
|
| 881 |
|
|
1 => (input_gf6x_1(1) xor '0'),
|
| 882 |
|
|
|
| 883 |
|
|
|
| 884 |
|
|
|
| 885 |
|
|
end GF6_xor_1;
|
| 886 |
|
|
|
| 887 |
|
|
architecture GF7_2 of CRC_top is
|
| 888 |
|
|
|
| 889 |
|
|
begin -- GF7_2
|
| 890 |
|
|
|
| 891 |
|
|
port map (
|
| 892 |
|
|
reset => reset,
|
| 893 |
|
|
phi2 => phi2,
|
| 894 |
|
|
input_gf7_2 (63 downto 32) => output_gf6_1 (63 downto 32),
|
| 895 |
|
|
input_gf7_2 (31 downto 0) => output_gf6x_1,
|
| 896 |
|
|
output_gf7_2 (63 downto 32) => input_gf8_1 (63 downto 32),
|
| 897 |
|
|
output_gf7_2 (31 downto 0) => input_gf7x_2);
|
| 898 |
|
|
|
| 899 |
|
|
if reset='0' then output_gf7_2 <= X'0000000000000000'
|
| 900 |
|
|
elsif phi2='1' and phi2'event then output_gf7_2 <= input_gf7_2;
|
| 901 |
|
|
end if;
|
| 902 |
|
|
|
| 903 |
|
|
end GF7_2;
|
| 904 |
|
|
|
| 905 |
|
|
|
| 906 |
|
|
architecture GF7_xor_2 of CRC_top is
|
| 907 |
|
|
|
| 908 |
|
|
begin -- GF7_xor_2
|
| 909 |
|
|
|
| 910 |
|
|
port map (
|
| 911 |
|
|
input_gf7x_2 => output_gf7_2 (31 downto 0),
|
| 912 |
|
|
output_gf7x_2 => input_gf8_1 (31 downto 0));
|
| 913 |
|
|
|
| 914 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 915 |
|
|
-- the 32 bits of the fcs
|
| 916 |
|
|
|
| 917 |
|
|
output_gf7x_2 (31 => input_gf7x_2(31),
|
| 918 |
|
|
30 => input_gf7x_2(30),
|
| 919 |
|
|
29 => input_gf7x_2(29),
|
| 920 |
|
|
28 => input_gf7x_2(28),
|
| 921 |
|
|
27 => (input_gf7x_2(27) xor output_gf7_2(15+32)),
|
| 922 |
|
|
26 => (input_gf7x_2(26) xor output_gf7_2(12+32)),
|
| 923 |
|
|
25 => (input_gf7x_2(25) xor output_gf7_2(11+32)),
|
| 924 |
|
|
24 => (input_gf7x_2(24) xor output_gf7_2(12+32)),
|
| 925 |
|
|
23 => (input_gf7x_2(23) xor output_gf7_2(12+32)),
|
| 926 |
|
|
22 => (input_gf7x_2(22) xor output_gf7_2(11+32)),
|
| 927 |
|
|
21 => (input_gf7x_2(21) xor output_gf7_2(13+32)),
|
| 928 |
|
|
20 => (input_gf7x_2(20) xor output_gf7_2(15+32)),
|
| 929 |
|
|
19 => (input_gf7x_2(19) xor output_gf7_2(14+32)),
|
| 930 |
|
|
18 => (input_gf7x_2(18) xor output_gf7_2(13+32)),
|
| 931 |
|
|
17 => (input_gf7x_2(17) xor output_gf7_2(13+32)),
|
| 932 |
|
|
16 => (input_gf7x_2(16) xor '0'),
|
| 933 |
|
|
15 => (input_gf7x_2(15) xor '0'),
|
| 934 |
|
|
14 => (input_gf7x_2(14) xor '0'),
|
| 935 |
|
|
13 => (input_gf7x_2(13) xor '0'),
|
| 936 |
|
|
12 => (input_gf7x_2(12) xor '0'),
|
| 937 |
|
|
11 => (input_gf7x_2(11) xor '0'),
|
| 938 |
|
|
10 => (input_gf7x_2(10) xor '0'),
|
| 939 |
|
|
9 => input_gf7x_2(9),
|
| 940 |
|
|
8 => (input_gf7x_2(8) xor '0'),
|
| 941 |
|
|
7 => input_gf7x_2(7),
|
| 942 |
|
|
6 => input_gf7x_2(6),
|
| 943 |
|
|
5 => (input_gf7x_2(5) xor '0'),
|
| 944 |
|
|
4 => (input_gf7x_2(4) xor '0'),
|
| 945 |
|
|
3 => input_gf7x_2(3),
|
| 946 |
|
|
2 => input_gf7x_2(2),
|
| 947 |
|
|
1 => input_gf7x_2(1),
|
| 948 |
|
|
|
| 949 |
|
|
|
| 950 |
|
|
|
| 951 |
|
|
end GF7_xor_2;
|
| 952 |
|
|
|
| 953 |
|
|
architecture GF8_1 of CRC_top is
|
| 954 |
|
|
|
| 955 |
|
|
begin -- GF8_1
|
| 956 |
|
|
|
| 957 |
|
|
port map (
|
| 958 |
|
|
reset => reset,
|
| 959 |
|
|
phi1 => phi1,
|
| 960 |
|
|
input_gf8_1 (63 downto 32) => output_gf7_2 (63 downto 32),
|
| 961 |
|
|
input_gf8_1 (31 downto 0) => output_gf7x_2,
|
| 962 |
|
|
output_gf8_1 (63 downto 32) => input_gf9_2 (63 downto 32),
|
| 963 |
|
|
output_gf8_1 (31 downto 0) => input_gf8x_1);
|
| 964 |
|
|
|
| 965 |
|
|
if reset='0' then output_gf8_1 <= X'0000000000000000'
|
| 966 |
|
|
elsif phi1='1' and phi1'event then output_gf8_1 <= input_gf8_1;
|
| 967 |
|
|
end if;
|
| 968 |
|
|
|
| 969 |
|
|
end GF8_1;
|
| 970 |
|
|
|
| 971 |
|
|
|
| 972 |
|
|
architecture GF8_xor_1 of CRC_top is
|
| 973 |
|
|
|
| 974 |
|
|
begin -- GF8_xor_1
|
| 975 |
|
|
|
| 976 |
|
|
port map (
|
| 977 |
|
|
input_gf8x_1 => output_gf8_1 (31 downto 0),
|
| 978 |
|
|
output_gf8x_1 => input_gf9_2 (31 downto 0));
|
| 979 |
|
|
|
| 980 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 981 |
|
|
-- the 32 bits of the fcs
|
| 982 |
|
|
|
| 983 |
|
|
output_gf8x_1 (31 => input_gf8x_1(31),
|
| 984 |
|
|
30 => input_gf8x_1(30),
|
| 985 |
|
|
29 => input_gf8x_1(29),
|
| 986 |
|
|
28 => input_gf8x_1(28),
|
| 987 |
|
|
27 => input_gf8x_1(27),
|
| 988 |
|
|
26 => (input_gf8x_1(26) xor output_gf8_1(14+32)),
|
| 989 |
|
|
25 => (input_gf8x_1(25) xor output_gf8_1(13+32)),
|
| 990 |
|
|
24 => (input_gf8x_1(24) xor output_gf8_1(13+32)),
|
| 991 |
|
|
23 => (input_gf8x_1(23) xor output_gf8_1(14+32)),
|
| 992 |
|
|
22 => (input_gf8x_1(22) xor output_gf8_1(13+32)),
|
| 993 |
|
|
21 => (input_gf8x_1(21) xor output_gf8_1(15+32)),
|
| 994 |
|
|
20 => input_gf8x_1(20),
|
| 995 |
|
|
19 => (input_gf8x_1(19) xor output_gf8_1(15+32)),
|
| 996 |
|
|
18 => (input_gf8x_1(18) xor output_gf8_1(14+32)),
|
| 997 |
|
|
17 => (input_gf8x_1(17) xor '0'),
|
| 998 |
|
|
16 => input_gf8x_1(16),
|
| 999 |
|
|
15 => input_gf8x_1(15),
|
| 1000 |
|
|
14 => input_gf8x_1(14),
|
| 1001 |
|
|
13 => input_gf8x_1(13),
|
| 1002 |
|
|
12 => input_gf8x_1(12),
|
| 1003 |
|
|
11 => input_gf8x_1(11),
|
| 1004 |
|
|
10 => input_gf8x_1(10),
|
| 1005 |
|
|
9 => input_gf8x_1(9),
|
| 1006 |
|
|
8 => input_gf8x_1(8),
|
| 1007 |
|
|
7 => input_gf8x_1(7),
|
| 1008 |
|
|
6 => input_gf8x_1(6),
|
| 1009 |
|
|
5 => input_gf8x_1(5),
|
| 1010 |
|
|
4 => input_gf8x_1(4),
|
| 1011 |
|
|
3 => input_gf8x_1(3),
|
| 1012 |
|
|
2 => input_gf8x_1(2),
|
| 1013 |
|
|
1 => input_gf8x_1(1),
|
| 1014 |
|
|
|
| 1015 |
|
|
|
| 1016 |
|
|
|
| 1017 |
|
|
end GF8_xor_1;
|
| 1018 |
|
|
|
| 1019 |
|
|
architecture GF9_2 of CRC_top is
|
| 1020 |
|
|
|
| 1021 |
|
|
begin -- GF9_2
|
| 1022 |
|
|
|
| 1023 |
|
|
port map (
|
| 1024 |
|
|
reset => reset,
|
| 1025 |
|
|
phi2 => phi2,
|
| 1026 |
|
|
input_gf9_2 (63 downto 32) => output_gf8_1 (63 downto 32),
|
| 1027 |
|
|
input_gf9_2 (31 downto 0) => output_gf8x_1,
|
| 1028 |
|
|
output_gf9_2 (63 downto 32) => input_gf10_1 (63 downto 32),
|
| 1029 |
|
|
output_gf9_2 (31 downto 0) => input_gf9x_2);
|
| 1030 |
|
|
|
| 1031 |
|
|
if reset='0' then output_gf9_2 <= X'0000000000000000'
|
| 1032 |
|
|
elsif phi2='1' and phi2'event then output_gf9_2 <= input_gf9_2;
|
| 1033 |
|
|
end if;
|
| 1034 |
|
|
|
| 1035 |
|
|
end GF9_2;
|
| 1036 |
|
|
|
| 1037 |
|
|
|
| 1038 |
|
|
architecture GF9_xor_2 of CRC_top is
|
| 1039 |
|
|
|
| 1040 |
|
|
begin -- GF9_xor_2
|
| 1041 |
|
|
|
| 1042 |
|
|
port map (
|
| 1043 |
|
|
input_gf9x_2 => output_gf9_2 (31 downto 0),
|
| 1044 |
|
|
output_gf9x_2 => input_gf10_1 (31 downto 0));
|
| 1045 |
|
|
|
| 1046 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 1047 |
|
|
-- the 32 bits of the fcs
|
| 1048 |
|
|
|
| 1049 |
|
|
output_gf9x_2 (31 => input_gf9x_2(31),
|
| 1050 |
|
|
30 => input_gf9x_2(30),
|
| 1051 |
|
|
29 => input_gf9x_2(29),
|
| 1052 |
|
|
28 => input_gf9x_2(28),
|
| 1053 |
|
|
27 => input_gf9x_2(27),
|
| 1054 |
|
|
26 => (input_gf9x_2(26) xor output_gf9_2(15+32)),
|
| 1055 |
|
|
25 => (input_gf9x_2(25) xor output_gf9_2(14+32)),
|
| 1056 |
|
|
24 => (input_gf9x_2(24) xor output_gf9_2(15+32)),
|
| 1057 |
|
|
23 => (input_gf9x_2(23) xor output_gf9_2(15+32)),
|
| 1058 |
|
|
22 => (input_gf9x_2(22) xor output_gf9_2(14+32)),
|
| 1059 |
|
|
21 => (input_gf9x_2(21) xor '0'),
|
| 1060 |
|
|
20 => input_gf9x_2(20),
|
| 1061 |
|
|
19 => (input_gf9x_2(19) xor '0'),
|
| 1062 |
|
|
18 => (input_gf9x_2(18) xor '0'),
|
| 1063 |
|
|
17 => (input_gf9x_2(17) xor '0'),
|
| 1064 |
|
|
16 => input_gf9x_2(16),
|
| 1065 |
|
|
15 => input_gf9x_2(15),
|
| 1066 |
|
|
14 => input_gf9x_2(14),
|
| 1067 |
|
|
13 => input_gf9x_2(13),
|
| 1068 |
|
|
12 => input_gf9x_2(12),
|
| 1069 |
|
|
11 => input_gf9x_2(11),
|
| 1070 |
|
|
10 => input_gf9x_2(10),
|
| 1071 |
|
|
9 => input_gf9x_2(9),
|
| 1072 |
|
|
8 => input_gf9x_2(8),
|
| 1073 |
|
|
7 => input_gf9x_2(7),
|
| 1074 |
|
|
6 => input_gf9x_2(6),
|
| 1075 |
|
|
5 => input_gf9x_2(5),
|
| 1076 |
|
|
4 => input_gf9x_2(4),
|
| 1077 |
|
|
3 => input_gf9x_2(3),
|
| 1078 |
|
|
2 => input_gf9x_2(2),
|
| 1079 |
|
|
1 => input_gf9x_2(1),
|
| 1080 |
|
|
|
| 1081 |
|
|
|
| 1082 |
|
|
|
| 1083 |
|
|
end GF9_xor_2;
|
| 1084 |
|
|
|
| 1085 |
|
|
architecture GF10_1 of CRC_top is
|
| 1086 |
|
|
|
| 1087 |
|
|
begin -- GF10_1
|
| 1088 |
|
|
|
| 1089 |
|
|
port map (
|
| 1090 |
|
|
reset => reset,
|
| 1091 |
|
|
phi1 => phi1,
|
| 1092 |
|
|
input_gf10_1 (63 downto 32) => output_gf9_2 (63 downto 32),
|
| 1093 |
|
|
input_gf10_1 (31 downto 0) => output_gf9x_2,
|
| 1094 |
|
|
output_gf10_1 (63 downto 32) => input_gf11_2 (63 downto 32),
|
| 1095 |
|
|
output_gf10_1 (31 downto 0) => input_gf10x_1);
|
| 1096 |
|
|
|
| 1097 |
|
|
if reset='0' then output_gf10_1 <= X'0000000000000000'
|
| 1098 |
|
|
elsif phi1='1' and phi1'event then output_gf10_1 <= input_gf10_1;
|
| 1099 |
|
|
end if;
|
| 1100 |
|
|
|
| 1101 |
|
|
end GF10_1;
|
| 1102 |
|
|
|
| 1103 |
|
|
|
| 1104 |
|
|
architecture GF10_xor_1 of CRC_top is
|
| 1105 |
|
|
|
| 1106 |
|
|
begin -- GF10_xor_1
|
| 1107 |
|
|
|
| 1108 |
|
|
port map (
|
| 1109 |
|
|
input_gf10x_1 => output_gf10_1 (31 downto 0),
|
| 1110 |
|
|
output_gf10x_1 => input_gf11_2 (31 downto 0));
|
| 1111 |
|
|
|
| 1112 |
|
|
-- Some area optimizations could be done, since we don't use all
|
| 1113 |
|
|
-- the 32 bits of the fcs
|
| 1114 |
|
|
|
| 1115 |
|
|
output_gf10x_1 (31 => input_gf10x_1(31),
|
| 1116 |
|
|
30 => input_gf10x_1(30),
|
| 1117 |
|
|
29 => input_gf10x_1(29),
|
| 1118 |
|
|
28 => input_gf10x_1(28),
|
| 1119 |
|
|
27 => input_gf10x_1(27),
|
| 1120 |
|
|
26 => input_gf10x_1(26),
|
| 1121 |
|
|
25 => input_gf10x_1(25),
|
| 1122 |
|
|
24 => (input_gf10x_1(24) xor '0'),
|
| 1123 |
|
|
23 => (input_gf10x_1(23) xor '0'),
|
| 1124 |
|
|
22 => (input_gf10x_1(22) xor '0'),
|
| 1125 |
|
|
21 => input_gf10x_1(21),
|
| 1126 |
|
|
20 => input_gf10x_1(20),
|
| 1127 |
|
|
19 => input_gf10x_1(19),
|
| 1128 |
|
|
18 => input_gf10x_1(18),
|
| 1129 |
|
|
17 => input_gf10x_1(17),
|
| 1130 |
|
|
16 => input_gf10x_1(16),
|
| 1131 |
|
|
15 => input_gf10x_1(15),
|
| 1132 |
|
|
14 => input_gf10x_1(14),
|
| 1133 |
|
|
13 => input_gf10x_1(13),
|
| 1134 |
|
|
12 => input_gf10x_1(12),
|
| 1135 |
|
|
11 => input_gf10x_1(11),
|
| 1136 |
|
|
10 => input_gf10x_1(10),
|
| 1137 |
|
|
9 => input_gf10x_1(9),
|
| 1138 |
|
|
8 => input_gf10x_1(8),
|
| 1139 |
|
|
7 => input_gf10x_1(7),
|
| 1140 |
|
|
6 => input_gf10x_1(6),
|
| 1141 |
|
|
5 => input_gf10x_1(5),
|
| 1142 |
|
|
4 => input_gf10x_1(4),
|
| 1143 |
|
|
3 => input_gf10x_1(3),
|
| 1144 |
|
|
2 => input_gf10x_1(2),
|
| 1145 |
|
|
1 => input_gf10x_1(1),
|
| 1146 |
|
|
|
| 1147 |
|
|
|
| 1148 |
|
|
|
| 1149 |
|
|
end GF10_xor_1;
|
| 1150 |
|
|
|
| 1151 |
|
|
architecture GF11_2 of CRC_top is
|
| 1152 |
|
|
|
| 1153 |
|
|
begin -- GF11_2
|
| 1154 |
|
|
|
| 1155 |
|
|
port map (
|
| 1156 |
|
|
reset => reset,
|
| 1157 |
|
|
phi2 => phi2,
|
| 1158 |
|
|
input_gf11_2 => output_gf10x_1,
|
| 1159 |
|
|
output_gf11_2 => input_gf12_1;
|
| 1160 |
|
|
|
| 1161 |
|
|
if reset='0' then output_gf11_2 <= X'0000000000000000'
|
| 1162 |
|
|
elsif phi2='1' and phi2'event then output_gf11_2 <= input_gf11_2;
|
| 1163 |
|
|
end if;
|
| 1164 |
|
|
|
| 1165 |
|
|
end GF11_2;
|
| 1166 |
|
|
|
| 1167 |
|
|
|
| 1168 |
|
|
architecture GF12_1 of CRC_top is
|
| 1169 |
|
|
|
| 1170 |
|
|
begin -- GF12_1
|
| 1171 |
|
|
|
| 1172 |
|
|
port map (
|
| 1173 |
|
|
reset => reset,
|
| 1174 |
|
|
phi1 => phi1,
|
| 1175 |
|
|
input_gf12_1 => output_gf11_2,
|
| 1176 |
|
|
output_gf12_1(15 downto 0) => input_bigx12_1,
|
| 1177 |
|
|
output_gf12_1(31 downto 16) => input_fcs13_2(31 downto 16);
|
| 1178 |
|
|
|
| 1179 |
|
|
if reset='0' then output_gf12_1 <= X'0000000000000000'
|
| 1180 |
|
|
elsif phi1='1' and phi1'event then output_gf12_1 <= input_gf12_1;
|
| 1181 |
|
|
end if;
|
| 1182 |
|
|
|
| 1183 |
|
|
end GF12_1;
|
| 1184 |
|
|
|
| 1185 |
|
|
-- Final part of the circuit: XOR and output
|
| 1186 |
|
|
|
| 1187 |
|
|
architecture Big_XOR_12_1 of CRC_top is
|
| 1188 |
|
|
|
| 1189 |
|
|
begin -- Big_XOR_12_1
|
| 1190 |
|
|
|
| 1191 |
|
|
port map (
|
| 1192 |
|
|
input_bigx12_1 => input_bigx12_1,
|
| 1193 |
|
|
output_bigx12_1 => input_fcs13_2(15 downto 0));
|
| 1194 |
|
|
|
| 1195 |
|
|
output_bigx12_1 (15 => (input_bigx12_1(15) xor output12_1(15)),
|
| 1196 |
|
|
14 => (input_bigx12_1(14) xor output12_1(14)),
|
| 1197 |
|
|
13 => (input_bigx12_1(13) xor output12_1(13)),
|
| 1198 |
|
|
12 => (input_bigx12_1(12) xor output12_1(12)),
|
| 1199 |
|
|
11 => (input_bigx12_1(11) xor output12_1(11)),
|
| 1200 |
|
|
10 => (input_bigx12_1(10) xor output12_1(10)),
|
| 1201 |
|
|
9 => (input_bigx12_1(9) xor output12_1(9)),
|
| 1202 |
|
|
8 => (input_bigx12_1(8) xor output12_1(8)),
|
| 1203 |
|
|
7 => (input_bigx12_1(7) xor output12_1(7)),
|
| 1204 |
|
|
6 => (input_bigx12_1(6) xor output12_1(6)),
|
| 1205 |
|
|
5 => (input_bigx12_1(5) xor output12_1(5)),
|
| 1206 |
|
|
4 => (input_bigx12_1(4) xor output12_1(4)),
|
| 1207 |
|
|
3 => (input_bigx12_1(3) xor output12_1(3)),
|
| 1208 |
|
|
2 => (input_bigx12_1(2) xor output12_1(2)),
|
| 1209 |
|
|
1 => (input_bigx12_1(1) xor output12_1(1)),
|
| 1210 |
|
|
|
| 1211 |
|
|
|
| 1212 |
|
|
end Big_XOR_12_1;
|
| 1213 |
|
|
|
| 1214 |
|
|
architecture FCS_out_13_2 of CRC_top is
|
| 1215 |
|
|
|
| 1216 |
|
|
begin -- FCS_out_13_2
|
| 1217 |
|
|
|
| 1218 |
|
|
port map (
|
| 1219 |
|
|
reset => reset,
|
| 1220 |
|
|
phi2 => phi2,
|
| 1221 |
|
|
input_fcs13_2(15 downto 0) => output_bigx12_1,
|
| 1222 |
|
|
input_fcs13_2(31 downto 16) => output_gf12_1,
|
| 1223 |
|
|
output_fcs13_2 => input_gf1x_2, output_fcs13_2);
|
| 1224 |
|
|
|
| 1225 |
|
|
end FCS_out_13_2;
|
