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[/] [fast-crc/] [trunk/] [vhdl/] [gf_multiplier_tb.vhd] - Blame information for rev 4

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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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-- synopsys synthesis on
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library STD;
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use STD.TEXTIO.all;
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-- synopsys synthesis off
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entity gf_multiplier_tb is end gf_multiplier_tb;
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architecture structural of gf_multiplier_tb is
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component gf_multiplier
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  port (
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    phi1       : in    std_logic;
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    phi2       : in    std_logic;
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    reset      : in    std_logic;
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    input      : in    std_logic_vector(31 downto 0);
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    output_fcs : inout std_logic_vector(15 downto 0);
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    output_xor : out   std_logic_vector(15 downto 0));
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end component;
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signal phi1, phi2, reset : std_logic;
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signal input             : std_logic_vector(31 downto 0);
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signal output_fcs        : std_logic_vector(15 downto 0);
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signal output_xor        : std_logic_vector(15 downto 0);
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-- We also specify the files used to get the data and to put the data back
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file file_read     : text is in "/h/d1/c/x00jn/CRC_generator/data/data_multiplier_input.dat";
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file file_out_fcs  : text is out "/h/d1/c/x00jn/CRC_generator/data/data_multiplier_fcs_out.dat";
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file file_out_xor  : text is out "/h/d1/c/x00jn/CRC_generator/data/data_multiplier_xor_out.dat";
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begin  -- structural
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  -- Important: These parameters have been calculated for a 500MHz
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  -- relative clock -2 ns per stage-
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  p_phi1: process
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  begin  -- process p_phi1
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    phi1 <= '1', '0' after 2.1 ns;
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    wait for 4.2 ns;
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  end process p_phi1;
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  p_phi2: process
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  begin  -- process p_phi2
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    phi2 <= '1', '0' after 0.3 ns, '1' after 1.8 ns;
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    wait for 4.2 ns;
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  end process p_phi2;
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  p_reset: process
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  begin  -- process p_reset
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    reset <= '0' after 10 ns, '1' after 30 ns;
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    wait;
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  end process p_reset;
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  p_input: process (phi2)
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    variable input_file : bit_vector(31 downto 0);
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    variable line : line;
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  begin  -- process p_input
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   if phi2'event and phi2='1' then
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    if (not (endfile(file_read))) then
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      readline (file_read, line);
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      read(line, input_file);
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      input <= To_StdLogicVector(input_file);
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--      wait for 2 ns;                    -- IMPORTANT!! Modify this to change
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                                        -- the speed of the incoming data!
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    end if;
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   end if;
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  end process p_input;
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  p_output: process (phi1)
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    variable output_file_fcs : bit_vector(15 downto 0);
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    variable output_file_xor : bit_vector(15 downto 0);
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    variable line_fcs : line;
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    variable line_xor : line;
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  begin  -- process p_output
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    if phi1'event and phi1 = '1' then  -- rising clock edge
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      output_file_fcs:=To_BitVector(output_fcs);
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      write(line_fcs,output_file_fcs);
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      writeline(file_out_fcs,line_fcs);
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      output_file_xor:=To_BitVector(output_xor);
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      write(line_xor,output_file_xor);
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      writeline(file_out_xor,line_xor);
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    end if;
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  end process p_output;
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  gf_multiplier_1 : gf_multiplier port map (phi1 => phi1, phi2 => phi2, reset => reset,
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                                            input => input, output_fcs => output_fcs,
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                                            output_xor => output_xor);
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end structural;
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configuration cfg_gf_multiplier_tb_structural of gf_multiplier_tb is
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  for structural
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    for gf_multiplier_1: gf_multiplier use entity work.gf_multiplier(structural); end for;
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  end for;
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end cfg_gf_multiplier_tb_structural;

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