URL https://opencores.org/ocsvn/fast-crc/fast-crc/trunk

Subversion Repositories fast-crc

[/] [fast-crc/] [trunk/] [vhdl/] [gf_registers.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log


library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
entity gf_phi1_register_out is
 
  port (
      reset        : in  std_logic;           -- #RESET
      phi1         : in  std_logic;           -- Clock
      input_wip    : in  std_logic_vector(31 downto 0);
      output_final : out std_logic_vector(31 downto 0));
 
end gf_phi1_register_out;
 
 
architecture behavior of gf_phi1_register_out is
 
begin  -- gf_phi1_register_out
 
  -- purpose: This is the final register in the GF multiplier.
  -- It is a different entuty since it is much smaller that the "standard" ones
 
  p_gf_phi1_register_out: process (phi1, reset)
  begin  -- process p_gf_phi1_register_out
    if reset = '0' then                 -- asynchronous reset (active low)
      output_final <= X"46AF6449";
    elsif phi1'event and phi1 = '1' then  -- rising clock edge
      output_final <= input_wip;
    end if;
  end process p_gf_phi1_register_out;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi1_register_2 is
 
  port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi1_register_2;
 
 
architecture behavior of gf_phi1_register_2 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi1, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi1_register_2: process (phi1, reset)
  begin  -- process p_gf_phi1_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"E3ED5B2A";
    elsif phi1'event and phi1 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi1_register_2;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi2_register_3 is
 
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi2_register_3;
 
 
architecture behavior of gf_phi2_register_3 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi2, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi2_register_3: process (phi2, reset)
  begin  -- process p_gf_phi2_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"CEAD1918";
    elsif phi2'event and phi2 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi2_register_3;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi1_register_4 is
 
  port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi1_register_4;
 
 
architecture behavior of gf_phi1_register_4 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi1, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi1_register_4: process (phi1, reset)
  begin  -- process p_gf_phi1_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"90903DD8";
    elsif phi1'event and phi1 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi1_register_4;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi2_register_5 is
 
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi2_register_5;
 
 
architecture behavior of gf_phi2_register_5 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi2, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi2_register_5: process (phi2, reset)
  begin  -- process p_gf_phi2_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"74EBF27F";
    elsif phi2'event and phi2 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi2_register_5;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi1_register_6 is
 
  port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi1_register_6;
 
 
architecture behavior of gf_phi1_register_6 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi1, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi1_register_6: process (phi1, reset)
  begin  -- process p_gf_phi1_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"462A4987";
    elsif phi1'event and phi1 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi1_register_6;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi2_register_7 is
 
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi2_register_7;
 
 
architecture behavior of gf_phi2_register_7 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi2, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi2_register_7: process (phi2, reset)
  begin  -- process p_gf_phi2_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"46AFBDFF";
    elsif phi2'event and phi2 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi2_register_7;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi1_register_8 is
 
  port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi1_register_8;
 
 
architecture behavior of gf_phi1_register_8 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi1, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi1_register_8: process (phi1, reset)
  begin  -- process p_gf_phi1_register_8
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"46AF747D";
    elsif phi1'event and phi1 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi1_register_8;
 
end behavior;
 
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity gf_phi2_register_9 is
 
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
 
end gf_phi2_register_9;
 
 
architecture behavior of gf_phi2_register_9 is
 
begin  -- behavior
 
  -- purpose: 63 bit pipeline register
  -- type   : sequential
  -- inputs : phi2, reset, input_fcs, input_wip
  -- outputs: output_fcs, output_wip
  p_gf_phi2_register_9: process (phi2, reset)
  begin  -- process p_gf_phi2_register
    if reset = '0' then                 -- asynchronous reset (active low)
      output_fcs <= X"68B932F5";
      output_wip <= X"46AF7449";
    elsif phi2'event and phi2 = '1' then  -- rising clock edge
      output_fcs <= input_fcs;
      output_wip <= input_wip;
    end if;
  end process p_gf_phi2_register_9;
 
end behavior;
 
 
 
 
 
 
 
 
 
 
 

Browse

Tools

Subversion Repositories fast-crc

[/] [fast-crc/] [trunk/] [vhdl/] [gf_registers.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	trueno	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`-------------------------------------------------------------------------------`
4			`entity gf_phi1_register_out is`
5
6			`port (`
7			`reset : in std_logic; -- #RESET`
8			`phi1 : in std_logic; -- Clock`
9			`input_wip : in std_logic_vector(31 downto 0);`
10			`output_final : out std_logic_vector(31 downto 0));`
11
12			`end gf_phi1_register_out;`
13
14
15			`architecture behavior of gf_phi1_register_out is`
16
17			`begin -- gf_phi1_register_out`
18
19			`-- purpose: This is the final register in the GF multiplier.`
20			`-- It is a different entuty since it is much smaller that the "standard" ones`
21
22			`p_gf_phi1_register_out: process (phi1, reset)`
23			`begin -- process p_gf_phi1_register_out`
24			`if reset = '0' then -- asynchronous reset (active low)`
25			`output_final <= X"46AF6449";`
26			`elsif phi1'event and phi1 = '1' then -- rising clock edge`
27			`output_final <= input_wip;`
28			`end if;`
29			`end process p_gf_phi1_register_out;`
30
31			`end behavior;`
32
33			`-------------------------------------------------------------------------------`
34			`library IEEE;`
35			`use IEEE.std_logic_1164.all;`
36
37			`entity gf_phi1_register_2 is`
38
39			`port (`
40			`reset : in std_logic; -- #RESET`
41			`phi1 : in std_logic; -- Clock`
42			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
43			`input_fcs : in std_logic_vector(31 downto 0);`
44			`-- The original data for that step. Since we are using pipelining`
45			`-- we have to grant that we will have the original FCS data`
46			`-- available.`
47			`output_wip : out std_logic_vector(31 downto 0);`
48			`-- The modified data -our "WIP"-`
49			`output_fcs : out std_logic_vector(31 downto 0));`
50			`-- The original data is kept untouched`
51
52			`end gf_phi1_register_2;`
53
54
55			`architecture behavior of gf_phi1_register_2 is`
56
57			`begin -- behavior`
58
59			`-- purpose: 63 bit pipeline register`
60			`-- type : sequential`
61			`-- inputs : phi1, reset, input_fcs, input_wip`
62			`-- outputs: output_fcs, output_wip`
63			`p_gf_phi1_register_2: process (phi1, reset)`
64			`begin -- process p_gf_phi1_register`
65			`if reset = '0' then -- asynchronous reset (active low)`
66			`output_fcs <= X"68B932F5";`
67			`output_wip <= X"E3ED5B2A";`
68			`elsif phi1'event and phi1 = '1' then -- rising clock edge`
69			`output_fcs <= input_fcs;`
70			`output_wip <= input_wip;`
71			`end if;`
72			`end process p_gf_phi1_register_2;`
73
74			`end behavior;`
75
76			`-------------------------------------------------------------------------------`
77			`library IEEE;`
78			`use IEEE.std_logic_1164.all;`
79
80			`entity gf_phi2_register_3 is`
81
82			`port (`
83			`reset : in std_logic; -- #RESET`
84			`phi2 : in std_logic; -- Clock`
85			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
86			`input_fcs : in std_logic_vector(31 downto 0);`
87			`-- The original data for that step. Since we are using pipelining`
88			`-- we have to grant that we will have the original FCS data`
89			`-- available.`
90			`output_wip : out std_logic_vector(31 downto 0);`
91			`-- The modified data -our "WIP"-`
92			`output_fcs : out std_logic_vector(31 downto 0));`
93			`-- The original data is kept untouched`
94
95			`end gf_phi2_register_3;`
96
97
98			`architecture behavior of gf_phi2_register_3 is`
99
100			`begin -- behavior`
101
102			`-- purpose: 63 bit pipeline register`
103			`-- type : sequential`
104			`-- inputs : phi2, reset, input_fcs, input_wip`
105			`-- outputs: output_fcs, output_wip`
106			`p_gf_phi2_register_3: process (phi2, reset)`
107			`begin -- process p_gf_phi2_register`
108			`if reset = '0' then -- asynchronous reset (active low)`
109			`output_fcs <= X"68B932F5";`
110			`output_wip <= X"CEAD1918";`
111			`elsif phi2'event and phi2 = '1' then -- rising clock edge`
112			`output_fcs <= input_fcs;`
113			`output_wip <= input_wip;`
114			`end if;`
115			`end process p_gf_phi2_register_3;`
116
117			`end behavior;`
118
119			`-------------------------------------------------------------------------------`
120			`library IEEE;`
121			`use IEEE.std_logic_1164.all;`
122
123			`entity gf_phi1_register_4 is`
124
125			`port (`
126			`reset : in std_logic; -- #RESET`
127			`phi1 : in std_logic; -- Clock`
128			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
129			`input_fcs : in std_logic_vector(31 downto 0);`
130			`-- The original data for that step. Since we are using pipelining`
131			`-- we have to grant that we will have the original FCS data`
132			`-- available.`
133			`output_wip : out std_logic_vector(31 downto 0);`
134			`-- The modified data -our "WIP"-`
135			`output_fcs : out std_logic_vector(31 downto 0));`
136			`-- The original data is kept untouched`
137
138			`end gf_phi1_register_4;`
139
140
141			`architecture behavior of gf_phi1_register_4 is`
142
143			`begin -- behavior`
144
145			`-- purpose: 63 bit pipeline register`
146			`-- type : sequential`
147			`-- inputs : phi1, reset, input_fcs, input_wip`
148			`-- outputs: output_fcs, output_wip`
149			`p_gf_phi1_register_4: process (phi1, reset)`
150			`begin -- process p_gf_phi1_register`
151			`if reset = '0' then -- asynchronous reset (active low)`
152			`output_fcs <= X"68B932F5";`
153			`output_wip <= X"90903DD8";`
154			`elsif phi1'event and phi1 = '1' then -- rising clock edge`
155			`output_fcs <= input_fcs;`
156			`output_wip <= input_wip;`
157			`end if;`
158			`end process p_gf_phi1_register_4;`
159
160			`end behavior;`
161
162			`-------------------------------------------------------------------------------`
163			`library IEEE;`
164			`use IEEE.std_logic_1164.all;`
165
166			`entity gf_phi2_register_5 is`
167
168			`port (`
169			`reset : in std_logic; -- #RESET`
170			`phi2 : in std_logic; -- Clock`
171			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
172			`input_fcs : in std_logic_vector(31 downto 0);`
173			`-- The original data for that step. Since we are using pipelining`
174			`-- we have to grant that we will have the original FCS data`
175			`-- available.`
176			`output_wip : out std_logic_vector(31 downto 0);`
177			`-- The modified data -our "WIP"-`
178			`output_fcs : out std_logic_vector(31 downto 0));`
179			`-- The original data is kept untouched`
180
181			`end gf_phi2_register_5;`
182
183
184			`architecture behavior of gf_phi2_register_5 is`
185
186			`begin -- behavior`
187
188			`-- purpose: 63 bit pipeline register`
189			`-- type : sequential`
190			`-- inputs : phi2, reset, input_fcs, input_wip`
191			`-- outputs: output_fcs, output_wip`
192			`p_gf_phi2_register_5: process (phi2, reset)`
193			`begin -- process p_gf_phi2_register`
194			`if reset = '0' then -- asynchronous reset (active low)`
195			`output_fcs <= X"68B932F5";`
196			`output_wip <= X"74EBF27F";`
197			`elsif phi2'event and phi2 = '1' then -- rising clock edge`
198			`output_fcs <= input_fcs;`
199			`output_wip <= input_wip;`
200			`end if;`
201			`end process p_gf_phi2_register_5;`
202
203			`end behavior;`
204
205			`-------------------------------------------------------------------------------`
206			`library IEEE;`
207			`use IEEE.std_logic_1164.all;`
208
209			`entity gf_phi1_register_6 is`
210
211			`port (`
212			`reset : in std_logic; -- #RESET`
213			`phi1 : in std_logic; -- Clock`
214			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
215			`input_fcs : in std_logic_vector(31 downto 0);`
216			`-- The original data for that step. Since we are using pipelining`
217			`-- we have to grant that we will have the original FCS data`
218			`-- available.`
219			`output_wip : out std_logic_vector(31 downto 0);`
220			`-- The modified data -our "WIP"-`
221			`output_fcs : out std_logic_vector(31 downto 0));`
222			`-- The original data is kept untouched`
223
224			`end gf_phi1_register_6;`
225
226
227			`architecture behavior of gf_phi1_register_6 is`
228
229			`begin -- behavior`
230
231			`-- purpose: 63 bit pipeline register`
232			`-- type : sequential`
233			`-- inputs : phi1, reset, input_fcs, input_wip`
234			`-- outputs: output_fcs, output_wip`
235			`p_gf_phi1_register_6: process (phi1, reset)`
236			`begin -- process p_gf_phi1_register`
237			`if reset = '0' then -- asynchronous reset (active low)`
238			`output_fcs <= X"68B932F5";`
239			`output_wip <= X"462A4987";`
240			`elsif phi1'event and phi1 = '1' then -- rising clock edge`
241			`output_fcs <= input_fcs;`
242			`output_wip <= input_wip;`
243			`end if;`
244			`end process p_gf_phi1_register_6;`
245
246			`end behavior;`
247
248			`-------------------------------------------------------------------------------`
249			`library IEEE;`
250			`use IEEE.std_logic_1164.all;`
251
252			`entity gf_phi2_register_7 is`
253
254			`port (`
255			`reset : in std_logic; -- #RESET`
256			`phi2 : in std_logic; -- Clock`
257			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
258			`input_fcs : in std_logic_vector(31 downto 0);`
259			`-- The original data for that step. Since we are using pipelining`
260			`-- we have to grant that we will have the original FCS data`
261			`-- available.`
262			`output_wip : out std_logic_vector(31 downto 0);`
263			`-- The modified data -our "WIP"-`
264			`output_fcs : out std_logic_vector(31 downto 0));`
265			`-- The original data is kept untouched`
266
267			`end gf_phi2_register_7;`
268
269
270			`architecture behavior of gf_phi2_register_7 is`
271
272			`begin -- behavior`
273
274			`-- purpose: 63 bit pipeline register`
275			`-- type : sequential`
276			`-- inputs : phi2, reset, input_fcs, input_wip`
277			`-- outputs: output_fcs, output_wip`
278			`p_gf_phi2_register_7: process (phi2, reset)`
279			`begin -- process p_gf_phi2_register`
280			`if reset = '0' then -- asynchronous reset (active low)`
281			`output_fcs <= X"68B932F5";`
282			`output_wip <= X"46AFBDFF";`
283			`elsif phi2'event and phi2 = '1' then -- rising clock edge`
284			`output_fcs <= input_fcs;`
285			`output_wip <= input_wip;`
286			`end if;`
287			`end process p_gf_phi2_register_7;`
288
289			`end behavior;`
290
291			`-------------------------------------------------------------------------------`
292			`library IEEE;`
293			`use IEEE.std_logic_1164.all;`
294
295			`entity gf_phi1_register_8 is`
296
297			`port (`
298			`reset : in std_logic; -- #RESET`
299			`phi1 : in std_logic; -- Clock`
300			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
301			`input_fcs : in std_logic_vector(31 downto 0);`
302			`-- The original data for that step. Since we are using pipelining`
303			`-- we have to grant that we will have the original FCS data`
304			`-- available.`
305			`output_wip : out std_logic_vector(31 downto 0);`
306			`-- The modified data -our "WIP"-`
307			`output_fcs : out std_logic_vector(31 downto 0));`
308			`-- The original data is kept untouched`
309
310			`end gf_phi1_register_8;`
311
312
313			`architecture behavior of gf_phi1_register_8 is`
314
315			`begin -- behavior`
316
317			`-- purpose: 63 bit pipeline register`
318			`-- type : sequential`
319			`-- inputs : phi1, reset, input_fcs, input_wip`
320			`-- outputs: output_fcs, output_wip`
321			`p_gf_phi1_register_8: process (phi1, reset)`
322			`begin -- process p_gf_phi1_register_8`
323			`if reset = '0' then -- asynchronous reset (active low)`
324			`output_fcs <= X"68B932F5";`
325			`output_wip <= X"46AF747D";`
326			`elsif phi1'event and phi1 = '1' then -- rising clock edge`
327			`output_fcs <= input_fcs;`
328			`output_wip <= input_wip;`
329			`end if;`
330			`end process p_gf_phi1_register_8;`
331
332			`end behavior;`
333
334			`-------------------------------------------------------------------------------`
335			`library IEEE;`
336			`use IEEE.std_logic_1164.all;`
337
338			`entity gf_phi2_register_9 is`
339
340			`port (`
341			`reset : in std_logic; -- #RESET`
342			`phi2 : in std_logic; -- Clock`
343			`input_wip : in std_logic_vector(31 downto 0); -- The incoming WIP`
344			`input_fcs : in std_logic_vector(31 downto 0);`
345			`-- The original data for that step. Since we are using pipelining`
346			`-- we have to grant that we will have the original FCS data`
347			`-- available.`
348			`output_wip : out std_logic_vector(31 downto 0);`
349			`-- The modified data -our "WIP"-`
350			`output_fcs : out std_logic_vector(31 downto 0));`
351			`-- The original data is kept untouched`
352
353			`end gf_phi2_register_9;`
354
355
356			`architecture behavior of gf_phi2_register_9 is`
357
358			`begin -- behavior`
359
360			`-- purpose: 63 bit pipeline register`
361			`-- type : sequential`
362			`-- inputs : phi2, reset, input_fcs, input_wip`
363			`-- outputs: output_fcs, output_wip`
364			`p_gf_phi2_register_9: process (phi2, reset)`
365			`begin -- process p_gf_phi2_register`
366			`if reset = '0' then -- asynchronous reset (active low)`
367			`output_fcs <= X"68B932F5";`
368			`output_wip <= X"46AF7449";`
369			`elsif phi2'event and phi2 = '1' then -- rising clock edge`
370			`output_fcs <= input_fcs;`
371			`output_wip <= input_wip;`
372			`end if;`
373			`end process p_gf_phi2_register_9;`
374
375			`end behavior;`
376
377
378
379
380
381
382
383
384
385
386