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--------------------------------------------------------------------------------
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--
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-- BLK MEM GEN v7_2 Core - Stimulus Generator For Single Port Ram
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: bmg_stim_gen.vhd
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--
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-- Description:
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-- Stimulus Generation For SRAM
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-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
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-- simulation ends
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--
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--------------------------------------------------------------------------------
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-- Author: IP Solutions Division
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--
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-- History: Sep 12, 2011 - First Release
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--------------------------------------------------------------------------------
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE IEEE.STD_LOGIC_MISC.ALL;
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LIBRARY work;
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USE work.ALL;
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USE work.BMG_TB_PKG.ALL;
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ENTITY REGISTER_LOGIC_SRAM IS
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PORT(
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Q : OUT STD_LOGIC;
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CLK : IN STD_LOGIC;
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RST : IN STD_LOGIC;
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D : IN STD_LOGIC
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);
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END REGISTER_LOGIC_SRAM;
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ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
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SIGNAL Q_O : STD_LOGIC :='0';
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BEGIN
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Q <= Q_O;
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FF_BEH: PROCESS(CLK)
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BEGIN
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IF(RISING_EDGE(CLK)) THEN
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IF(RST ='1') THEN
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Q_O <= '0';
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ELSE
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Q_O <= D;
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END IF;
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END IF;
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END PROCESS;
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END REGISTER_ARCH;
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE IEEE.STD_LOGIC_MISC.ALL;
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LIBRARY work;
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USE work.ALL;
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USE work.BMG_TB_PKG.ALL;
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ENTITY BMG_STIM_GEN IS
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PORT (
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CLK : IN STD_LOGIC;
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RST : IN STD_LOGIC;
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ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
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DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
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CHECK_DATA: OUT STD_LOGIC:='0'
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);
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END BMG_STIM_GEN;
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ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
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CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
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SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
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SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
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SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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SIGNAL DO_WRITE : STD_LOGIC := '0';
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SIGNAL DO_READ : STD_LOGIC := '0';
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SIGNAL COUNT_NO : INTEGER :=0;
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SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
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BEGIN
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WRITE_ADDR_INT(11 DOWNTO 0) <= WRITE_ADDR(11 DOWNTO 0);
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READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
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ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
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DINA <= DINA_INT ;
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CHECK_DATA <= DO_READ;
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RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
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GENERIC MAP(
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C_MAX_DEPTH => 4096
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)
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PORT MAP(
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CLK => CLK,
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RST => RST,
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EN => DO_READ,
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LOAD => '0',
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LOAD_VALUE => ZERO,
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ADDR_OUT => READ_ADDR
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);
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WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
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GENERIC MAP(
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C_MAX_DEPTH => 4096 )
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PORT MAP(
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CLK => CLK,
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RST => RST,
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EN => DO_WRITE,
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LOAD => '0',
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LOAD_VALUE => ZERO,
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ADDR_OUT => WRITE_ADDR
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);
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WR_DATA_GEN_INST:ENTITY work.DATA_GEN
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GENERIC MAP (
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DATA_GEN_WIDTH => 8,
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DOUT_WIDTH => 8,
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DATA_PART_CNT => DATA_PART_CNT_A,
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SEED => 2
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)
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PORT MAP (
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CLK => CLK,
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RST => RST,
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EN => DO_WRITE,
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DATA_OUT => DINA_INT
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);
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WR_RD_PROCESS: PROCESS (CLK)
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BEGIN
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IF(RISING_EDGE(CLK)) THEN
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IF(RST='1') THEN
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DO_WRITE <= '0';
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DO_READ <= '0';
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COUNT_NO <= 0 ;
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ELSIF(COUNT_NO < 4) THEN
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DO_WRITE <= '1';
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DO_READ <= '0';
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COUNT_NO <= COUNT_NO + 1;
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ELSIF(COUNT_NO< 8) THEN
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DO_WRITE <= '0';
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DO_READ <= '1';
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COUNT_NO <= COUNT_NO + 1;
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ELSIF(COUNT_NO=8) THEN
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DO_WRITE <= '0';
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DO_READ <= '0';
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COUNT_NO <= 0 ;
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END IF;
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END IF;
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END PROCESS;
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BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
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BEGIN
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DFF_RIGHT: IF I=0 GENERATE
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BEGIN
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SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
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PORT MAP(
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Q => DO_READ_REG(0),
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CLK => CLK,
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RST => RST,
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D => DO_READ
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);
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END GENERATE DFF_RIGHT;
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DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
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BEGIN
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SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
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PORT MAP(
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Q => DO_READ_REG(I),
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CLK => CLK,
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RST => RST,
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D => DO_READ_REG(I-1)
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);
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END GENERATE DFF_OTHERS;
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END GENERATE BEGIN_SHIFT_REG;
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WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
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END ARCHITECTURE;
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