1 |
2 |
armando |
--===========================================================================--
|
2 |
|
|
--
|
3 |
|
|
-- CF SECTOR READER - HOST ATAPI UNIT (HAU)
|
4 |
|
|
--
|
5 |
|
|
-- - SEPTEMBER 2002
|
6 |
|
|
-- - UPV / EHU
|
7 |
|
|
--
|
8 |
|
|
-- - APPLIED ELECTRONICS RESEARCH TEAM (APERT)-
|
9 |
|
|
-- DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATIONS - BASQUE COUNTRY UNIVERSITY
|
10 |
|
|
--
|
11 |
|
|
-- THIS CODE IS DISTRIBUTED UNDER :
|
12 |
|
|
-- OpenIPCore Hardware General Public License "OHGPL"
|
13 |
|
|
-- http://www.opencores.org/OIPC/OHGPL.shtml
|
14 |
|
|
--
|
15 |
|
|
-- Design units : COMPACT FLASH TOOLS
|
16 |
|
|
--
|
17 |
|
|
-- File name : cf_sector_reader.vhd
|
18 |
|
|
--
|
19 |
|
|
-- Purpose : IDE interface and ATAPI p. managment
|
20 |
|
|
--
|
21 |
|
|
-- Library : WORK
|
22 |
|
|
--
|
23 |
|
|
-- Dependencies : IEEE.Std_Logic_1164
|
24 |
|
|
--
|
25 |
|
|
-- Simulator : ModelSim SE version 5.5e on a WindowsXP PC
|
26 |
|
|
--===========================================================================--
|
27 |
|
|
-------------------------------------------------------------------------------
|
28 |
|
|
-- Revision list
|
29 |
|
|
-- Version Author Date Changes
|
30 |
|
|
--
|
31 |
|
|
-- 270902 Armando Astarloa 27 September First VHDL synthesizable code
|
32 |
|
|
-- 070103 Armando Astarloa 07 January Included address 0 for wb bus
|
33 |
|
|
-- 090103 Armando Astarloa 09 January Included wb_in_bus inputs
|
34 |
|
|
-- Changed DAT_O to DAT_I_O (inout)
|
35 |
|
|
-- 200103 Armando Astarloa 20 January Changed triestate control of the WB bus
|
36 |
|
|
-- 280503 Armando Astarloa 28 May KCPSM V.1002 - with reset
|
37 |
|
|
-- 240603 Armando Astarloa 24 June Quit soft reset signals (with kcpsm
|
38 |
|
|
-- v.1002)
|
39 |
|
|
-------------------------------------------------------------------------------
|
40 |
|
|
-- Description : This module is an "active" IDE interface for sector
|
41 |
|
|
-- reading. Through the WB interface the LBA of the desired sector is written and
|
42 |
|
|
-- the module reads it from the IDE device following the ATAPI procol. The sector
|
43 |
|
|
-- data are given through doing consecutive requests.
|
44 |
|
|
-- NOTE : The WB interface of this module is not full Wishbone compatible due to
|
45 |
|
|
-- the "soft" proc. of the signals. If the designer wants to use it independently
|
46 |
|
|
-- an state machine for the ack signal should be added as the one added in
|
47 |
|
|
-- "cf_file_reader.vhd"
|
48 |
|
|
-------------------------------------------------------------------------------
|
49 |
|
|
-- Entity for cf_sector_reader Unit --
|
50 |
|
|
-------------------------------------------------------------------------------
|
51 |
|
|
library IEEE;
|
52 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
53 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
54 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
55 |
|
|
|
56 |
|
|
entity cf_sector_reader is
|
57 |
|
|
Port (
|
58 |
|
|
--
|
59 |
|
|
-- WISHBONE SIGNALS
|
60 |
|
|
--
|
61 |
|
|
RST_I: in std_logic; -- WB : Global RESET signal
|
62 |
|
|
ACK_O: out std_logic; -- WB : Ack to the master
|
63 |
|
|
ADR_I: in std_logic; -- WB : Register selection
|
64 |
|
|
CLK_I: in std_logic; -- WB : Global bus clock
|
65 |
|
|
DAT_I_O: inout std_logic_vector(15 downto 0 ); -- WB : 16 bits data bus input
|
66 |
|
|
STB_I: in std_logic; -- WB : Access qualify from master
|
67 |
|
|
WE_I: in std_logic; -- WB : Read/write request from master
|
68 |
|
|
TAG0_WORD_AVAILABLE: out std_logic; --
|
69 |
|
|
TAG1_WORD_REQUEST: in std_logic; -- IDE : Write Strobe
|
70 |
|
|
|
71 |
|
|
--
|
72 |
|
|
-- NON WISHBONE SIGNALS
|
73 |
|
|
--
|
74 |
|
|
IDE_BUS: inout std_logic_vector(15 downto 0 ); -- IDE DATA bidirectional bus
|
75 |
|
|
|
76 |
|
|
NIOWR: out std_logic; -- IDE : Write Strobe
|
77 |
|
|
NIORD: out std_logic; -- IDE : Read Strobe
|
78 |
|
|
NCE1: out std_logic; -- IDE : CE1
|
79 |
|
|
NCE0: out std_logic; -- IDE : CE2
|
80 |
|
|
A2: out std_logic; -- IDE : Address bit 2
|
81 |
|
|
A1: out std_logic; -- IDE : Address bit 1
|
82 |
|
|
A0: out std_logic; -- IDE : Address bit 0
|
83 |
|
|
|
84 |
|
|
ERROR: out std_logic -- Error on cf access
|
85 |
|
|
|
86 |
|
|
);
|
87 |
|
|
end cf_sector_reader;
|
88 |
|
|
|
89 |
|
|
architecture Behavioral of cf_sector_reader is
|
90 |
|
|
--
|
91 |
|
|
-- COMPONENT : KCPSM MICRO PICOBLAZE
|
92 |
|
|
--
|
93 |
|
|
component kcpsm is
|
94 |
|
|
Port (
|
95 |
|
|
address: out std_logic_vector(7 downto 0);
|
96 |
|
|
instruction : in std_logic_vector(15 downto 0);
|
97 |
|
|
port_id : out std_logic_vector(7 downto 0);
|
98 |
|
|
write_strobe : out std_logic;
|
99 |
|
|
out_port : out std_logic_vector(7 downto 0);
|
100 |
|
|
read_strobe : out std_logic;
|
101 |
|
|
in_port : in std_logic_vector(7 downto 0);
|
102 |
|
|
interrupt : in std_logic;
|
103 |
|
|
reset : in std_logic;
|
104 |
|
|
clk : in std_logic
|
105 |
|
|
);
|
106 |
|
|
end component;
|
107 |
|
|
|
108 |
|
|
--
|
109 |
|
|
-- COMPONENT :FIRMWARE ROM
|
110 |
|
|
--
|
111 |
|
|
component cfreader is
|
112 |
|
|
Port (
|
113 |
|
|
instruction: out std_logic_vector(15 downto 0);
|
114 |
|
|
address: in std_logic_vector(7 downto 0);
|
115 |
|
|
clk: in std_logic
|
116 |
|
|
);
|
117 |
|
|
|
118 |
|
|
end component;
|
119 |
|
|
--
|
120 |
|
|
-- MODULE INTERCONNECTION SIGNALS
|
121 |
|
|
--
|
122 |
|
|
signal ADDRESS_BUS : std_logic_vector(7 downto 0); -- FIRMWARE ROM ADDRESSES BUS
|
123 |
|
|
signal INSTRUCTIONS_BUS : std_logic_vector(15 downto 0); -- INSTRUCTIONS BUS
|
124 |
|
|
signal INPUTS_BUS : std_logic_vector(7 downto 0); -- INPUTS BUS
|
125 |
|
|
signal OUTPUTS_BUS : std_logic_vector(7 downto 0); -- OUTPUTS BUS
|
126 |
|
|
signal PORTS_ID : std_logic_vector(7 downto 0); -- PORTS ID
|
127 |
|
|
signal READ_STROBE : std_logic;
|
128 |
|
|
signal WRITE_STROBE : std_logic;
|
129 |
|
|
signal INTERRUPT : std_logic;
|
130 |
|
|
|
131 |
|
|
--
|
132 |
|
|
-- INTERNAL REGISTERS
|
133 |
|
|
--
|
134 |
|
|
|
135 |
|
|
|
136 |
|
|
signal DATA_IDE_OUT_7_0: std_logic_vector(7 downto 0); -- IDE DATA OUTPUT BUS
|
137 |
|
|
signal DATA_IDE_OUT_15_8: std_logic_vector(7 downto 0); -- IDE DATA OUTPUT BUS
|
138 |
|
|
signal IDE_CONTROL_OUT: std_logic_vector(1 downto 0); -- IDE BUS CONTROL SIGNALS
|
139 |
|
|
signal IDE_ADDRESS_OUT: std_logic_vector(4 downto 0); -- IDE ADDRESS SIGNALS
|
140 |
|
|
signal DATA_WB_OUT_7_0: std_logic_vector(7 downto 0); -- WISHBONE DATA OUTPUT BUS
|
141 |
|
|
signal DATA_WB_OUT_15_8: std_logic_vector(7 downto 0); -- WISHBONE DATA OUTPUT BUS
|
142 |
|
|
signal CONTROL_WB_OUT: std_logic_vector(1 downto 0); -- WISHBONE CONTROL SIGNALS
|
143 |
|
|
signal CONTROL_OUT: std_logic_vector(2 downto 0); -- GENERAL CONTROL SIGNALS
|
144 |
|
|
signal DATA_IDE_IN_7_0: std_logic_vector(7 downto 0); -- IDE DATA OUTPUT BUS
|
145 |
|
|
signal DATA_IDE_IN_15_8: std_logic_vector(7 downto 0); -- IDE DATA OUTPUT BUS
|
146 |
|
|
signal CONTROL_WB_IN:std_logic_vector(4 downto 0); -- WISHBONE CONTROL INPUT SIGNALS
|
147 |
|
|
signal DATA_WB_IN_7_0: std_logic_vector(7 downto 0); -- WISHBONE DATA INPUT BUS
|
148 |
|
|
signal DATA_WB_IN_15_8: std_logic_vector(7 downto 0); -- WISHBONE DATA INPUT BUS
|
149 |
|
|
|
150 |
|
|
--
|
151 |
|
|
-- CLOCK ENABLE FOR THE REGISTERS
|
152 |
|
|
--
|
153 |
|
|
signal DATA_IDE_OUT_7_0_CE : std_logic;
|
154 |
|
|
signal DATA_IDE_OUT_15_8_CE : std_logic;
|
155 |
|
|
signal IDE_CONTROL_OUT_CE : std_logic;
|
156 |
|
|
signal IDE_ADDRESS_OUT_CE : std_logic;
|
157 |
|
|
signal DATA_WB_OUT_7_0_CE : std_logic;
|
158 |
|
|
signal DATA_WB_OUT_15_8_CE : std_logic;
|
159 |
|
|
signal CONTROL_WB_OUT_CE : std_logic;
|
160 |
|
|
signal CONTROL_OUT_CE : std_logic;
|
161 |
|
|
signal DATA_IDE_IN_7_0_CE : std_logic;
|
162 |
|
|
signal DATA_IDE_IN_15_8_CE : std_logic;
|
163 |
|
|
signal CONTROL_WB_IN_CE : std_logic;
|
164 |
|
|
signal DATA_WB_IN_7_0_CE : std_logic;
|
165 |
|
|
signal DATA_WB_IN_15_8_CE : std_logic;
|
166 |
|
|
|
167 |
|
|
--
|
168 |
|
|
-- INTERNAL SIGNALS
|
169 |
|
|
--
|
170 |
|
|
signal IDE_BUS_WRITE_ENABLE : std_logic;
|
171 |
|
|
signal WB_BUS_WRITE_ENABLE : std_logic;
|
172 |
|
|
|
173 |
|
|
|
174 |
|
|
begin
|
175 |
|
|
|
176 |
|
|
--
|
177 |
|
|
-- COMPONENTS INSTANTATION
|
178 |
|
|
--
|
179 |
|
|
|
180 |
|
|
--
|
181 |
|
|
-- KCPSM INSTANTATION
|
182 |
|
|
--
|
183 |
|
|
micro:kcpsm port map (
|
184 |
|
|
address => ADDRESS_BUS,
|
185 |
|
|
instruction => INSTRUCTIONS_BUS,
|
186 |
|
|
port_id => PORTS_ID,
|
187 |
|
|
write_strobe => WRITE_STROBE,
|
188 |
|
|
out_port => OUTPUTS_BUS,
|
189 |
|
|
read_strobe => READ_STROBE,
|
190 |
|
|
in_port => INPUTS_BUS,
|
191 |
|
|
interrupt => INTERRUPT,
|
192 |
|
|
reset => RST_I,
|
193 |
|
|
clk => CLK_I);
|
194 |
|
|
--
|
195 |
|
|
-- FIRMWARE ROM INSTANTATION
|
196 |
|
|
--
|
197 |
|
|
rom:cfreader port map (
|
198 |
|
|
instruction => INSTRUCTIONS_BUS,
|
199 |
|
|
address => ADDRESS_BUS,
|
200 |
|
|
clk => CLK_I);
|
201 |
|
|
|
202 |
|
|
--
|
203 |
|
|
-- BUSES CONTROL
|
204 |
|
|
--
|
205 |
|
|
DAT_I_O <= (DATA_WB_OUT_15_8 & DATA_WB_OUT_7_0) when WB_BUS_WRITE_ENABLE = '1' else (others => 'Z');
|
206 |
|
|
DATA_WB_IN_15_8 <= DAT_I_O(15 downto 8);
|
207 |
|
|
DATA_WB_IN_7_0 <= DAT_I_O(7 downto 0);
|
208 |
|
|
-- WISHBONE BUS COMPOSITION
|
209 |
|
|
|
210 |
|
|
DATA_IDE_IN_15_8 <= IDE_BUS(15 downto 8); -- IDE INPUT BUS
|
211 |
|
|
DATA_IDE_IN_7_0 <= IDE_BUS(7 downto 0);
|
212 |
|
|
IDE_BUS <= (DATA_IDE_OUT_15_8 & DATA_IDE_OUT_7_0)
|
213 |
|
|
when IDE_BUS_WRITE_ENABLE='1' else (others =>'Z'); -- WRITING INTO IDE BIDIR BUS
|
214 |
|
|
|
215 |
|
|
|
216 |
|
|
|
217 |
|
|
--
|
218 |
|
|
-- SIGNALS CONNECTIONS
|
219 |
|
|
--
|
220 |
|
|
interrupt <= '0';
|
221 |
|
|
NIOWR <= IDE_CONTROL_OUT(1);
|
222 |
|
|
NIORD <= IDE_CONTROL_OUT(0);
|
223 |
|
|
|
224 |
|
|
NCE1 <= IDE_ADDRESS_OUT(4);
|
225 |
|
|
NCE0 <= IDE_ADDRESS_OUT(3);
|
226 |
|
|
A2 <= IDE_ADDRESS_OUT(2);
|
227 |
|
|
A1 <= IDE_ADDRESS_OUT(1);
|
228 |
|
|
A0 <= IDE_ADDRESS_OUT(0);
|
229 |
|
|
|
230 |
|
|
TAG0_WORD_AVAILABLE <= CONTROL_WB_OUT(1);
|
231 |
|
|
ACK_O <= CONTROL_WB_OUT(0);
|
232 |
|
|
|
233 |
|
|
ERROR <= CONTROL_OUT(2);
|
234 |
|
|
WB_BUS_WRITE_ENABLE <= CONTROL_OUT(1);
|
235 |
|
|
IDE_BUS_WRITE_ENABLE <= CONTROL_OUT(0); -- EXTRACT WRITE ENABLE SIGNAL FROM THE PORT
|
236 |
|
|
|
237 |
|
|
-- INPUTS
|
238 |
|
|
CONTROL_WB_IN (4) <= ADR_I;
|
239 |
|
|
CONTROL_WB_IN (2) <= WE_I;
|
240 |
|
|
CONTROL_WB_IN (1) <= TAG1_WORD_REQUEST;
|
241 |
|
|
CONTROL_WB_IN (0) <= STB_I;
|
242 |
|
|
|
243 |
|
|
--
|
244 |
|
|
-- INPUT PORTS DECODING
|
245 |
|
|
--
|
246 |
|
|
-- KCPSM DATASHEET NOTE:
|
247 |
|
|
-- The user interface logic is required to decode the port address value
|
248 |
|
|
-- and supply the correct data. Note that the Read_Strobe provides an
|
249 |
|
|
-- indicator that a port has been read, but in not vital to qualify a valid address.
|
250 |
|
|
--
|
251 |
|
|
process (CLK_I, RST_I)
|
252 |
|
|
begin
|
253 |
|
|
--
|
254 |
|
|
-- INPUT PORTS RESET STATE
|
255 |
|
|
--
|
256 |
|
|
if RST_I='1' then
|
257 |
|
|
|
258 |
|
|
INPUTS_BUS <= (others => '0'); -- WISHBONE CONTROL INPUT SIGNALS
|
259 |
|
|
--
|
260 |
|
|
-- SYNCRONOUS INPUT SIGNALS SAMPLE
|
261 |
|
|
--
|
262 |
|
|
elsif (CLK_I='1' and CLK_I'event) then
|
263 |
|
|
if CONTROL_WB_IN_CE='1' then
|
264 |
|
|
INPUTS_BUS(7 downto 4) <= (others => '0');
|
265 |
|
|
INPUTS_BUS(4 downto 0) <= CONTROL_WB_IN;
|
266 |
|
|
elsif DATA_IDE_IN_7_0_CE='1' THEN
|
267 |
|
|
INPUTS_BUS <= DATA_IDE_IN_7_0;
|
268 |
|
|
elsif DATA_IDE_IN_15_8_CE='1' THEN
|
269 |
|
|
INPUTS_BUS <= DATA_IDE_IN_15_8;
|
270 |
|
|
elsif DATA_WB_IN_7_0_CE='1' THEN
|
271 |
|
|
INPUTS_BUS <= DATA_WB_IN_7_0;
|
272 |
|
|
elsif DATA_WB_IN_15_8_CE='1' THEN
|
273 |
|
|
INPUTS_BUS <= DATA_WB_IN_15_8;
|
274 |
|
|
end if;
|
275 |
|
|
|
276 |
|
|
end if;
|
277 |
|
|
end process;
|
278 |
|
|
|
279 |
|
|
--
|
280 |
|
|
-- OUTPUT PORTS DECODING
|
281 |
|
|
--
|
282 |
|
|
-- KCPSM DATASHEET NOTE: The user interface logic is required to decode the port
|
283 |
|
|
-- address value and enable the correct logic to capture the data value. The
|
284 |
|
|
---Write_Strobe must be used in this case ensure the transfer of valid data only.
|
285 |
|
|
--
|
286 |
|
|
--
|
287 |
|
|
process (CLK_I, RST_I)
|
288 |
|
|
begin
|
289 |
|
|
--
|
290 |
|
|
-- OUTPUT PORTS RESET STATE
|
291 |
|
|
--
|
292 |
|
|
if RST_I = '1' then
|
293 |
|
|
-- NIOWR <= '1';
|
294 |
|
|
-- NIORD <= '1';
|
295 |
|
|
-- NCE1 <= '1';
|
296 |
|
|
-- NCE0 <= '1';
|
297 |
|
|
-- A2 <= '0';
|
298 |
|
|
-- A1 <= '0';
|
299 |
|
|
-- A0 <= '0';
|
300 |
|
|
DATA_IDE_OUT_7_0 <= (others => 'Z');
|
301 |
|
|
DATA_IDE_OUT_15_8 <= (others => 'Z');
|
302 |
|
|
IDE_CONTROL_OUT <= (others => 'Z');
|
303 |
|
|
IDE_ADDRESS_OUT <= (others => 'Z');
|
304 |
|
|
DATA_WB_OUT_7_0 <= (others => 'Z');
|
305 |
|
|
DATA_WB_OUT_15_8 <= (others => 'Z');
|
306 |
|
|
CONTROL_WB_OUT <= (others => 'Z');
|
307 |
|
|
CONTROL_OUT <=(others => 'Z');
|
308 |
|
|
|
309 |
|
|
--
|
310 |
|
|
-- SYNC LOAD
|
311 |
|
|
--
|
312 |
|
|
elsif (CLK_I='1' and CLK_I'event) then
|
313 |
|
|
if DATA_IDE_OUT_7_0_CE='1' then
|
314 |
|
|
DATA_IDE_OUT_7_0 <= OUTPUTS_BUS;
|
315 |
|
|
elsif DATA_IDE_OUT_15_8_CE='1' then
|
316 |
|
|
DATA_IDE_OUT_15_8 <= OUTPUTS_BUS;
|
317 |
|
|
elsif IDE_CONTROL_OUT_CE='1' then
|
318 |
|
|
IDE_CONTROL_OUT <= OUTPUTS_BUS(1 downto 0);
|
319 |
|
|
elsif IDE_ADDRESS_OUT_CE='1' then
|
320 |
|
|
IDE_ADDRESS_OUT <= OUTPUTS_BUS(4 downto 0);
|
321 |
|
|
elsif DATA_WB_OUT_7_0_CE='1' then
|
322 |
|
|
DATA_WB_OUT_7_0 <= OUTPUTS_BUS;
|
323 |
|
|
elsif DATA_WB_OUT_15_8_CE='1' then
|
324 |
|
|
DATA_WB_OUT_15_8 <= OUTPUTS_BUS;
|
325 |
|
|
elsif CONTROL_WB_OUT_CE='1' then
|
326 |
|
|
CONTROL_WB_OUT <= OUTPUTS_BUS(1 downto 0);
|
327 |
|
|
elsif CONTROL_OUT_CE='1' then
|
328 |
|
|
CONTROL_OUT <= OUTPUTS_BUS(2 downto 0);
|
329 |
|
|
else
|
330 |
|
|
null;
|
331 |
|
|
end if;
|
332 |
|
|
end if;
|
333 |
|
|
end process;
|
334 |
|
|
--
|
335 |
|
|
-- CLOCK ENABLE GENERATION (COMBINATIONAL => STUDY SYNC. IMPROVEMENTS)
|
336 |
|
|
--
|
337 |
|
|
--
|
338 |
|
|
-- OUTPUTS
|
339 |
|
|
--
|
340 |
|
|
process (WRITE_STROBE,PORTS_ID)
|
341 |
|
|
begin
|
342 |
|
|
if WRITE_STROBE = '1' then
|
343 |
|
|
case PORTS_ID is
|
344 |
|
|
when "00000000" =>
|
345 |
|
|
DATA_IDE_OUT_7_0_CE <= '1';
|
346 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
347 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
348 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
349 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
350 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
351 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
352 |
|
|
CONTROL_OUT_CE <= '0';
|
353 |
|
|
when "00000001" =>
|
354 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
355 |
|
|
DATA_IDE_OUT_15_8_CE <= '1';
|
356 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
357 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
358 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
359 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
360 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
361 |
|
|
CONTROL_OUT_CE <= '0';
|
362 |
|
|
when "00000010" =>
|
363 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
364 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
365 |
|
|
IDE_CONTROL_OUT_CE <= '1';
|
366 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
367 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
368 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
369 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
370 |
|
|
CONTROL_OUT_CE <= '0';
|
371 |
|
|
when "00000011" =>
|
372 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
373 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
374 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
375 |
|
|
IDE_ADDRESS_OUT_CE <= '1';
|
376 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
377 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
378 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
379 |
|
|
CONTROL_OUT_CE <= '0';
|
380 |
|
|
when "00000100" =>
|
381 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
382 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
383 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
384 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
385 |
|
|
DATA_WB_OUT_7_0_CE <= '1';
|
386 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
387 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
388 |
|
|
CONTROL_OUT_CE <= '0';
|
389 |
|
|
when "00000101" =>
|
390 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
391 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
392 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
393 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
394 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
395 |
|
|
DATA_WB_OUT_15_8_CE <= '1';
|
396 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
397 |
|
|
CONTROL_OUT_CE <= '0';
|
398 |
|
|
when "00000110" =>
|
399 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
400 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
401 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
402 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
403 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
404 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
405 |
|
|
CONTROL_WB_OUT_CE <= '1';
|
406 |
|
|
CONTROL_OUT_CE <= '0';
|
407 |
|
|
when "00000111" =>
|
408 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
409 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
410 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
411 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
412 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
413 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
414 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
415 |
|
|
CONTROL_OUT_CE <= '1';
|
416 |
|
|
when others =>
|
417 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
418 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
419 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
420 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
421 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
422 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
423 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
424 |
|
|
CONTROL_OUT_CE <= '0';
|
425 |
|
|
end case;
|
426 |
|
|
else
|
427 |
|
|
DATA_IDE_OUT_7_0_CE <= '0';
|
428 |
|
|
DATA_IDE_OUT_15_8_CE <= '0';
|
429 |
|
|
IDE_CONTROL_OUT_CE <= '0';
|
430 |
|
|
IDE_ADDRESS_OUT_CE <= '0';
|
431 |
|
|
DATA_WB_OUT_7_0_CE <= '0';
|
432 |
|
|
DATA_WB_OUT_15_8_CE <= '0';
|
433 |
|
|
CONTROL_WB_OUT_CE <= '0';
|
434 |
|
|
CONTROL_OUT_CE <= '0';
|
435 |
|
|
end if;
|
436 |
|
|
end process;
|
437 |
|
|
--
|
438 |
|
|
-- INPUTS
|
439 |
|
|
--
|
440 |
|
|
process (PORTS_ID)
|
441 |
|
|
begin
|
442 |
|
|
case PORTS_ID is
|
443 |
|
|
when "00000000" =>
|
444 |
|
|
DATA_IDE_IN_7_0_CE <= '1';
|
445 |
|
|
DATA_IDE_IN_15_8_CE <= '0';
|
446 |
|
|
CONTROL_WB_IN_CE <= '0';
|
447 |
|
|
DATA_WB_IN_7_0_CE <= '0';
|
448 |
|
|
DATA_WB_IN_15_8_CE <= '0';
|
449 |
|
|
|
450 |
|
|
when "00000001" =>
|
451 |
|
|
DATA_IDE_IN_7_0_CE <= '0';
|
452 |
|
|
DATA_IDE_IN_15_8_CE <= '1';
|
453 |
|
|
CONTROL_WB_IN_CE <= '0';
|
454 |
|
|
DATA_WB_IN_7_0_CE <= '0';
|
455 |
|
|
DATA_WB_IN_15_8_CE <= '0';
|
456 |
|
|
|
457 |
|
|
when "00000010" =>
|
458 |
|
|
DATA_IDE_IN_7_0_CE <= '0';
|
459 |
|
|
DATA_IDE_IN_15_8_CE <= '0';
|
460 |
|
|
CONTROL_WB_IN_CE <= '1';
|
461 |
|
|
DATA_WB_IN_7_0_CE <= '0';
|
462 |
|
|
DATA_WB_IN_15_8_CE <= '0';
|
463 |
|
|
|
464 |
|
|
when "00000011" =>
|
465 |
|
|
DATA_IDE_IN_7_0_CE <= '0';
|
466 |
|
|
DATA_IDE_IN_15_8_CE <= '0';
|
467 |
|
|
CONTROL_WB_IN_CE <= '0';
|
468 |
|
|
DATA_WB_IN_7_0_CE <= '1';
|
469 |
|
|
DATA_WB_IN_15_8_CE <= '0';
|
470 |
|
|
|
471 |
|
|
|
472 |
|
|
when "00000100" =>
|
473 |
|
|
DATA_IDE_IN_7_0_CE <= '0';
|
474 |
|
|
DATA_IDE_IN_15_8_CE <= '0';
|
475 |
|
|
CONTROL_WB_IN_CE <= '0';
|
476 |
|
|
DATA_WB_IN_7_0_CE <= '0';
|
477 |
|
|
DATA_WB_IN_15_8_CE <= '1';
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
|
481 |
|
|
when others =>
|
482 |
|
|
DATA_IDE_IN_7_0_CE <= '0';
|
483 |
|
|
DATA_IDE_IN_15_8_CE <= '0';
|
484 |
|
|
CONTROL_WB_IN_CE <= '0';
|
485 |
|
|
DATA_WB_IN_7_0_CE <= '0';
|
486 |
|
|
DATA_WB_IN_15_8_CE <= '0';
|
487 |
|
|
end case;
|
488 |
|
|
|
489 |
|
|
end process;
|
490 |
|
|
|
491 |
|
|
end Behavioral;
|