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-- Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices

--

-- Version : 1.00c

-- Version Date : 14th August 2002

--

-- Start of design entry : 2nd July 2002

--

-- Ken Chapman

-- Xilinx Ltd

-- Benchmark House

-- 203 Brooklands Road

-- Weybridge

-- Surrey KT13 ORH

-- United Kingdom

--

-- chapman@xilinx.com

--

------------------------------------------------------------------------------------

--

-- NOTICE:

--

-- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 

-- third parites.  By providing this core as one possible implementation of a standard,

-- Xilinx is making no representation that the provided implementation of this standard 

-- is free from any claims of infringement by any third party.  Xilinx expressly 

-- disclaims any warranty with respect to the adequacy of the implementation, including 

-- but not limited to any warranty or representation that the implementation is free 

-- from claims of any third party.  Futhermore, Xilinx is providing this core as a 

-- courtesy to you and suggests that you contact all third parties to obtain the 

-- necessary rights to use this implementation.

--

------------------------------------------------------------------------------------

--

-- Format of this file.

--

-- This file contains the definition of KCPSM and all the submodules which it 

-- required. The definition of KCPSM is placed at the end of this file as the order 

-- in which each entity is read is important for some simulation and synthesis tools.

-- Hence the first entity to be seen below is that of a submodule.

--

--

-- The submodules define the implementation of the logic using Xilinx primitives.

-- These ensure predictable synthesis results and maximise the density of the implementation. 

-- The Unisim Library is used to define Xilinx primitives. It is also used during

-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd

-- It is only specified in sub modules which contain primitive components.

-- 

-- library unisim;

-- use unisim.vcomponents.all;

--

------------------------------------------------------------------------------------

--

-- Description of sub-modules and further low level modules.

--

------------------------------------------------------------------------------------

--

-- Definition of an 8-bit bus 4 to 1 multiplexer with embeded select signal decoding.

-- 

-- sel1  sel0a  sel0b   Y_bus 

--  

--  0      0      x     D0_bus

--  0      1      x     D1_bus

--  1      x      0     D2_bus

--  1      x      1     D3_bus

--

-- sel1 is the pipelined decode of instruction12, instruction13, and instruction15.

-- sel0a is code2 after pipeline delay.

-- sel0b is instruction14 after pipeline delay.

--

-- Requires 17 LUTs and 3 flip-flops.

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library unisim;

use unisim.vcomponents.all;

--

entity data_bus_mux4 is

    Port (         D3_bus : in std_logic_vector(7 downto 0);

                   D2_bus : in std_logic_vector(7 downto 0);

                   D1_bus : in std_logic_vector(7 downto 0);

                   D0_bus : in std_logic_vector(7 downto 0);

            instruction15 : in std_logic;

            instruction14 : in std_logic;

            instruction13 : in std_logic;

            instruction12 : in std_logic;

                    code2 : in std_logic;

                    Y_bus : out std_logic_vector(7 downto 0);

                      clk : in std_logic );

    end data_bus_mux4;

--

architecture low_level_definition of data_bus_mux4 is

--

-- Internal signals

--

signal upper_selection : std_logic_vector(7 downto 0);

signal lower_selection : std_logic_vector(7 downto 0);

signal decode_sel1     : std_logic;

signal sel1            : std_logic;

signal sel0a           : std_logic;

signal sel0b           : std_logic;

--

-- Attribute to define LUT contents during implementation 

-- The information is repeated in the generic map for functional simulation

attribute INIT : string;

attribute INIT of decode_lut : label is "E0";

--

begin

  -- Forming decode signals

  decode_lut: LUT3

  --translate_off

    generic map (INIT => X"E0")

  --translate_on

  port map( I0 => instruction12,

            I1 => instruction13,

            I2 => instruction15,

             O => decode_sel1 );

  sel1_pipe: FD

  port map ( D => decode_sel1,

             Q => sel1,

             C => clk);

  sel0a_pipe: FD

  port map ( D => code2,

             Q => sel0a,

             C => clk);

  sel0b_pipe: FD

  port map ( D => instruction14,

             Q => sel0b,

             C => clk);

  bus_width_loop: for i in 0 to 7 generate

  --

  -- Attribute to define LUT contents during implementation 

  -- The information is repeated in the generic map for functional simulation

  attribute INIT : string;

  attribute INIT of high_mux_lut : label is "E4";

  attribute INIT of low_mux_lut  : label is "E4";

  --

  begin

    high_mux_lut: LUT3

    --translate_off

      generic map (INIT => X"E4")

    --translate_on

    port map( I0 => sel0b,

              I1 => D2_bus(i),

              I2 => D3_bus(i),

               O => upper_selection(i) );

    low_mux_lut: LUT3

    --translate_off

      generic map (INIT => X"E4")

    --translate_on

    port map( I0 => sel0a,

              I1 => D0_bus(i),

              I2 => D1_bus(i),

               O => lower_selection(i) );

    final_mux: MUXF5

    port map(  I1 => upper_selection(i),

               I0 => lower_selection(i),

                S => sel1,

                O => Y_bus(i) );

  end generate bus_width_loop;

--

end low_level_definition;

--

------------------------------------------------------------------------------------

--

-- Definition of an 8-bit shift/rotate process

--      

-- This function uses 11 LUTs.

-- The function contains an output pipeline register using 9 FDs.

--

-- Operation

--

-- The input operand is shifted by one bit left or right.

-- The bit which falls out of the end is passed to the carry_out.

-- The bit shifted in is determined by the select bits

--

--     code1    code0         Bit injected

--

--       0        0          carry_in           

--       0        1          msb of input_operand 

--       1        0          lsb of operand 

--       1        1          inject_bit 

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library unisim;

use unisim.vcomponents.all;

--

entity shift_rotate_process is

    Port    (    operand : in std_logic_vector(7 downto 0);

                carry_in : in std_logic;

              inject_bit : in std_logic;

             shift_right : in std_logic;

                   code1 : in std_logic;

                   code0 : in std_logic;

                       Y : out std_logic_vector(7 downto 0);

               carry_out : out std_logic;

                     clk : in std_logic);

    end shift_rotate_process;

--

architecture low_level_definition of shift_rotate_process is

--

-- Attribute to define LUT contents during implementation 

-- The information is repeated in the generic map for functional simulation

attribute INIT : string;

attribute INIT of high_mux_lut       : label is "E4";

attribute INIT of low_mux_lut        : label is "E4";

attribute INIT of carry_out_mux_lut  : label is "E4";

--

-- Internal signals

--

signal upper_selection : std_logic;

signal lower_selection : std_logic;

signal mux_output      : std_logic_vector(7 downto 0);

signal shift_in_bit    : std_logic;

signal carry_bit       : std_logic;

--

begin

  --

  -- 4 to 1 mux selection of the bit to be shifted in

  --

    high_mux_lut: LUT3

    --translate_off

      generic map (INIT => X"E4")

    --translate_on

    port map( I0 => code0,

              I1 => operand(0),

              I2 => inject_bit,

               O => upper_selection );

    low_mux_lut: LUT3

    --translate_off

      generic map (INIT => X"E4")

    --translate_on

    port map( I0 => code0,

              I1 => carry_in,

              I2 => operand(7),

               O => lower_selection );

    final_mux: MUXF5

    port map(  I1 => upper_selection,

               I0 => lower_selection,

                S => code1,

                O => shift_in_bit );

  --

  -- shift left or right of operand

  --

  bus_width_loop: for i in 0 to 7 generate

  --

  begin

     lsb_shift: if i=0 generate

        --

        -- Attribute to define LUT contents during implementation 

        -- The information is repeated in the generic map for functional simulation

        attribute INIT : string;

        attribute INIT of mux_lut : label is "E4";

        --

        begin

          mux_lut: LUT3

          --translate_off

            generic map (INIT => X"E4")

          --translate_on

          port map( I0 => shift_right,

                    I1 => shift_in_bit,

                    I2 => operand(i+1),

                     O => mux_output(i) );

        end generate lsb_shift;

     mid_shift: if i>0 and i<7 generate

        --

        -- Attribute to define LUT contents during implementation 

        -- The information is repeated in the generic map for functional simulation

        attribute INIT : string;

        attribute INIT of mux_lut : label is "E4";

        --

        begin

          mux_lut: LUT3

          --translate_off

            generic map (INIT => X"E4")

          --translate_on

          port map( I0 => shift_right,

                    I1 => operand(i-1),

                    I2 => operand(i+1),

                     O => mux_output(i) );

          end generate mid_shift;

     msb_shift: if i=7 generate

        --

        -- Attribute to define LUT contents during implementation 

        -- The information is repeated in the generic map for functional simulation

        attribute INIT : string;

        attribute INIT of mux_lut : label is "E4";

        --

        begin

          mux_lut: LUT3

          --translate_off

            generic map (INIT => X"E4")

          --translate_on

          port map( I0 => shift_right,

                    I1 => operand(i-1),

                    I2 => shift_in_bit,

                     O => mux_output(i) );

          end generate msb_shift;

     pipeline_bit: FD

     port map ( D => mux_output(i),

                Q => Y(i),

                C => clk);

  end generate bus_width_loop;

  --

  -- Selection of carry output

  --

  carry_out_mux_lut: LUT3

  --translate_off

    generic map (INIT => X"E4")

  --translate_on

  port map( I0 => shift_right,

            I1 => operand(7),

            I2 => operand(0),

             O => carry_bit );

  pipeline_bit: FD

  port map ( D => carry_bit,

             Q => carry_out,

             C => clk);

--

end low_level_definition;

--

------------------------------------------------------------------------------------

--

-- Definition of an 8-bit logical processing unit

--      

-- This function uses 8 LUTs (4 slices) to provide the logical bit operations.

-- The function contains an output pipeline register using 8 FDs.

--

--     Code1    Code0       Bit Operation

--

--       0        0            LOAD      Y <= second_operand 

--       0        1            AND       Y <= first_operand and second_operand

--       1        0            OR        Y <= first_operand or second_operand 

--       1        1            XOR       Y <= first_operand xor second_operand

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library unisim;

use unisim.vcomponents.all;

--

entity logical_bus_processing is

    Port (  first_operand : in std_logic_vector(7 downto 0);

           second_operand : in std_logic_vector(7 downto 0);

                    code1 : in std_logic;

                    code0 : in std_logic;

                        Y : out std_logic_vector(7 downto 0);

                      clk : in std_logic);

    end logical_bus_processing;

--

architecture low_level_definition of logical_bus_processing is

--

-- Internal signals

--

signal combinatorial_logical_processing : std_logic_vector(7 downto 0);

--

begin

  bus_width_loop: for i in 0 to 7 generate

  --

  -- Attribute to define LUT contents during implementation 

  -- The information is repeated in the generic map for functional simulation

  attribute INIT : string;

  attribute INIT of logical_lut : label is "6E8A";

  --

  begin

     logical_lut: LUT4

     --translate_off

     generic map (INIT => X"6E8A")

     --translate_on

     port map( I0 => second_operand(i),

               I1 => first_operand(i),

               I2 => code0,

               I3 => code1,

                O => combinatorial_logical_processing(i));

     pipeline_bit: FD

     port map ( D => combinatorial_logical_processing(i),

                Q => Y(i),

                C => clk);

  end generate bus_width_loop;

--

end low_level_definition;

--

------------------------------------------------------------------------------------

--

--

-- Definition of an 8-bit arithmetic process

--      

-- This function uses 10 LUTs and associated carry logic.

-- The function contains an output pipeline register using 9 FDs.

--

-- Operation

--

-- Two input operands are added or subtracted.

-- An input carry bit can be included in the calculation.

-- An output carry is always generated.

-- Carry signals work in the positive sense at all times.

--

--     code1     code0         Bit injected

--

--       0        0            ADD           

--       0        1            ADD with carry 

--       1        0            SUB  

--       1        1            SUB with carry 

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library unisim;

use unisim.vcomponents.all;

--

entity arithmetic_process is

    Port (  first_operand : in std_logic_vector(7 downto 0);

           second_operand : in std_logic_vector(7 downto 0);

                 carry_in : in std_logic;

                    code1 : in std_logic;

                    code0 : in std_logic;

                        Y : out std_logic_vector(7 downto 0);

                carry_out : out std_logic;

                      clk : in std_logic);

    end arithmetic_process;

--

architecture low_level_definition of arithmetic_process is

--

-- Internal signals

--

signal carry_in_bit       : std_logic;

signal carry_out_bit      : std_logic;

signal modified_carry_out : std_logic;

signal half_addsub        : std_logic_vector(7 downto 0);

signal full_addsub        : std_logic_vector(7 downto 0);

signal carry_chain        : std_logic_vector(6 downto 0);

--

--

-- Attributes to define LUT contents during implementation 

-- The information is repeated in the generic map for functional simulation

attribute INIT : string;

attribute INIT of carry_input_lut : label is "78";

attribute INIT of carry_output_lut : label is "6";

--

begin

  --

  -- Selection of the carry input to add/sub

  --

  carry_input_lut: LUT3

  --translate_off

    generic map (INIT => X"78")

  --translate_on

  port map( I0 => carry_in,

            I1 => code0,

            I2 => code1,

             O => carry_in_bit );

  --

  -- Main add/sub

  --    

  --    code1    Operation

  --

  --      0          ADD          Y <= first_operand + second_operand

  --      1          SUB          Y <= first_operand - second_operand

  --                

  bus_width_loop: for i in 0 to 7 generate

  --

  -- Attribute to define LUT contents during implementation 

  -- The information is repeated in the generic map for functional simulation

  attribute INIT : string;

  attribute INIT of arithmetic_lut : label is "96";

  --

  begin

     lsb_carry: if i=0 generate

        begin

          arithmetic_carry: MUXCY

          port map( DI => first_operand(i),

                    CI => carry_in_bit,

                     S => half_addsub(i),

                     O => carry_chain(i));

          arithmetic_xor: XORCY

          port map( LI => half_addsub(i),

                    CI => carry_in_bit,

                     O => full_addsub(i));

          end generate lsb_carry;

     mid_carry: if i>0 and i<7 generate

        begin

          arithmetic_carry: MUXCY

          port map( DI => first_operand(i),

                    CI => carry_chain(i-1),

                     S => half_addsub(i),

                     O => carry_chain(i));

          arithmetic_xor: XORCY

          port map( LI => half_addsub(i),

                    CI => carry_chain(i-1),

                     O => full_addsub(i));

          end generate mid_carry;

     msb_carry: if i=7 generate

        begin

          arithmetic_carry: MUXCY

          port map( DI => first_operand(i),

                    CI => carry_chain(i-1),

                     S => half_addsub(i),

                     O => carry_out_bit);

          arithmetic_xor: XORCY

          port map( LI => half_addsub(i),

                    CI => carry_chain(i-1),

                     O => full_addsub(i));

          end generate msb_carry;

     arithmetic_lut: LUT3

     --translate_off

     generic map (INIT => X"96")

     --translate_on

     port map( I0 => first_operand(i),

               I1 => second_operand(i),

               I2 => code1,

                O => half_addsub(i));

     pipeline_bit: FD

     port map ( D => full_addsub(i),

                Q => Y(i),

                C => clk);

  end generate bus_width_loop;

  --

  -- Modification to carry output and pipeline

  --

  carry_output_lut: LUT2

  --translate_off

    generic map (INIT => X"6")

  --translate_on

  port map( I0 => carry_out_bit,

            I1 => code1,

             O => modified_carry_out );

  pipeline_bit: FD

  port map ( D => modified_carry_out,

             Q => carry_out,

             C => clk);

--

end low_level_definition;

--

------------------------------------------------------------------------------------

--

-- Definition of the Zero and Carry Flags including decoding logic.

--      

-- The ZERO value is detected using 2 LUTs and associated carry logic to 

-- form a wired NOR gate. A further LUT selects the source for the ZERO flag

-- which is stored in an FDRE.

--

-- Definition of the Carry Flag 

--

-- 3 LUTs and a pipeline flip-flop are used to select the source for the 

-- CARRY flag which is stored in an FDRE.

--

-- Total size 11 LUTs and 5 flip-flops.

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library unisim;

use unisim.vcomponents.all;

--

entity flag_logic is

    Port (                data : in std_logic_vector(7 downto 0);

                 instruction15 : in std_logic;

                 instruction14 : in std_logic;

                 instruction13 : in std_logic;

                 instruction12 : in std_logic;

                  instruction8 : in std_logic;

                  instruction6 : in std_logic;

                          code : in std_logic_vector(2 downto 0);

                   shadow_zero : in std_logic;

                  shadow_carry : in std_logic;

            shift_rotate_carry : in std_logic;

                 add_sub_carry : in std_logic;

                         reset : in std_logic;

                       T_state : in std_logic;

                     zero_flag : out std_logic;

                    carry_flag : out std_logic;

                           clk : in std_logic);

    end flag_logic;

--

architecture low_level_definition of flag_logic is

--

-- Internal signals

--

signal enable1a                 : std_logic;

signal enable1a_carry           : std_logic;

signal enable1b                 : std_logic;

signal enable1b_carry           : std_logic;

signal flag_en_op_sx_or_returni : std_logic;

signal enable2a                 : std_logic;

signal enable2a_carry           : std_logic;

signal enable2b                 : std_logic;

signal enable2b_carry           : std_logic;

signal flag_en_op_sx_sy_or_kk   : std_logic;

signal flag_enable              : std_logic;

signal lower_zero               : std_logic;

signal upper_zero               : std_logic;

signal lower_zero_carry         : std_logic;

signal data_zero                : std_logic;

signal next_zero_flag           : std_logic;

signal carry_status             : std_logic;

signal next_carry_flag          : std_logic;

signal sX_op_decode             : std_logic;

signal sX_operation             : std_logic;

--

-- Attributes to define LUT contents during implementation 

-- The information is repeated in the generic map for functional simulation

attribute INIT : string;

attribute INIT of en1a_lut         : label is "F002";

attribute INIT of en1b_lut         : label is "4";

attribute INIT of en2a_lut         : label is "10FF";

attribute INIT of en2b_lut         : label is "FE";

attribute INIT of flag_enable_lut  : label is "A8";

attribute INIT of lower_zero_lut   : label is "0001";

attribute INIT of upper_zero_lut   : label is "0001";

attribute INIT of zero_select_lut  : label is "F4B0";

attribute INIT of operation_lut    : label is "2000";

attribute INIT of carry_status_lut : label is "EC20";

attribute INIT of carry_select_lut : label is "F4B0";

--

begin

  --

  -- Decode instructions requiring flags to be enabled

  --

  en1a_lut: LUT4

  --translate_off

    generic map (INIT => X"F002")

  --translate_on

  port map( I0 => instruction6,

            I1 => instruction8,

            I2 => instruction12,

            I3 => instruction14,

             O => enable1a );

  en1b_lut: LUT2

  --translate_off

    generic map (INIT => X"4")

  --translate_on

  port map( I0 => instruction13,

            I1 => instruction15,