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[/] [ffr16/] [trunk/] [sources/] [hau/] [240603KN/] [cfreader.psm] - Blame information for rev 13

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;--===========================================================================--
;--
;--  CF SECTOR READER
;--
;--  - SEPTEMBER 2002
;--  - APERT - UPV / EHU. - BASQUE COUNTRY UNIVERSITY
;--  - DISTRIBUTED UNDER GPL LICENSE
;--
;-- Design units        : FAT FILE LOADER
;--
;-- File name           : cfreader.psm
;--
;-- Purpose             : READ RAW SECTORS FROM CF
;--
;-- Library             : -
;--
;-- Languaje    : ASSEMBLER FOR XILINX PICOBLAZE
;--
;-- Compiler    : KCPSM ASSEMBLER V1.10
;--
;-- Debugger    : PSM DEBUG V1.00
;--===========================================================================--
;-------------------------------------------------------------------------------
;-- Revision list
;-- Version   Author                 Date           Changes
;--
;-- 260902    Armando Astarloa   27 September 2002  -
;-- 241002    Armando Astarloa   27 October   2002  Reset on error
;-- 031202    Armando Astarloa   27 December  2002  Load LBA information from data bus
;-- 120103        Armando Astarloa   12 January   2003  Quit status check when words reading
;-- 290103        Armando Astarloa   29 January   2003  Reset function. Reset after error
;-- 050503        Armando Astarloa   02 May         2003  Allow not all bytes of the sector read.
;--                                                                 do_reset_and_retry state
;-- 160503        Armando Astarloa   15 May         2003  Complete sector reading
;-- 170603        Armando Astarloa   17 June        2003  Bug in words per sector read
;-- 230603        Armando Astarloa   24 June        2003  Quit soft reset (KCPSM v.1002 has reset)
;--
;-------------------------------------------------------------------------------
;-- Description    :  DUMMY CF SECTORS READ
;-------------------------------------------------------------------------------
 
;--
;-- CONSTANT DEFINITIONS
;--
CONSTANT DELAY1,03
; 50 MHZ DELAY1 => T(clk_i) => fastloop=DELAY1*T*2= 120ns sF=1 => delay= sF*fastloop
; 50 MHZ DELAY1=03 => T=20NS => fastloop=3*20*2= 120ns sF=1 => delay= 120ns
CONSTANT IDENTIFY_COMMAND,EC
CONSTANT WRITE_SECTOR_COMMAND,30
CONSTANT READ_SECTOR_COMMAND,20
CONSTANT WRITE_SEC_FEATURE,00
CONSTANT SOFT_RESET,04
;--
;-- RAM REGISTERS
;--
 
;
; s0
; s1
; s2
; s3 -> WISHBONE CONTROL
; s4 -> REGISTERS STACK
; s5 -> MY_STATUS
;               D3 = ERROR
;               D2 = DATA TRANSFER ALLOWED (0 NOT / 1 YES)
;               D1 = COMMAND ALLOWED (NOT BUSY) (0 NOT / 1 YES)
;               D0 = SECTOR AVAILABLE (0 NOT / 1 YES)
                CONSTANT SECTOR_AVAILABLE,01
                CONSTANT COMMAND_ALLOWED,02
                CONSTANT DATA_TRANSFER_ALLOWED,04
                CONSTANT ERROR_MY_STATUS,08
; s6 -> WORDS_READ
; s7 -> LBA_7_0
; s8 -> LBA_15_8
; s9 -> LBA_23_16
; sA -> LD_LBA_27_24
; sB -> data[7:0] in ide
; sC -> data[15:8] in ide
; sD -> data[7:0] out ide
; sE -> data[15:8] out ide
; sF -> acummulator
;
 
;--
;-- OUTPUT PORTS
;--
 
                ;--
                ;-- IDE INTERFACE PORTS - OUTPUTS
                ;--
                CONSTANT DATA_IDE_OUT_7_0,00
                CONSTANT DATA_IDE_OUT_15_8,01
                CONSTANT IDE_CONTROL_OUT,02
                                                        ; D7 =
                                                        ; D6 =
                                                        ; D5 =
                                                        ; D4 =
                                                        ; D3 =
                                                        ; D2 =
                                                        ; D1 = NIOWR
                                                        ; D0 = NIORD
                                                        CONSTANT NIOWR,FD
                                                        CONSTANT NIORD,FE
 
                CONSTANT IDE_ADDRESS_OUT,03
                                                        ; D7 =
                                                        ; D6 =
                                                        ; D5 =
                                                        ; D4 = NCE1
                                                        ; D3 = NCE0
                                                        ; D2 = A2
                                                        ; D1 = A1
                                                        ; D0 = A0
                                                        ;
                                                        ; WRITE IDE REGISTERS
                                                        ;
                                                                                ;    NCE1/NCE0/ A2/ A1/ A0
                                                        CONSTANT CONTROL,0E     ; 000   0    1   1   1   0
                                                        CONSTANT DATA,10        ; 000   1    0   0   0   0
                                                        CONSTANT FEATURE,11     ; 000   1    0   0   0   1
                                                        CONSTANT SECTOR_COUNT,12; 000   1    0   0   1   0
                                                        CONSTANT LBA_7_0,13     ; 000   1    0   0   1   1
                                                        CONSTANT LBA_15_8,14    ; 000   1    0   1   0   0
                                                        CONSTANT LBA_23_16,15   ; 000   1    0   1   0   1
                                                        CONSTANT LD_LBA_27_24,16; 000   1    0   1   1   0
                                                        CONSTANT COMMAND,17     ; 000   1    0   1   1   1
                                                        CONSTANT CF_OFF,18      ; 000   1    1   0   0   0
                                                        ;
                                                        ; READ IDE REGISTERS
                                                                                        ;    NCE1/NCE0/ A2/ A1/ A0
                                                        CONSTANT A_STATUS,0E    ; 000   0    1   1   1   0
                                                        CONSTANT STATUS,17      ; 000   1    0   1   1   1
 
                ;--
                ;-- WISHBONE INTERFACE PORTS - OUTPUTS
                ;--
                CONSTANT DATA_WB_OUT_7_0,04
                CONSTANT DATA_WB_OUT_15_8,05
                CONSTANT CONTROL_WB_OUT,06
                                                        ; D7 =
                                                        ; D6 =
                                                        ; D5 =
                                                        ; D4 =
                                                        ; D3 =
                                                        ; D2 =
                                                        ; D1 = TAG0_WORD_AVAILABLE
                                                        ; D0 = ACK_CF_READER
                                                        CONSTANT ACK_CF_READER,01
                                                        CONSTANT TAG0_WORD_AVAILABLE,02
                ;--
                ;-- BUS CONTROL SIGNALS
                ;--
                CONSTANT CONTROL_OUT,07
                                                        ; D7 =
                                                        ; D6 =
                                                        ; D5 =
                                                        ; D4 =
                                                        ; D3 =
                                                        ; D2 = ERROR
                                                        ; D1 = WB_BUS_WRITE_ENABLE
                                                        ; D0 = IDE_BUS_WRITE_ENABLE
                                                        CONSTANT IDE_BUS_WRITE_ENABLE,01
                                                        CONSTANT WB_BUS_WRITE_ENABLE,02
                                                        CONSTANT ERROR,04
 
;--
;-- INPUT PORTS
;--
 
                ;--
                ;-- IDE INTERFACE PORTS - INPUTS
                ;--
                CONSTANT DATA_IDE_IN_7_0,00
                CONSTANT DATA_IDE_IN_15_8,01
 
                ;--
                ;-- WISHBONE INTERFACE PORTS - INPUTS
                ;--
                CONSTANT CONTROL_WB_IN,02
                                                        ; D7 =
                                                        ; D6 =
                                                        ; D5 =
                                                        ; D4 = WB_A0
                                                        ; D3 = -
                                                        ; D2 = W_WE
                                                        ; D1 = TAG1_WORD_REQUEST
                                                        ; D0 = STROBE_CF_READER
                                                        ;
                                                        ; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 0
                                                        CONSTANT WRITE_LBA_15_0,05
                                                        ; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 1
                                                        CONSTANT WRITE_LBA_27_16,15
                                                        CONSTANT STROBE_CF_READER_AND_RD,01
                                                        CONSTANT TAG1_WORD_REQUEST,02
                                                        CONSTANT W_WE,04
 
 
                ;--
                ;-- WISHBONE INTERFACE PORTS - INPUTS
                ;--
                CONSTANT DATA_WB_IN_7_0,03
                CONSTANT DATA_WB_IN_15_8,04
 
;--
;-- REGISTERS INITIALIZATION
;--
initialization:
                ;
                ; BUS CONTROL : WRITE NOT ENABLE
                ;
                LOAD sF,00
                OUTPUT sF,CONTROL_OUT
                ;
                ; WISHBONE BUS INITIALIZATION
                ;
                LOAD sF,00
                OUTPUT sF,DATA_WB_OUT_7_0
                OUTPUT sF,DATA_WB_OUT_15_8
                OUTPUT sF,CONTROL_WB_OUT
                ;
                ; IDE BUS INITIALIZATION
                ;
                LOAD sF,00
                OUTPUT sF,DATA_IDE_OUT_7_0
                OUTPUT sF,DATA_IDE_OUT_15_8
            LOAD sF,18
                OUTPUT sF,IDE_ADDRESS_OUT
                LOAD sF,FF
                OUTPUT sF,IDE_CONTROL_OUT
                ;
                ; WAIT FOR 210NS*31 (RESET DELAY)
                ;
                LOAD s5,00
                LOAD s6,00
                LOAD sF,FF
                CALL wait_loop
                CALL soft_reset
                LOAD sF,FF
                CALL wait_loop
                LOAD sF,FF
                CALL wait_loop
                LOAD sF,FF
                CALL wait_loop
 
main:
                ;
                ; CHECK WISHBONE BUS
                ;
                ; wait state for stb_i deassertion
                ;LOAD sF,01
                ;CALL wait_loop
                AND sF,sF
                AND sF,sF
                AND sF,sF
                AND sF,sF
                INPUT s3,CONTROL_WB_IN
                ;
                ; CHECK STROBE & READ
                ;
                LOAD sF,s3
                SUB sF,WRITE_LBA_15_0
                JUMP Z,store_lba_15_0
                LOAD sF,s3
                SUB sF,WRITE_LBA_27_16
                JUMP Z,store_lba_27_16
                LOAD sF,s3
                SUB sF,STROBE_CF_READER_AND_RD
                JUMP Z,put_data_in_wb_bus
                ;
                ; IF NOT READ REQUEST MAINTAIN SIGNAL
                ;
                LOAD sF,00
                OUTPUT sF,CONTROL_OUT
                OUTPUT sF,CONTROL_WB_OUT
                JUMP main
 
store_lba_15_0:
                ; DATA_WB_IN_7_0 -> s7 LBA_7_0
                INPUT s7,DATA_WB_IN_7_0
                ; DATA_WB_IN_15_8 -> s8 LBA_15_8
                INPUT s8,DATA_WB_IN_15_8
                ; SECTOR AVAILABLE / COMMAND AVAILABLE -> 0
                LOAD sF,00
                AND s5,sF
                JUMP wishbone_ack
 
store_lba_27_16:
                ; DATA_WB_IN_7_0 -> s9 LBA_23_16
                INPUT s9,DATA_WB_IN_7_0
                ; DATA_WB_IN_15_8 -> s10 LD_LBA_27_24
            INPUT sA,DATA_WB_IN_15_8
                ; SECTOR AVAILABLE -> 0
                ; antes 020503 LOAD sF,FE
                LOAD sF,00
                AND s5,sF
 
                JUMP wishbone_ack
do_reset_and_retry:
                CALL soft_reset
                LOAD s5,00
put_data_in_wb_bus:
                CALL read_word_from_cf
                ; check for error
                LOAD sF,s5
                AND sF,ERROR_MY_STATUS
                JUMP NZ,do_reset_and_retry
            OUTPUT sB,DATA_WB_OUT_7_0
            OUTPUT sC,DATA_WB_OUT_15_8
                ;
                ; ENABLE WB ENABLE
                ;
                LOAD sF,WB_BUS_WRITE_ENABLE
                OUTPUT sF,CONTROL_OUT
wishbone_ack:
                ;
                ; WISHBONE ACK
                ;
                LOAD sF,ACK_CF_READER
                OUTPUT sF,CONTROL_WB_OUT
                ; null - wait state
                ;
                AND sF,sF
                AND sF,sF
                AND sF,sF
                AND sF,sF
                ; WISHBONE MASTER MUST CHECK ACK SIGNAL
                ; IN THE RISING EDGE OF THE CLOCK AND DEASSERT
                ; STROBE SIGNAL. SLAVE AUTOMATICALLY DEASSERT ACK
                ;
                LOAD sF,00
                OUTPUT sF,CONTROL_WB_OUT
                ;OUTPUT sF,CONTROL_OUT
 
            JUMP main
 
wait_loop:
                ;
            ; SOFTWARE DELAY LOOP
                ; TAKES SLOW LOOP VALUE FROM sF
                ;
                ; TWO CYCLES PER INSTRUCTION
                ;
                ; SLOW LOOP 3 INSTRUCTIONS * sF
                ; FAST LOOP 2 INSTRUCTIONS * DELAY1
                ; 50 MHZ DELAY1=0A => T=20NS => fl=3*20*2= 120ns sF=1 => delay= 120ns
                LOAD s1,sF
    slow_loop:
                LOAD s0,DELAY1
    fast_loop:
                SUB s0,01
               JUMP NZ,fast_loop
                SUB s1,01
                JUMP NZ,slow_loop
                RETURN
 
write_ide_register:
                ;
                ; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT
                ;
                OUTPUT sF,IDE_ADDRESS_OUT
                ;
                ; DATA OUT IDE
                ;
                OUTPUT sD,DATA_IDE_OUT_7_0
                OUTPUT sE,DATA_IDE_OUT_15_8
                ;
                ; DATA OUT BUS ENABLE
                ;
                LOAD sF,IDE_BUS_WRITE_ENABLE
                OUTPUT sF,CONTROL_OUT
                ;
                ; WAIT FOR 70 NS (MIN)
                ; (120ns/50Mhz)
                LOAD sF,01
                CALL wait_loop
                ;
                ; WRITE STROBE ON
                ;
                LOAD sF,NIOWR
                OUTPUT sF,IDE_CONTROL_OUT
                ;
                ; WAIT FOR 165NS (MIN)
                ; (240ns/50Mhz)
                ; 020503
                LOAD sF,02
                CALL wait_loop
                ;
                ; WRITE STROBE OFF
                ;
                LOAD sF,FF
                OUTPUT sF,IDE_CONTROL_OUT
                ;
                ; WAIT FOR 20NS (MIN)
                ; (410ns/50Mhz)
                ; 020503
                ;LOAD sF,01
                ;CALL wait_loop
                ;
                ; CE AND ADRESSES OFF
                ;
                LOAD sF,CF_OFF
                OUTPUT sF,IDE_ADDRESS_OUT
                ;
                ; WAIT FOR 30NS (MIN) (if delay of the two previos inst>30ns this is not necessary)
                ; (put again 020503)
            LOAD sF,01
                CALL wait_loop
                ;
                ; DATA OUT BUS DISABLE
                ;
                LOAD sF,00
                OUTPUT sF,CONTROL_OUT
                ;
                ; (put again 020503)
            LOAD sF,02
                CALL wait_loop
                RETURN
 
read_ide_register:
                ;
                ; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT
                ;
                OUTPUT sF,IDE_ADDRESS_OUT
                ;
                ; WAIT FOR 70 NS (MIN)
                ;
            LOAD sF,01
                CALL wait_loop
                ;
                ; READ STROBE ON
                ; reset control_out (140503)
                LOAD sF,00
                OUTPUT sF,CONTROL_OUT
                LOAD sF,NIORD
                OUTPUT sF,IDE_CONTROL_OUT
                ;
                ; WAIT FOR 165NS (MIN)
                ;
            LOAD sF,02
                CALL wait_loop
                ;
                ; TAKE DE DATA FROM IDE BUS
                ;
                INPUT sB,DATA_IDE_IN_7_0
                INPUT sC,DATA_IDE_IN_15_8
                ;
                ; READ STROBE OFF
                ;
                LOAD sF,FF
                OUTPUT sF,IDE_CONTROL_OUT
                ;
                ; WAIT FOR 20NS (MIN)
                ;
                ;LOAD sF,01
                ;CALL wait_loop
                ;
                ; CE AND ADRESSES OFF
                ;
                LOAD sF,CF_OFF
                OUTPUT sF,IDE_ADDRESS_OUT
                ;
                ; WAIT FOR 20NS (MIN)
                ; (120ns/50mhz)
                ;LOAD sF,01
                ;CALL wait_loop
                RETURN
 
 
read_sector:
                ;
                ; WRITE ATA COMMANDS TO THE CF
                ;
                ;
                ; IDE FEATURE REGISTER
                ;
                LOAD sD,WRITE_SEC_FEATURE
                LOAD sF,FEATURE
                CALL write_ide_register
                ;
                ; IDE SECTOR COUNT REGISTER
                ;
                LOAD sD,01
                LOAD sF,SECTOR_COUNT
                CALL write_ide_register
                ;
                ; IDE LBA_7_0
                ;
                LOAD sD,s7
                LOAD sF,LBA_7_0
                CALL write_ide_register
                ;
                ; IDE LBA_15_8
                ;
                LOAD sD,s8
                LOAD sF,LBA_15_8
                CALL write_ide_register
                ;
                ; IDE LBA_23_16
                ;
                LOAD sD,s9
                LOAD sF,LBA_23_16
                CALL write_ide_register
 
                ;
                ; IDE LD_LBA_27_24
                ;
                ; LBA_27_42 OR WITH 1110
                ;                       BIT7 : 1
                ;                       BIT6 : LBA=1
                ;                       BIT5 : 1
                ;                       BIT4 : DRV=0
                ;
                ;
                LOAD sF,sA
                OR   sF,E0
                LOAD sD,sF
                LOAD sF,LD_LBA_27_24
                CALL write_ide_register
                ;
                ; IDE READ SECTOR COMMAND
                ;
                LOAD sD,READ_SECTOR_COMMAND
                LOAD sF,COMMAND
                CALL write_ide_register
                ;
                ; PUT SECTOR ALLOWED FLAG INTO MY_STATUS
                ;
                ; 290103 Added data available check
        retry_status_check:
                CALL cf_status_check
                LOAD sF,s5
                AND sF,ERROR_MY_STATUS
                RETURN NZ
                LOAD sF,DATA_TRANSFER_ALLOWED
                AND sF,s5
                ; LOOPS UNTIL SECTOR DATA IS AVAILABLE
                JUMP Z,retry_status_check
                LOAD sF,SECTOR_AVAILABLE
                OR s5,sF
                ;
                ; RESET WORDS READ REGISTER
                ;
                LOAD s6,FF
                RETURN
 
read_word_from_cf:
                ;
                ; CHECK IF THE SECTOR IS AVAILABLE
                ;
                LOAD sF,SECTOR_AVAILABLE
                AND sF,s5
                ;
                ; IF SECTOR_AVAILABLE=0 JUMP TO READ_NEW_SECTOR
                ;
                CALL Z,read_new_sector
                ; check for error
                LOAD sF,s5
                AND sF,ERROR_MY_STATUS
                RETURN NZ
                ;retry_status_check:
                ;CALL cf_status_check
                ;
                ; CHECK IF DATA IS AVAILABLE
                ;
                ; 120103 - changed . When there is sector
                ; available in the cf ram buffer it is not
                ; necessary to check neither bsy or drq
                ; only read words with the correct timing paramenters
                ;
                ;LOAD sF,DATA_TRANSFER_ALLOWED
                ;AND sF,s5
                ; LOOPS UNTIL SECTOR DATA IS AVAILABLE
                ;JUMP Z,retry_status_check
                ; end 120103
                ;
                ; IF 256 WORD READ -> SECTOR AVAILABLE=0
                ;
                CALL read_word
                AND s6,s6
                JUMP Z,reset_word_READ
                ;
                ; DECREMENT NUMBER OF WORDS READ
                ;
                SUB s6,01
                RETURN
 
reset_word_READ:
                ;
                ; IF 256 WORD READ -> SECTOR AVAILABLE=0
                ;
                ;ADD s7,01
                LOAD s6,FF
                LOAD sF,FE
                AND s5,sF
                RETURN
 
 
read_word:
                ;
                ; READ WORDS FROM IDE DATA REGISTERS
                ;
                LOAD sF,DATA
                CALL read_ide_register
                ;
                ; DATA ARE IN sB , sC
                ;
                ; DATA AVAILABLE SIGNAL IS STORED
                LOAD sF,TAG0_WORD_AVAILABLE
                OUTPUT sF,CONTROL_WB_OUT
                RETURN
dummy_word_read:
                CALL read_word
                SUB s6,01
read_new_sector:
                CALL cf_status_check
                LOAD sF,s5
                AND sF,DATA_TRANSFER_ALLOWED
                ;loops until previous non READ words are READ
                JUMP NZ,dummy_word_read
                LOAD sF,s5
                AND sF,ERROR_MY_STATUS
                RETURN NZ
                LOAD sF,s5
                AND sF,COMMAND_ALLOWED
                ; loops until commands are allowed
                LOAD s6,FF
                JUMP Z,read_new_sector
                JUMP read_sector
 
cf_status_check:
                ;
                ; CF STATUS REGISTER READ
                ;
                LOAD sF,STATUS
                CALL read_ide_register
                ;
                ; ERROR
                ;
                ;         BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR
                ; MASK    0    0   0   0   0    0 0   1
                ; ERR-ST  X    X   X   X   X    X X   1
                ; AND     0    0   0   0   0    0 0   1
                LOAD sF,01
                AND sF,sB
                JUMP NZ,put_error_code
 
                ;
                ; DATA REQUEST MASK (READY=1 : BUSY=0 : DRQ=1)
                ;
                ;         BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR
                ; MASK    1    1   0   0   1    0 0   1
                ; DRQ-ST  0    1   X   X   1    X X   0
                ; AND     0    1   0   0   1    0 0   0
                LOAD sF,C9
                AND sF,sB
                SUB sF,48
                JUMP Z,put_data_request_allowed
 
                ;
                ; COMMAND ALLOWED MASK (READY=1 : BUSY=0)
                ;
                ;         BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR
                ; MASK    1    1   0   0   0    0 0   1
                ; CMD-ST  0    1   X   X   0    X X   0
                ; AND     0    1   0   0   0    0 0   0
                LOAD sF,C1
                AND sF,sB
                SUB sF,40
                JUMP Z,put_command_allowed
 
                ;
                ; ELSE DATA_TRANSFER_ALLOWED & COMMAND_ALLOWED => 0
                ;
                ;JUMP put_error_code
                ; REVISAR ???
                ;AND s5,01
                RETURN
 
 
put_error_code:
                ;
                ; ERROR SIGNAL
                ;
                ; PUT ERROR CODE
                ;
                LOAD sF,04
            OUTPUT sF,CONTROL_OUT
                CALL soft_reset
                LOAD s5,ERROR_MY_STATUS
                RETURN
                ;JUMP initialization (STACK OVERFLOW???)
 
soft_reset:
                LOAD sD,SOFT_RESET
                LOAD sF,CONTROL
                CALL write_ide_register
                LOAD sF,FF
                CALL wait_loop
                LOAD sF,FF
                CALL wait_loop
                LOAD sF,FF
                CALL wait_loop
                LOAD sF,FF
                CALL wait_loop
                LOAD sD,00
                LOAD sF,CONTROL
                CALL write_ide_register
                RETURN
 
put_data_request_allowed:
                ;
                ; DRQ ALLOW -> MY STATUS REGISTER
                ;
                AND s5,FD
                LOAD sF,DATA_TRANSFER_ALLOWED
                OR s5,sF
                RETURN
 
put_command_allowed:
                ;
                ; DRQ ALLOW -> MY STATUS REGISTER
                ;
                AND s5,FB
                LOAD sF,COMMAND_ALLOWED
                OR s5,sF
                RETURN
 
                ADDRESS FF
 
interrupt:
                RETURNI ENABLE

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[/] [ffr16/] [trunk/] [sources/] [hau/] [240603KN/] [cfreader.psm] - Blame information for rev 13

Line No.	Rev	Author	Line
1	2	armando	`;--===========================================================================--`
2			`;--`
3			`;-- CF SECTOR READER`
4			`;--`
5			`;-- - SEPTEMBER 2002`
6			`;-- - APERT - UPV / EHU. - BASQUE COUNTRY UNIVERSITY`
7			`;-- - DISTRIBUTED UNDER GPL LICENSE`
8			`;--`
9			`;-- Design units : FAT FILE LOADER`
10			`;--`
11			`;-- File name : cfreader.psm`
12			`;--`
13			`;-- Purpose : READ RAW SECTORS FROM CF`
14			`;--`
15			`;-- Library : -`
16			`;--`
17			`;-- Languaje : ASSEMBLER FOR XILINX PICOBLAZE`
18			`;--`
19			`;-- Compiler : KCPSM ASSEMBLER V1.10`
20			`;--`
21			`;-- Debugger : PSM DEBUG V1.00`
22			`;--===========================================================================--`
23			`;-------------------------------------------------------------------------------`
24			`;-- Revision list`
25			`;-- Version Author Date Changes`
26			`;--`
27			`;-- 260902 Armando Astarloa 27 September 2002 -`
28			`;-- 241002 Armando Astarloa 27 October 2002 Reset on error`
29			`;-- 031202 Armando Astarloa 27 December 2002 Load LBA information from data bus`
30			`;-- 120103 Armando Astarloa 12 January 2003 Quit status check when words reading`
31			`;-- 290103 Armando Astarloa 29 January 2003 Reset function. Reset after error`
32			`;-- 050503 Armando Astarloa 02 May 2003 Allow not all bytes of the sector read.`
33			`;-- do_reset_and_retry state`
34			`;-- 160503 Armando Astarloa 15 May 2003 Complete sector reading`
35			`;-- 170603 Armando Astarloa 17 June 2003 Bug in words per sector read`
36			`;-- 230603 Armando Astarloa 24 June 2003 Quit soft reset (KCPSM v.1002 has reset)`
37			`;--`
38			`;-------------------------------------------------------------------------------`
39			`;-- Description : DUMMY CF SECTORS READ`
40			`;-------------------------------------------------------------------------------`
41
42			`;--`
43			`;-- CONSTANT DEFINITIONS`
44			`;--`
45			`CONSTANT DELAY1,03`
46			`; 50 MHZ DELAY1 => T(clk_i) => fastloop=DELAY1T2= 120ns sF=1 => delay= sF*fastloop`
47			`; 50 MHZ DELAY1=03 => T=20NS => fastloop=3202= 120ns sF=1 => delay= 120ns`
48			`CONSTANT IDENTIFY_COMMAND,EC`
49			`CONSTANT WRITE_SECTOR_COMMAND,30`
50			`CONSTANT READ_SECTOR_COMMAND,20`
51			`CONSTANT WRITE_SEC_FEATURE,00`
52			`CONSTANT SOFT_RESET,04`
53			`;--`
54			`;-- RAM REGISTERS`
55			`;--`
56
57			`;`
58			`; s0`
59			`; s1`
60			`; s2`
61			`; s3 -> WISHBONE CONTROL`
62			`; s4 -> REGISTERS STACK`
63			`; s5 -> MY_STATUS`
64			`; D3 = ERROR`
65			`; D2 = DATA TRANSFER ALLOWED (0 NOT / 1 YES)`
66			`; D1 = COMMAND ALLOWED (NOT BUSY) (0 NOT / 1 YES)`
67			`; D0 = SECTOR AVAILABLE (0 NOT / 1 YES)`
68			`CONSTANT SECTOR_AVAILABLE,01`
69			`CONSTANT COMMAND_ALLOWED,02`
70			`CONSTANT DATA_TRANSFER_ALLOWED,04`
71			`CONSTANT ERROR_MY_STATUS,08`
72			`; s6 -> WORDS_READ`
73			`; s7 -> LBA_7_0`
74			`; s8 -> LBA_15_8`
75			`; s9 -> LBA_23_16`
76			`; sA -> LD_LBA_27_24`
77			`; sB -> data[7:0] in ide`
78			`; sC -> data[15:8] in ide`
79			`; sD -> data[7:0] out ide`
80			`; sE -> data[15:8] out ide`
81			`; sF -> acummulator`
82			`;`
83
84			`;--`
85			`;-- OUTPUT PORTS`
86			`;--`
87
88			`;--`
89			`;-- IDE INTERFACE PORTS - OUTPUTS`
90			`;--`
91			`CONSTANT DATA_IDE_OUT_7_0,00`
92			`CONSTANT DATA_IDE_OUT_15_8,01`
93			`CONSTANT IDE_CONTROL_OUT,02`
94			`; D7 =`
95			`; D6 =`
96			`; D5 =`
97			`; D4 =`
98			`; D3 =`
99			`; D2 =`
100			`; D1 = NIOWR`
101			`; D0 = NIORD`
102			`CONSTANT NIOWR,FD`
103			`CONSTANT NIORD,FE`
104
105			`CONSTANT IDE_ADDRESS_OUT,03`
106			`; D7 =`
107			`; D6 =`
108			`; D5 =`
109			`; D4 = NCE1`
110			`; D3 = NCE0`
111			`; D2 = A2`
112			`; D1 = A1`
113			`; D0 = A0`
114			`;`
115			`; WRITE IDE REGISTERS`
116			`;`
117			`; NCE1/NCE0/ A2/ A1/ A0`
118			`CONSTANT CONTROL,0E ; 000 0 1 1 1 0`
119			`CONSTANT DATA,10 ; 000 1 0 0 0 0`
120			`CONSTANT FEATURE,11 ; 000 1 0 0 0 1`
121			`CONSTANT SECTOR_COUNT,12; 000 1 0 0 1 0`
122			`CONSTANT LBA_7_0,13 ; 000 1 0 0 1 1`
123			`CONSTANT LBA_15_8,14 ; 000 1 0 1 0 0`
124			`CONSTANT LBA_23_16,15 ; 000 1 0 1 0 1`
125			`CONSTANT LD_LBA_27_24,16; 000 1 0 1 1 0`
126			`CONSTANT COMMAND,17 ; 000 1 0 1 1 1`
127			`CONSTANT CF_OFF,18 ; 000 1 1 0 0 0`
128			`;`
129			`; READ IDE REGISTERS`
130			`; NCE1/NCE0/ A2/ A1/ A0`
131			`CONSTANT A_STATUS,0E ; 000 0 1 1 1 0`
132			`CONSTANT STATUS,17 ; 000 1 0 1 1 1`
133
134			`;--`
135			`;-- WISHBONE INTERFACE PORTS - OUTPUTS`
136			`;--`
137			`CONSTANT DATA_WB_OUT_7_0,04`
138			`CONSTANT DATA_WB_OUT_15_8,05`
139			`CONSTANT CONTROL_WB_OUT,06`
140			`; D7 =`
141			`; D6 =`
142			`; D5 =`
143			`; D4 =`
144			`; D3 =`
145			`; D2 =`
146			`; D1 = TAG0_WORD_AVAILABLE`
147			`; D0 = ACK_CF_READER`
148			`CONSTANT ACK_CF_READER,01`
149			`CONSTANT TAG0_WORD_AVAILABLE,02`
150			`;--`
151			`;-- BUS CONTROL SIGNALS`
152			`;--`
153			`CONSTANT CONTROL_OUT,07`
154			`; D7 =`
155			`; D6 =`
156			`; D5 =`
157			`; D4 =`
158			`; D3 =`
159			`; D2 = ERROR`
160			`; D1 = WB_BUS_WRITE_ENABLE`
161			`; D0 = IDE_BUS_WRITE_ENABLE`
162			`CONSTANT IDE_BUS_WRITE_ENABLE,01`
163			`CONSTANT WB_BUS_WRITE_ENABLE,02`
164			`CONSTANT ERROR,04`
165
166			`;--`
167			`;-- INPUT PORTS`
168			`;--`
169
170			`;--`
171			`;-- IDE INTERFACE PORTS - INPUTS`
172			`;--`
173			`CONSTANT DATA_IDE_IN_7_0,00`
174			`CONSTANT DATA_IDE_IN_15_8,01`
175
176			`;--`
177			`;-- WISHBONE INTERFACE PORTS - INPUTS`
178			`;--`
179			`CONSTANT CONTROL_WB_IN,02`
180			`; D7 =`
181			`; D6 =`
182			`; D5 =`
183			`; D4 = WB_A0`
184			`; D3 = -`
185			`; D2 = W_WE`
186			`; D1 = TAG1_WORD_REQUEST`
187			`; D0 = STROBE_CF_READER`
188			`;`
189			`; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 0`
190			`CONSTANT WRITE_LBA_15_0,05`
191			`; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 1`
192			`CONSTANT WRITE_LBA_27_16,15`
193			`CONSTANT STROBE_CF_READER_AND_RD,01`
194			`CONSTANT TAG1_WORD_REQUEST,02`
195			`CONSTANT W_WE,04`
196
197
198			`;--`
199			`;-- WISHBONE INTERFACE PORTS - INPUTS`
200			`;--`
201			`CONSTANT DATA_WB_IN_7_0,03`
202			`CONSTANT DATA_WB_IN_15_8,04`
203
204			`;--`
205			`;-- REGISTERS INITIALIZATION`
206			`;--`
207	5	armando	`initialization:`
208	2	armando	`;`
209			`; BUS CONTROL : WRITE NOT ENABLE`
210			`;`
211			`LOAD sF,00`
212			`OUTPUT sF,CONTROL_OUT`
213			`;`
214	5	armando	`; WISHBONE BUS INITIALIZATION`
215	2	armando	`;`
216			`LOAD sF,00`
217			`OUTPUT sF,DATA_WB_OUT_7_0`
218			`OUTPUT sF,DATA_WB_OUT_15_8`
219			`OUTPUT sF,CONTROL_WB_OUT`
220			`;`
221	5	armando	`; IDE BUS INITIALIZATION`
222	2	armando	`;`
223			`LOAD sF,00`
224			`OUTPUT sF,DATA_IDE_OUT_7_0`
225			`OUTPUT sF,DATA_IDE_OUT_15_8`
226			`LOAD sF,18`
227			`OUTPUT sF,IDE_ADDRESS_OUT`
228			`LOAD sF,FF`
229			`OUTPUT sF,IDE_CONTROL_OUT`
230			`;`
231			`; WAIT FOR 210NS*31 (RESET DELAY)`
232			`;`
233			`LOAD s5,00`
234			`LOAD s6,00`
235			`LOAD sF,FF`
236			`CALL wait_loop`
237			`CALL soft_reset`
238			`LOAD sF,FF`
239			`CALL wait_loop`
240			`LOAD sF,FF`
241			`CALL wait_loop`
242			`LOAD sF,FF`
243			`CALL wait_loop`
244
245			`main:`
246			`;`
247			`; CHECK WISHBONE BUS`
248			`;`
249			`; wait state for stb_i deassertion`
250			`;LOAD sF,01`
251			`;CALL wait_loop`
252			`AND sF,sF`
253			`AND sF,sF`
254			`AND sF,sF`
255			`AND sF,sF`
256			`INPUT s3,CONTROL_WB_IN`
257			`;`
258			`; CHECK STROBE & READ`
259			`;`
260			`LOAD sF,s3`
261			`SUB sF,WRITE_LBA_15_0`
262			`JUMP Z,store_lba_15_0`
263			`LOAD sF,s3`
264			`SUB sF,WRITE_LBA_27_16`
265			`JUMP Z,store_lba_27_16`
266			`LOAD sF,s3`
267			`SUB sF,STROBE_CF_READER_AND_RD`
268			`JUMP Z,put_data_in_wb_bus`
269			`;`
270			`; IF NOT READ REQUEST MAINTAIN SIGNAL`
271			`;`
272			`LOAD sF,00`
273			`OUTPUT sF,CONTROL_OUT`
274			`OUTPUT sF,CONTROL_WB_OUT`
275			`JUMP main`
276
277			`store_lba_15_0:`
278			`; DATA_WB_IN_7_0 -> s7 LBA_7_0`
279			`INPUT s7,DATA_WB_IN_7_0`
280			`; DATA_WB_IN_15_8 -> s8 LBA_15_8`
281			`INPUT s8,DATA_WB_IN_15_8`
282			`; SECTOR AVAILABLE / COMMAND AVAILABLE -> 0`
283			`LOAD sF,00`
284			`AND s5,sF`
285			`JUMP wishbone_ack`
286
287			`store_lba_27_16:`
288			`; DATA_WB_IN_7_0 -> s9 LBA_23_16`
289			`INPUT s9,DATA_WB_IN_7_0`
290			`; DATA_WB_IN_15_8 -> s10 LD_LBA_27_24`
291			`INPUT sA,DATA_WB_IN_15_8`
292			`; SECTOR AVAILABLE -> 0`
293			`; antes 020503 LOAD sF,FE`
294			`LOAD sF,00`
295			`AND s5,sF`
296
297			`JUMP wishbone_ack`
298			`do_reset_and_retry:`
299			`CALL soft_reset`
300			`LOAD s5,00`
301			`put_data_in_wb_bus:`
302			`CALL read_word_from_cf`
303			`; check for error`
304			`LOAD sF,s5`
305			`AND sF,ERROR_MY_STATUS`
306			`JUMP NZ,do_reset_and_retry`
307			`OUTPUT sB,DATA_WB_OUT_7_0`
308			`OUTPUT sC,DATA_WB_OUT_15_8`
309			`;`
310			`; ENABLE WB ENABLE`
311			`;`
312			`LOAD sF,WB_BUS_WRITE_ENABLE`
313			`OUTPUT sF,CONTROL_OUT`
314			`wishbone_ack:`
315			`;`
316			`; WISHBONE ACK`
317			`;`
318			`LOAD sF,ACK_CF_READER`
319			`OUTPUT sF,CONTROL_WB_OUT`
320			`; null - wait state`
321			`;`
322			`AND sF,sF`
323			`AND sF,sF`
324			`AND sF,sF`
325			`AND sF,sF`
326			`; WISHBONE MASTER MUST CHECK ACK SIGNAL`
327			`; IN THE RISING EDGE OF THE CLOCK AND DEASSERT`
328			`; STROBE SIGNAL. SLAVE AUTOMATICALLY DEASSERT ACK`
329			`;`
330			`LOAD sF,00`
331			`OUTPUT sF,CONTROL_WB_OUT`
332			`;OUTPUT sF,CONTROL_OUT`
333
334			`JUMP main`
335
336			`wait_loop:`
337			`;`
338			`; SOFTWARE DELAY LOOP`
339			`; TAKES SLOW LOOP VALUE FROM sF`
340			`;`
341			`; TWO CYCLES PER INSTRUCTION`
342			`;`
343			`; SLOW LOOP 3 INSTRUCTIONS * sF`
344			`; FAST LOOP 2 INSTRUCTIONS * DELAY1`
345			`; 50 MHZ DELAY1=0A => T=20NS => fl=3202= 120ns sF=1 => delay= 120ns`
346			`LOAD s1,sF`
347			`slow_loop:`
348			`LOAD s0,DELAY1`
349			`fast_loop:`
350			`SUB s0,01`
351			`JUMP NZ,fast_loop`
352			`SUB s1,01`
353			`JUMP NZ,slow_loop`
354			`RETURN`
355
356			`write_ide_register:`
357			`;`
358			`; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT`
359			`;`
360			`OUTPUT sF,IDE_ADDRESS_OUT`
361			`;`
362			`; DATA OUT IDE`
363			`;`
364			`OUTPUT sD,DATA_IDE_OUT_7_0`
365			`OUTPUT sE,DATA_IDE_OUT_15_8`
366			`;`
367			`; DATA OUT BUS ENABLE`
368			`;`
369			`LOAD sF,IDE_BUS_WRITE_ENABLE`
370			`OUTPUT sF,CONTROL_OUT`
371			`;`
372			`; WAIT FOR 70 NS (MIN)`
373			`; (120ns/50Mhz)`
374			`LOAD sF,01`
375			`CALL wait_loop`
376			`;`
377			`; WRITE STROBE ON`
378			`;`
379			`LOAD sF,NIOWR`
380			`OUTPUT sF,IDE_CONTROL_OUT`
381			`;`
382			`; WAIT FOR 165NS (MIN)`
383			`; (240ns/50Mhz)`
384			`; 020503`
385			`LOAD sF,02`
386			`CALL wait_loop`
387			`;`
388			`; WRITE STROBE OFF`
389			`;`
390			`LOAD sF,FF`
391			`OUTPUT sF,IDE_CONTROL_OUT`
392			`;`
393			`; WAIT FOR 20NS (MIN)`
394			`; (410ns/50Mhz)`
395			`; 020503`
396			`;LOAD sF,01`
397			`;CALL wait_loop`
398			`;`
399			`; CE AND ADRESSES OFF`
400			`;`
401			`LOAD sF,CF_OFF`
402			`OUTPUT sF,IDE_ADDRESS_OUT`
403			`;`
404			`; WAIT FOR 30NS (MIN) (if delay of the two previos inst>30ns this is not necessary)`
405			`; (put again 020503)`
406			`LOAD sF,01`
407			`CALL wait_loop`
408			`;`
409			`; DATA OUT BUS DISABLE`
410			`;`
411			`LOAD sF,00`
412			`OUTPUT sF,CONTROL_OUT`
413			`;`
414			`; (put again 020503)`
415			`LOAD sF,02`
416			`CALL wait_loop`
417			`RETURN`
418
419			`read_ide_register:`
420			`;`
421			`; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT`
422			`;`
423			`OUTPUT sF,IDE_ADDRESS_OUT`
424			`;`
425			`; WAIT FOR 70 NS (MIN)`
426			`;`
427			`LOAD sF,01`
428			`CALL wait_loop`
429			`;`
430			`; READ STROBE ON`
431			`; reset control_out (140503)`
432			`LOAD sF,00`
433			`OUTPUT sF,CONTROL_OUT`
434			`LOAD sF,NIORD`
435			`OUTPUT sF,IDE_CONTROL_OUT`
436			`;`
437			`; WAIT FOR 165NS (MIN)`
438			`;`
439			`LOAD sF,02`
440			`CALL wait_loop`
441			`;`
442			`; TAKE DE DATA FROM IDE BUS`
443			`;`
444			`INPUT sB,DATA_IDE_IN_7_0`
445			`INPUT sC,DATA_IDE_IN_15_8`
446			`;`
447			`; READ STROBE OFF`
448			`;`
449			`LOAD sF,FF`
450			`OUTPUT sF,IDE_CONTROL_OUT`
451			`;`
452			`; WAIT FOR 20NS (MIN)`
453			`;`
454			`;LOAD sF,01`
455			`;CALL wait_loop`
456			`;`
457			`; CE AND ADRESSES OFF`
458			`;`
459			`LOAD sF,CF_OFF`
460			`OUTPUT sF,IDE_ADDRESS_OUT`
461			`;`
462			`; WAIT FOR 20NS (MIN)`
463			`; (120ns/50mhz)`
464			`;LOAD sF,01`
465			`;CALL wait_loop`
466			`RETURN`
467
468
469			`read_sector:`
470			`;`
471			`; WRITE ATA COMMANDS TO THE CF`
472			`;`
473			`;`
474			`; IDE FEATURE REGISTER`
475			`;`
476			`LOAD sD,WRITE_SEC_FEATURE`
477			`LOAD sF,FEATURE`
478			`CALL write_ide_register`
479			`;`
480			`; IDE SECTOR COUNT REGISTER`
481			`;`
482			`LOAD sD,01`
483			`LOAD sF,SECTOR_COUNT`
484			`CALL write_ide_register`
485			`;`
486			`; IDE LBA_7_0`
487			`;`
488			`LOAD sD,s7`
489			`LOAD sF,LBA_7_0`
490			`CALL write_ide_register`
491			`;`
492			`; IDE LBA_15_8`
493			`;`
494			`LOAD sD,s8`
495			`LOAD sF,LBA_15_8`
496			`CALL write_ide_register`
497			`;`
498			`; IDE LBA_23_16`
499			`;`
500			`LOAD sD,s9`
501			`LOAD sF,LBA_23_16`
502			`CALL write_ide_register`
503
504			`;`
505			`; IDE LD_LBA_27_24`
506			`;`
507			`; LBA_27_42 OR WITH 1110`
508			`; BIT7 : 1`
509			`; BIT6 : LBA=1`
510			`; BIT5 : 1`
511			`; BIT4 : DRV=0`
512			`;`
513			`;`
514			`LOAD sF,sA`
515			`OR sF,E0`
516			`LOAD sD,sF`
517			`LOAD sF,LD_LBA_27_24`
518			`CALL write_ide_register`
519			`;`
520			`; IDE READ SECTOR COMMAND`
521			`;`
522			`LOAD sD,READ_SECTOR_COMMAND`
523			`LOAD sF,COMMAND`
524			`CALL write_ide_register`
525			`;`
526			`; PUT SECTOR ALLOWED FLAG INTO MY_STATUS`
527			`;`
528			`; 290103 Added data available check`
529			`retry_status_check:`
530			`CALL cf_status_check`
531			`LOAD sF,s5`
532			`AND sF,ERROR_MY_STATUS`
533			`RETURN NZ`
534			`LOAD sF,DATA_TRANSFER_ALLOWED`
535			`AND sF,s5`
536			`; LOOPS UNTIL SECTOR DATA IS AVAILABLE`
537			`JUMP Z,retry_status_check`
538			`LOAD sF,SECTOR_AVAILABLE`
539			`OR s5,sF`
540			`;`
541			`; RESET WORDS READ REGISTER`
542			`;`
543			`LOAD s6,FF`
544			`RETURN`
545
546			`read_word_from_cf:`
547			`;`
548			`; CHECK IF THE SECTOR IS AVAILABLE`
549			`;`
550			`LOAD sF,SECTOR_AVAILABLE`
551			`AND sF,s5`
552			`;`
553			`; IF SECTOR_AVAILABLE=0 JUMP TO READ_NEW_SECTOR`
554			`;`
555			`CALL Z,read_new_sector`
556			`; check for error`
557			`LOAD sF,s5`
558			`AND sF,ERROR_MY_STATUS`
559			`RETURN NZ`
560			`;retry_status_check:`
561			`;CALL cf_status_check`
562			`;`
563			`; CHECK IF DATA IS AVAILABLE`
564			`;`
565			`; 120103 - changed . When there is sector`
566			`; available in the cf ram buffer it is not`
567			`; necessary to check neither bsy or drq`
568			`; only read words with the correct timing paramenters`
569			`;`
570			`;LOAD sF,DATA_TRANSFER_ALLOWED`
571			`;AND sF,s5`
572			`; LOOPS UNTIL SECTOR DATA IS AVAILABLE`
573			`;JUMP Z,retry_status_check`
574			`; end 120103`
575			`;`
576			`; IF 256 WORD READ -> SECTOR AVAILABLE=0`
577			`;`
578			`CALL read_word`
579			`AND s6,s6`
580			`JUMP Z,reset_word_READ`
581			`;`
582			`; DECREMENT NUMBER OF WORDS READ`
583			`;`
584			`SUB s6,01`
585			`RETURN`
586
587			`reset_word_READ:`
588			`;`
589			`; IF 256 WORD READ -> SECTOR AVAILABLE=0`
590			`;`
591			`;ADD s7,01`
592			`LOAD s6,FF`
593			`LOAD sF,FE`
594			`AND s5,sF`
595			`RETURN`
596
597
598			`read_word:`
599			`;`
600			`; READ WORDS FROM IDE DATA REGISTERS`
601			`;`
602			`LOAD sF,DATA`
603			`CALL read_ide_register`
604			`;`
605			`; DATA ARE IN sB , sC`
606			`;`
607			`; DATA AVAILABLE SIGNAL IS STORED`
608			`LOAD sF,TAG0_WORD_AVAILABLE`
609			`OUTPUT sF,CONTROL_WB_OUT`
610			`RETURN`
611			`dummy_word_read:`
612			`CALL read_word`
613			`SUB s6,01`
614			`read_new_sector:`
615			`CALL cf_status_check`
616			`LOAD sF,s5`
617			`AND sF,DATA_TRANSFER_ALLOWED`
618			`;loops until previous non READ words are READ`
619			`JUMP NZ,dummy_word_read`
620			`LOAD sF,s5`
621			`AND sF,ERROR_MY_STATUS`
622			`RETURN NZ`
623			`LOAD sF,s5`
624			`AND sF,COMMAND_ALLOWED`
625			`; loops until commands are allowed`
626			`LOAD s6,FF`
627			`JUMP Z,read_new_sector`
628			`JUMP read_sector`
629
630			`cf_status_check:`
631			`;`
632			`; CF STATUS REGISTER READ`
633			`;`
634			`LOAD sF,STATUS`
635			`CALL read_ide_register`
636			`;`
637			`; ERROR`
638			`;`
639			`; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR`
640			`; MASK 0 0 0 0 0 0 0 1`
641			`; ERR-ST X X X X X X X 1`
642			`; AND 0 0 0 0 0 0 0 1`
643			`LOAD sF,01`
644			`AND sF,sB`
645			`JUMP NZ,put_error_code`
646
647			`;`
648			`; DATA REQUEST MASK (READY=1 : BUSY=0 : DRQ=1)`
649			`;`
650			`; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR`
651			`; MASK 1 1 0 0 1 0 0 1`
652			`; DRQ-ST 0 1 X X 1 X X 0`
653			`; AND 0 1 0 0 1 0 0 0`
654			`LOAD sF,C9`
655			`AND sF,sB`
656			`SUB sF,48`
657			`JUMP Z,put_data_request_allowed`
658
659			`;`
660			`; COMMAND ALLOWED MASK (READY=1 : BUSY=0)`
661			`;`
662			`; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR`
663			`; MASK 1 1 0 0 0 0 0 1`
664			`; CMD-ST 0 1 X X 0 X X 0`
665			`; AND 0 1 0 0 0 0 0 0`
666			`LOAD sF,C1`
667			`AND sF,sB`
668			`SUB sF,40`
669			`JUMP Z,put_command_allowed`
670
671			`;`
672			`; ELSE DATA_TRANSFER_ALLOWED & COMMAND_ALLOWED => 0`
673			`;`
674			`;JUMP put_error_code`
675			`; REVISAR ???`
676			`;AND s5,01`
677			`RETURN`
678
679
680			`put_error_code:`
681			`;`
682			`; ERROR SIGNAL`
683			`;`
684			`; PUT ERROR CODE`
685			`;`
686			`LOAD sF,04`
687			`OUTPUT sF,CONTROL_OUT`
688			`CALL soft_reset`
689			`LOAD s5,ERROR_MY_STATUS`
690			`RETURN`
691	5	armando	`;JUMP initialization (STACK OVERFLOW???)`
692	2	armando
693			`soft_reset:`
694			`LOAD sD,SOFT_RESET`
695			`LOAD sF,CONTROL`
696			`CALL write_ide_register`
697			`LOAD sF,FF`
698			`CALL wait_loop`
699			`LOAD sF,FF`
700			`CALL wait_loop`
701			`LOAD sF,FF`
702			`CALL wait_loop`
703			`LOAD sF,FF`
704			`CALL wait_loop`
705			`LOAD sD,00`
706			`LOAD sF,CONTROL`
707			`CALL write_ide_register`
708			`RETURN`
709
710			`put_data_request_allowed:`
711			`;`
712			`; DRQ ALLOW -> MY STATUS REGISTER`
713			`;`
714			`AND s5,FD`
715			`LOAD sF,DATA_TRANSFER_ALLOWED`
716			`OR s5,sF`
717			`RETURN`
718
719			`put_command_allowed:`
720			`;`
721			`; DRQ ALLOW -> MY STATUS REGISTER`
722			`;`
723			`AND s5,FB`
724			`LOAD sF,COMMAND_ALLOWED`
725			`OR s5,sF`
726			`RETURN`
727
728			`ADDRESS FF`
729
730			`interrupt:`
731			`RETURNI ENABLE`