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armando |
KCPSM Assembler log file for program 'cfreader.psm'.
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Generated by KCPSM version 1.10
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Ken Chapman (Xilinx Ltd) 2002.
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Addr Code
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00 ;--===========================================================================--
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00 ;--
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00 ;-- CF SECTOR READER
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00 ;--
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00 ;-- - SEPTEMBER 2002
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00 ;-- - UPV / EHU.
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00 ;--
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00 ;-- Design units : FAT FILE LOADER
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00 ;--
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00 ;-- File name : cf_sector_reader.txt
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00 ;--
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00 ;-- Purpose : READ RAW SECTORS FROM CF
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00 ;--
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00 ;-- Library : -
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00 ;--
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00 ;-- Languaje : ASSEMBLER FOR XILINX PICOBLAZE
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00 ;--
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00 ;-- Compiler : KCPSM ASSEMBLER V1.25
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00 ;--
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00 ;-- Debugger : PSM DEBUG V1.00
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00 ;--===========================================================================--
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00 ;-------------------------------------------------------------------------------
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00 ;-- Revision list
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00 ;-- Version Author Date Changes
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00 ;--
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00 ;-- 260902 Armando Astarloa 27 September 2002 -
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00 ;-- 241002 Armando Astarloa 27 October 2002 Reset on error
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00 ;-- 031202 Armando Astarloa 27 December 2002 Load LBA information from data bus
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00 ;-- 120103 Armando Astarloa 12 January 2003 Quit status check when words reading
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00 ;-- 290103 Armando Astarloa 29 January 2003 Reset function. Reset after error
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00 ;-- 050503 Armando Astarloa 02 May 2003 Allow not all bytes of the sector read.
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00 ;-- do_reset_and_retry state
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00 ;-- 160503 Armando Astarloa 15 May 2003 Complete sector reading
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00 ;-- 170603 Armando Astarloa 17 June 2003 Bug in words per sector read
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00 ;-- 230603 Armando Astarloa 24 June 2003 Quit soft reset (KCPSM v.1002 has reset)
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00 ;--
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00 ;-------------------------------------------------------------------------------
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00 ;-- Description : DUMMY CF SECTORS READ
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00 ;-------------------------------------------------------------------------------
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00 ;--
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00 ;-- CONSTANT DEFINITIONS
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00 ;--
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00 CONSTANT DELAY1, 03
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00 ; 50 MHZ DELAY1 => T(clk_i) => fastloop=DELAY1*T*2= 120ns sF=1 => delay= sF*fastloop
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00 ; 50 MHZ DELAY1=03 => T=20NS => fastloop=3*20*2= 120ns sF=1 => delay= 120ns
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00 CONSTANT IDENTIFY_COMMAND, EC
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00 CONSTANT WRITE_SECTOR_COMMAND, 30
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00 CONSTANT READ_SECTOR_COMMAND, 20
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00 CONSTANT WRITE_SEC_FEATURE, 00
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00 CONSTANT SOFT_RESET, 04
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00 ;--
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00 ;-- RAM REGISTERS
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00 ;--
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00 ;
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00 ; s0
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00 ; s1
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00 ; s2
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00 ; s3 -> WISHBONE CONTROL
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00 ; s4 -> REGISTERS STACK
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00 ; s5 -> MY_STATUS
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00 ; D3 = ERROR
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00 ; D2 = DATA TRANSFER ALLOWED (0 NOT / 1 YES)
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00 ; D1 = COMMAND ALLOWED (NOT BUSY) (0 NOT / 1 YES)
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00 ; D0 = SECTOR AVAILABLE (0 NOT / 1 YES)
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00 CONSTANT SECTOR_AVAILABLE, 01
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00 CONSTANT COMMAND_ALLOWED, 02
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00 CONSTANT DATA_TRANSFER_ALLOWED, 04
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00 CONSTANT ERROR_MY_STATUS, 08
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00 ; s6 -> WORDS_READ
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00 ; s7 -> LBA_7_0
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00 ; s8 -> LBA_15_8
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00 ; s9 -> LBA_23_16
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00 ; sA -> LD_LBA_27_24
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00 ; sB -> data[7:0] in ide
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00 ; sC -> data[15:8] in ide
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00 ; sD -> data[7:0] out ide
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00 ; sE -> data[15:8] out ide
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00 ; sF -> acummulator
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00 ;
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00 ;--
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00 ;-- OUTPUT PORTS
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00 ;--
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00 ;--
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00 ;-- IDE INTERFACE PORTS - OUTPUTS
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00 ;--
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00 CONSTANT DATA_IDE_OUT_7_0, 00
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00 CONSTANT DATA_IDE_OUT_15_8, 01
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00 CONSTANT IDE_CONTROL_OUT, 02
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00 ; D7 =
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00 ; D6 =
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00 ; D5 =
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00 ; D4 =
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00 ; D3 =
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00 ; D2 =
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00 ; D1 = NIOWR
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00 ; D0 = NIORD
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00 CONSTANT NIOWR, FD
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00 CONSTANT NIORD, FE
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00 CONSTANT IDE_ADDRESS_OUT, 03
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00 ; D7 =
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00 ; D6 =
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00 ; D5 =
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00 ; D4 = NCE1
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00 ; D3 = NCE0
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00 ; D2 = A2
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00 ; D1 = A1
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00 ; D0 = A0
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00 ;
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00 ; WRITE IDE REGISTERS
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00 ;
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00 ; NCE1/NCE0/ A2/ A1/ A0
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00 CONSTANT CONTROL, 0E ; 000 0 1 1 1 0
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00 CONSTANT DATA, 10 ; 000 1 0 0 0 0
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00 CONSTANT FEATURE, 11 ; 000 1 0 0 0 1
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00 CONSTANT SECTOR_COUNT, 12 ; 000 1 0 0 1 0
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00 CONSTANT LBA_7_0, 13 ; 000 1 0 0 1 1
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00 CONSTANT LBA_15_8, 14 ; 000 1 0 1 0 0
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00 CONSTANT LBA_23_16, 15 ; 000 1 0 1 0 1
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00 CONSTANT LD_LBA_27_24, 16 ; 000 1 0 1 1 0
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00 CONSTANT COMMAND, 17 ; 000 1 0 1 1 1
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00 CONSTANT CF_OFF, 18 ; 000 1 1 0 0 0
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00 ;
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00 ; READ IDE REGISTERS
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00 ; NCE1/NCE0/ A2/ A1/ A0
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00 CONSTANT A_STATUS, 0E ; 000 0 1 1 1 0
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00 CONSTANT STATUS, 17 ; 000 1 0 1 1 1
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00 ;--
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00 ;-- WISHBONE INTERFACE PORTS - OUTPUTS
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00 ;--
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00 CONSTANT DATA_WB_OUT_7_0, 04
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00 CONSTANT DATA_WB_OUT_15_8, 05
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00 CONSTANT CONTROL_WB_OUT, 06
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00 ; D7 =
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00 ; D6 =
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00 ; D5 =
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00 ; D4 =
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00 ; D3 =
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00 ; D2 =
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00 ; D1 = TAG0_WORD_AVAILABLE
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00 ; D0 = ACK_CF_READER
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00 CONSTANT ACK_CF_READER, 01
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00 CONSTANT TAG0_WORD_AVAILABLE, 02
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00 ;--
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00 ;-- BUS CONTROL SIGNALS
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00 ;--
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00 CONSTANT CONTROL_OUT, 07
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00 ; D7 =
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00 ; D6 =
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00 ; D5 =
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00 ; D4 =
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00 ; D3 =
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00 ; D2 = ERROR
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00 ; D1 = WB_BUS_WRITE_ENABLE
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00 ; D0 = IDE_BUS_WRITE_ENABLE
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00 CONSTANT IDE_BUS_WRITE_ENABLE, 01
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00 CONSTANT WB_BUS_WRITE_ENABLE, 02
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00 CONSTANT ERROR, 04
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00 ;--
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00 ;-- INPUT PORTS
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00 ;--
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00 ;--
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00 ;-- IDE INTERFACE PORTS - INPUTS
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00 ;--
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00 CONSTANT DATA_IDE_IN_7_0, 00
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00 CONSTANT DATA_IDE_IN_15_8, 01
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00 ;--
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00 ;-- WISHBONE INTERFACE PORTS - INPUTS
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00 ;--
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00 CONSTANT CONTROL_WB_IN, 02
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00 ; D7 =
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00 ; D6 =
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00 ; D5 =
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00 ; D4 = WB_A0
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00 ; D3 = -
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00 ; D2 = W_WE
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00 ; D1 = TAG1_WORD_REQUEST
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00 ; D0 = STROBE_CF_READER
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00 ;
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00 ; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 0
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00 CONSTANT WRITE_LBA_15_0, 05
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00 ; STROBE_CF_READER = 1 & W_WE=1 & WB_A0 = 1
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00 CONSTANT WRITE_LBA_27_16, 15
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00 CONSTANT STROBE_CF_READER_AND_RD, 01
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00 CONSTANT TAG1_WORD_REQUEST, 02
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00 CONSTANT W_WE, 04
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00
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00
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00 ;--
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00 ;-- WISHBONE INTERFACE PORTS - INPUTS
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00 ;--
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00 CONSTANT DATA_WB_IN_7_0, 03
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00 CONSTANT DATA_WB_IN_15_8, 04
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00 ;--
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00 ;-- REGISTERS INITIALIZATION
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00 ;--
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00 inicialization:
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00 ;
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00 ; BUS CONTROL : WRITE NOT ENABLE
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00 ;
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00 0F00 LOAD sF, 00
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01 EF07 OUTPUT sF, CONTROL_OUT[07]
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02 ;
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02 ; WISHBONE BUS INIZIALIZATION
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02 ;
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02 0F00 LOAD sF, 00
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03 EF04 OUTPUT sF, DATA_WB_OUT_7_0[04]
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04 EF05 OUTPUT sF, DATA_WB_OUT_15_8[05]
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05 EF06 OUTPUT sF, CONTROL_WB_OUT[06]
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06 ;
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06 ; IDE BUS INICIALIZATION
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06 ;
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06 0F00 LOAD sF, 00
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07 EF00 OUTPUT sF, DATA_IDE_OUT_7_0[00]
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08 EF01 OUTPUT sF, DATA_IDE_OUT_15_8[01]
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09 0F18 LOAD sF, 18
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0A EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]
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0B 0FFF LOAD sF, FF
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0C EF02 OUTPUT sF, IDE_CONTROL_OUT[02]
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0D ;
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0D ; WAIT FOR 210NS*31 (RESET DELAY)
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| 227 |
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0D ;
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0D 0500 LOAD s5, 00
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0E 0600 LOAD s6, 00
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0F 0FFF LOAD sF, FF
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10 8347 CALL wait_loop[47]
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11 83CB CALL soft_reset[CB]
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12 0FFF LOAD sF, FF
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13 8347 CALL wait_loop[47]
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14 0FFF LOAD sF, FF
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15 8347 CALL wait_loop[47]
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16 0FFF LOAD sF, FF
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17 8347 CALL wait_loop[47]
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18 main:
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| 240 |
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18 ;
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18 ; CHECK WISHBONE BUS
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| 242 |
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18 ;
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18 ; wait state for stb_i deassertion
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18 ;LOAD sF,01
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18 ;CALL wait_loop
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18 CFF1 AND sF, sF
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| 247 |
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19 CFF1 AND sF, sF
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| 248 |
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1A CFF1 AND sF, sF
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| 249 |
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1B CFF1 AND sF, sF
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| 250 |
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1C A302 INPUT s3, CONTROL_WB_IN[02]
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| 251 |
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1D ;
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| 252 |
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1D ; CHECK STROBE & READ
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| 253 |
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1D ;
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| 254 |
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1D CF30 LOAD sF, s3
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| 255 |
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1E 6F05 SUB sF, WRITE_LBA_15_0[05]
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| 256 |
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1F 912A JUMP Z, store_lba_15_0[2A]
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| 257 |
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20 CF30 LOAD sF, s3
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| 258 |
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21 6F15 SUB sF, WRITE_LBA_27_16[15]
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| 259 |
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22 912F JUMP Z, store_lba_27_16[2F]
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| 260 |
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23 CF30 LOAD sF, s3
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| 261 |
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24 6F01 SUB sF, STROBE_CF_READER_AND_RD[01]
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| 262 |
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25 9136 JUMP Z, put_data_in_wb_bus[36]
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| 263 |
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26 ;
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| 264 |
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26 ; IF NOT READ REQUEST MAINTAIN SIGNAL
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| 265 |
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26 ;
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| 266 |
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26 0F00 LOAD sF, 00
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| 267 |
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27 EF07 OUTPUT sF, CONTROL_OUT[07]
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| 268 |
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28 EF06 OUTPUT sF, CONTROL_WB_OUT[06]
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| 269 |
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29 8118 JUMP main[18]
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| 270 |
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2A store_lba_15_0:
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| 271 |
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2A ; DATA_WB_IN_7_0 -> s7 LBA_7_0
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| 272 |
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2A A703 INPUT s7, DATA_WB_IN_7_0[03]
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| 273 |
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2B ; DATA_WB_IN_15_8 -> s8 LBA_15_8
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| 274 |
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2B A804 INPUT s8, DATA_WB_IN_15_8[04]
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| 275 |
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2C ; SECTOR AVAILABLE / COMMAND AVAILABLE -> 0
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| 276 |
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2C 0F00 LOAD sF, 00
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| 277 |
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2D C5F1 AND s5, sF
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| 278 |
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2E 813E JUMP wishbone_ack[3E]
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| 279 |
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2F store_lba_27_16:
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| 280 |
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2F ; DATA_WB_IN_7_0 -> s9 LBA_23_16
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| 281 |
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2F A903 INPUT s9, DATA_WB_IN_7_0[03]
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| 282 |
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30 ; DATA_WB_IN_15_8 -> s10 LD_LBA_27_24
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| 283 |
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30 AA04 INPUT sA, DATA_WB_IN_15_8[04]
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| 284 |
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31 ; SECTOR AVAILABLE -> 0
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| 285 |
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31 ; antes 020503 LOAD sF,FE
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| 286 |
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31 0F00 LOAD sF, 00
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| 287 |
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32 C5F1 AND s5, sF
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| 288 |
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33 813E JUMP wishbone_ack[3E]
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| 289 |
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34 do_reset_and_retry:
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| 290 |
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34 83CB CALL soft_reset[CB]
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| 291 |
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35 0500 LOAD s5, 00
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| 292 |
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36 put_data_in_wb_bus:
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| 293 |
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36 8396 CALL read_word_from_cf[96]
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| 294 |
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37 ; check for error
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| 295 |
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37 CF50 LOAD sF, s5
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| 296 |
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38 1F08 AND sF, ERROR_MY_STATUS[08]
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| 297 |
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39 9534 JUMP NZ, do_reset_and_retry[34]
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| 298 |
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3A EB04 OUTPUT sB, DATA_WB_OUT_7_0[04]
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| 299 |
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3B EC05 OUTPUT sC, DATA_WB_OUT_15_8[05]
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| 300 |
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3C ;
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| 301 |
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3C ; ENABLE WB ENABLE
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| 302 |
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3C ;
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| 303 |
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3C 0F02 LOAD sF, WB_BUS_WRITE_ENABLE[02]
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| 304 |
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3D EF07 OUTPUT sF, CONTROL_OUT[07]
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| 305 |
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3E wishbone_ack:
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| 306 |
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3E ;
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| 307 |
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3E ; WISHBONE ACK
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| 308 |
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3E ;
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| 309 |
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3E 0F01 LOAD sF, ACK_CF_READER[01]
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| 310 |
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3F EF06 OUTPUT sF, CONTROL_WB_OUT[06]
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| 311 |
|
|
40 ; null - wait state
|
| 312 |
|
|
40 ;
|
| 313 |
|
|
40 CFF1 AND sF, sF
|
| 314 |
|
|
41 CFF1 AND sF, sF
|
| 315 |
|
|
42 CFF1 AND sF, sF
|
| 316 |
|
|
43 CFF1 AND sF, sF
|
| 317 |
|
|
44 ; WISHBONE MASTER MUST CHECK ACK SIGNAL
|
| 318 |
|
|
44 ; IN THE RISING EDGE OF THE CLOCK AND DEASSERT
|
| 319 |
|
|
44 ; STROBE SIGNAL. SLAVE AUTOMATICALLY DEASSERT ACK
|
| 320 |
|
|
44 ;
|
| 321 |
|
|
44 0F00 LOAD sF, 00
|
| 322 |
|
|
45 EF06 OUTPUT sF, CONTROL_WB_OUT[06]
|
| 323 |
|
|
46 ;OUTPUT sF,CONTROL_OUT
|
| 324 |
|
|
46 8118 JUMP main[18]
|
| 325 |
|
|
47 wait_loop:
|
| 326 |
|
|
47 ;
|
| 327 |
|
|
47 ; SOFTWARE DELAY LOOP
|
| 328 |
|
|
47 ; TAKES SLOW LOOP VALUE FROM sF
|
| 329 |
|
|
47 ;
|
| 330 |
|
|
47 ; TWO CYCLES PER INSTRUCTION
|
| 331 |
|
|
47 ;
|
| 332 |
|
|
47 ; SLOW LOOP 3 INSTRUCTIONS * sF
|
| 333 |
|
|
47 ; FAST LOOP 2 INSTRUCTIONS * DELAY1
|
| 334 |
|
|
47 ; 50 MHZ DELAY1=0A => T=20NS => fl=3*20*2= 120ns sF=1 => delay= 120ns
|
| 335 |
|
|
47 C1F0 LOAD s1, sF
|
| 336 |
|
|
48 slow_loop:
|
| 337 |
|
|
48 0003 LOAD s0, DELAY1[03]
|
| 338 |
|
|
49 fast_loop:
|
| 339 |
|
|
49 6001 SUB s0, 01
|
| 340 |
|
|
4A 9549 JUMP NZ, fast_loop[49]
|
| 341 |
|
|
4B 6101 SUB s1, 01
|
| 342 |
|
|
4C 9548 JUMP NZ, slow_loop[48]
|
| 343 |
|
|
4D 8080 RETURN
|
| 344 |
|
|
4E write_ide_register:
|
| 345 |
|
|
4E ;
|
| 346 |
|
|
4E ; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT
|
| 347 |
|
|
4E ;
|
| 348 |
|
|
4E EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]
|
| 349 |
|
|
4F ;
|
| 350 |
|
|
4F ; DATA OUT IDE
|
| 351 |
|
|
4F ;
|
| 352 |
|
|
4F ED00 OUTPUT sD, DATA_IDE_OUT_7_0[00]
|
| 353 |
|
|
50 EE01 OUTPUT sE, DATA_IDE_OUT_15_8[01]
|
| 354 |
|
|
51 ;
|
| 355 |
|
|
51 ; DATA OUT BUS ENABLE
|
| 356 |
|
|
51 ;
|
| 357 |
|
|
51 0F01 LOAD sF, IDE_BUS_WRITE_ENABLE[01]
|
| 358 |
|
|
52 EF07 OUTPUT sF, CONTROL_OUT[07]
|
| 359 |
|
|
53 ;
|
| 360 |
|
|
53 ; WAIT FOR 70 NS (MIN)
|
| 361 |
|
|
53 ; (120ns/50Mhz)
|
| 362 |
|
|
53 0F01 LOAD sF, 01
|
| 363 |
|
|
54 8347 CALL wait_loop[47]
|
| 364 |
|
|
55 ;
|
| 365 |
|
|
55 ; WRITE STROBE ON
|
| 366 |
|
|
55 ;
|
| 367 |
|
|
55 0FFD LOAD sF, NIOWR[FD]
|
| 368 |
|
|
56 EF02 OUTPUT sF, IDE_CONTROL_OUT[02]
|
| 369 |
|
|
57 ;
|
| 370 |
|
|
57 ; WAIT FOR 165NS (MIN)
|
| 371 |
|
|
57 ; (240ns/50Mhz)
|
| 372 |
|
|
57 ; 020503
|
| 373 |
|
|
57 0F02 LOAD sF, 02
|
| 374 |
|
|
58 8347 CALL wait_loop[47]
|
| 375 |
|
|
59 ;
|
| 376 |
|
|
59 ; WRITE STROBE OFF
|
| 377 |
|
|
59 ;
|
| 378 |
|
|
59 0FFF LOAD sF, FF
|
| 379 |
|
|
5A EF02 OUTPUT sF, IDE_CONTROL_OUT[02]
|
| 380 |
|
|
5B ;
|
| 381 |
|
|
5B ; WAIT FOR 20NS (MIN)
|
| 382 |
|
|
5B ; (410ns/50Mhz)
|
| 383 |
|
|
5B ; 020503
|
| 384 |
|
|
5B ;LOAD sF,01
|
| 385 |
|
|
5B ;CALL wait_loop
|
| 386 |
|
|
5B ;
|
| 387 |
|
|
5B ; CE AND ADRESSES OFF
|
| 388 |
|
|
5B ;
|
| 389 |
|
|
5B 0F18 LOAD sF, CF_OFF[18]
|
| 390 |
|
|
5C EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]
|
| 391 |
|
|
5D ;
|
| 392 |
|
|
5D ; WAIT FOR 30NS (MIN) (if delay of the two previos inst>30ns this is not necessary)
|
| 393 |
|
|
5D ; (put again 020503)
|
| 394 |
|
|
5D 0F01 LOAD sF, 01
|
| 395 |
|
|
5E 8347 CALL wait_loop[47]
|
| 396 |
|
|
5F ;
|
| 397 |
|
|
5F ; DATA OUT BUS DISABLE
|
| 398 |
|
|
5F ;
|
| 399 |
|
|
5F 0F00 LOAD sF, 00
|
| 400 |
|
|
60 EF07 OUTPUT sF, CONTROL_OUT[07]
|
| 401 |
|
|
61 ;
|
| 402 |
|
|
61 ; (put again 020503)
|
| 403 |
|
|
61 0F02 LOAD sF, 02
|
| 404 |
|
|
62 8347 CALL wait_loop[47]
|
| 405 |
|
|
63 8080 RETURN
|
| 406 |
|
|
64 read_ide_register:
|
| 407 |
|
|
64 ;
|
| 408 |
|
|
64 ; TAKE ADDRESS FROM SF REGISTER AND IT'S PUT INTO THE PORT
|
| 409 |
|
|
64 ;
|
| 410 |
|
|
64 EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]
|
| 411 |
|
|
65 ;
|
| 412 |
|
|
65 ; WAIT FOR 70 NS (MIN)
|
| 413 |
|
|
65 ;
|
| 414 |
|
|
65 0F01 LOAD sF, 01
|
| 415 |
|
|
66 8347 CALL wait_loop[47]
|
| 416 |
|
|
67 ;
|
| 417 |
|
|
67 ; READ STROBE ON
|
| 418 |
|
|
67 ; reset control_out (140503)
|
| 419 |
|
|
67 0F00 LOAD sF, 00
|
| 420 |
|
|
68 EF07 OUTPUT sF, CONTROL_OUT[07]
|
| 421 |
|
|
69 0FFE LOAD sF, NIORD[FE]
|
| 422 |
|
|
6A EF02 OUTPUT sF, IDE_CONTROL_OUT[02]
|
| 423 |
|
|
6B ;
|
| 424 |
|
|
6B ; WAIT FOR 165NS (MIN)
|
| 425 |
|
|
6B ;
|
| 426 |
|
|
6B 0F02 LOAD sF, 02
|
| 427 |
|
|
6C 8347 CALL wait_loop[47]
|
| 428 |
|
|
6D ;
|
| 429 |
|
|
6D ; TAKE DE DATA FROM IDE BUS
|
| 430 |
|
|
6D ;
|
| 431 |
|
|
6D AB00 INPUT sB, DATA_IDE_IN_7_0[00]
|
| 432 |
|
|
6E AC01 INPUT sC, DATA_IDE_IN_15_8[01]
|
| 433 |
|
|
6F ;
|
| 434 |
|
|
6F ; READ STROBE OFF
|
| 435 |
|
|
6F ;
|
| 436 |
|
|
6F 0FFF LOAD sF, FF
|
| 437 |
|
|
70 EF02 OUTPUT sF, IDE_CONTROL_OUT[02]
|
| 438 |
|
|
71 ;
|
| 439 |
|
|
71 ; WAIT FOR 20NS (MIN)
|
| 440 |
|
|
71 ;
|
| 441 |
|
|
71 ;LOAD sF,01
|
| 442 |
|
|
71 ;CALL wait_loop
|
| 443 |
|
|
71 ;
|
| 444 |
|
|
71 ; CE AND ADRESSES OFF
|
| 445 |
|
|
71 ;
|
| 446 |
|
|
71 0F18 LOAD sF, CF_OFF[18]
|
| 447 |
|
|
72 EF03 OUTPUT sF, IDE_ADDRESS_OUT[03]
|
| 448 |
|
|
73 ;
|
| 449 |
|
|
73 ; WAIT FOR 20NS (MIN)
|
| 450 |
|
|
73 ; (120ns/50mhz)
|
| 451 |
|
|
73 ;LOAD sF,01
|
| 452 |
|
|
73 ;CALL wait_loop
|
| 453 |
|
|
73 8080 RETURN
|
| 454 |
|
|
74 read_sector:
|
| 455 |
|
|
74 ;
|
| 456 |
|
|
74 ; WRITE ATA COMMANDS TO THE CF
|
| 457 |
|
|
74 ;
|
| 458 |
|
|
74 ;
|
| 459 |
|
|
74 ; IDE FEATURE REGISTER
|
| 460 |
|
|
74 ;
|
| 461 |
|
|
74 0D00 LOAD sD, WRITE_SEC_FEATURE[00]
|
| 462 |
|
|
75 0F11 LOAD sF, FEATURE[11]
|
| 463 |
|
|
76 834E CALL write_ide_register[4E]
|
| 464 |
|
|
77 ;
|
| 465 |
|
|
77 ; IDE SECTOR COUNT REGISTER
|
| 466 |
|
|
77 ;
|
| 467 |
|
|
77 0D01 LOAD sD, 01
|
| 468 |
|
|
78 0F12 LOAD sF, SECTOR_COUNT[12]
|
| 469 |
|
|
79 834E CALL write_ide_register[4E]
|
| 470 |
|
|
7A ;
|
| 471 |
|
|
7A ; IDE LBA_7_0
|
| 472 |
|
|
7A ;
|
| 473 |
|
|
7A CD70 LOAD sD, s7
|
| 474 |
|
|
7B 0F13 LOAD sF, LBA_7_0[13]
|
| 475 |
|
|
7C 834E CALL write_ide_register[4E]
|
| 476 |
|
|
7D ;
|
| 477 |
|
|
7D ; IDE LBA_15_8
|
| 478 |
|
|
7D ;
|
| 479 |
|
|
7D CD80 LOAD sD, s8
|
| 480 |
|
|
7E 0F14 LOAD sF, LBA_15_8[14]
|
| 481 |
|
|
7F 834E CALL write_ide_register[4E]
|
| 482 |
|
|
80 ;
|
| 483 |
|
|
80 ; IDE LBA_23_16
|
| 484 |
|
|
80 ;
|
| 485 |
|
|
80 CD90 LOAD sD, s9
|
| 486 |
|
|
81 0F15 LOAD sF, LBA_23_16[15]
|
| 487 |
|
|
82 834E CALL write_ide_register[4E]
|
| 488 |
|
|
83 ;
|
| 489 |
|
|
83 ; IDE LD_LBA_27_24
|
| 490 |
|
|
83 ;
|
| 491 |
|
|
83 ; LBA_27_42 OR WITH 1110
|
| 492 |
|
|
83 ; BIT7 : 1
|
| 493 |
|
|
83 ; BIT6 : LBA=1
|
| 494 |
|
|
83 ; BIT5 : 1
|
| 495 |
|
|
83 ; BIT4 : DRV=0
|
| 496 |
|
|
83 ;
|
| 497 |
|
|
83 ;
|
| 498 |
|
|
83 CFA0 LOAD sF, sA
|
| 499 |
|
|
84 2FE0 OR sF, E0
|
| 500 |
|
|
85 CDF0 LOAD sD, sF
|
| 501 |
|
|
86 0F16 LOAD sF, LD_LBA_27_24[16]
|
| 502 |
|
|
87 834E CALL write_ide_register[4E]
|
| 503 |
|
|
88 ;
|
| 504 |
|
|
88 ; IDE READ SECTOR COMMAND
|
| 505 |
|
|
88 ;
|
| 506 |
|
|
88 0D20 LOAD sD, READ_SECTOR_COMMAND[20]
|
| 507 |
|
|
89 0F17 LOAD sF, COMMAND[17]
|
| 508 |
|
|
8A 834E CALL write_ide_register[4E]
|
| 509 |
|
|
8B ;
|
| 510 |
|
|
8B ; PUT SECTOR ALLOWED FLAG INTO MY_STATUS
|
| 511 |
|
|
8B ;
|
| 512 |
|
|
8B ; 290103 Added data available check
|
| 513 |
|
|
8B retry_status_check:
|
| 514 |
|
|
8B 83B8 CALL cf_status_check[B8]
|
| 515 |
|
|
8C CF50 LOAD sF, s5
|
| 516 |
|
|
8D 1F08 AND sF, ERROR_MY_STATUS[08]
|
| 517 |
|
|
8E 9480 RETURN NZ
|
| 518 |
|
|
8F 0F04 LOAD sF, DATA_TRANSFER_ALLOWED[04]
|
| 519 |
|
|
90 CF51 AND sF, s5
|
| 520 |
|
|
91 ; LOOPS UNTIL SECTOR DATA IS AVAILABLE
|
| 521 |
|
|
91 918B JUMP Z, retry_status_check[8B]
|
| 522 |
|
|
92 0F01 LOAD sF, SECTOR_AVAILABLE[01]
|
| 523 |
|
|
93 C5F2 OR s5, sF
|
| 524 |
|
|
94 ;
|
| 525 |
|
|
94 ; RESET WORDS READ REGISTER
|
| 526 |
|
|
94 ;
|
| 527 |
|
|
94 06FF LOAD s6, FF
|
| 528 |
|
|
95 8080 RETURN
|
| 529 |
|
|
96 read_word_from_cf:
|
| 530 |
|
|
96 ;
|
| 531 |
|
|
96 ; CHECK IF THE SECTOR IS AVAILABLE
|
| 532 |
|
|
96 ;
|
| 533 |
|
|
96 0F01 LOAD sF, SECTOR_AVAILABLE[01]
|
| 534 |
|
|
97 CF51 AND sF, s5
|
| 535 |
|
|
98 ;
|
| 536 |
|
|
98 ; IF SECTOR_AVAILABLE=0 JUMP TO READ_NEW_SECTOR
|
| 537 |
|
|
98 ;
|
| 538 |
|
|
98 93AC CALL Z, read_new_sector[AC]
|
| 539 |
|
|
99 ; check for error
|
| 540 |
|
|
99 CF50 LOAD sF, s5
|
| 541 |
|
|
9A 1F08 AND sF, ERROR_MY_STATUS[08]
|
| 542 |
|
|
9B 9480 RETURN NZ
|
| 543 |
|
|
9C ;retry_status_check:
|
| 544 |
|
|
9C ;CALL cf_status_check
|
| 545 |
|
|
9C ;
|
| 546 |
|
|
9C ; CHECK IF DATA IS AVAILABLE
|
| 547 |
|
|
9C ;
|
| 548 |
|
|
9C ; 120103 - changed . When there is sector
|
| 549 |
|
|
9C ; available in the cf ram buffer it is not
|
| 550 |
|
|
9C ; necessary to check neither bsy or drq
|
| 551 |
|
|
9C ; only read words with the correct timing paramenters
|
| 552 |
|
|
9C ;
|
| 553 |
|
|
9C ;LOAD sF,DATA_TRANSFER_ALLOWED
|
| 554 |
|
|
9C ;AND sF,s5
|
| 555 |
|
|
9C ; LOOPS UNTIL SECTOR DATA IS AVAILABLE
|
| 556 |
|
|
9C ;JUMP Z,retry_status_check
|
| 557 |
|
|
9C ; end 120103
|
| 558 |
|
|
9C ;
|
| 559 |
|
|
9C ; IF 256 WORD READ -> SECTOR AVAILABLE=0
|
| 560 |
|
|
9C ;
|
| 561 |
|
|
9C 83A5 CALL read_word[A5]
|
| 562 |
|
|
9D C661 AND s6, s6
|
| 563 |
|
|
9E 91A1 JUMP Z, reset_word_READ[A1]
|
| 564 |
|
|
9F ;
|
| 565 |
|
|
9F ; DECREMENT NUMBER OF WORDS READ
|
| 566 |
|
|
9F ;
|
| 567 |
|
|
9F 6601 SUB s6, 01
|
| 568 |
|
|
A0 8080 RETURN
|
| 569 |
|
|
A1 reset_word_READ:
|
| 570 |
|
|
A1 ;
|
| 571 |
|
|
A1 ; IF 256 WORD READ -> SECTOR AVAILABLE=0
|
| 572 |
|
|
A1 ;
|
| 573 |
|
|
A1 ;ADD s7,01
|
| 574 |
|
|
A1 06FF LOAD s6, FF
|
| 575 |
|
|
A2 0FFE LOAD sF, FE
|
| 576 |
|
|
A3 C5F1 AND s5, sF
|
| 577 |
|
|
A4 8080 RETURN
|
| 578 |
|
|
A5
|
| 579 |
|
|
A5 read_word:
|
| 580 |
|
|
A5 ;
|
| 581 |
|
|
A5 ; READ WORDS FROM IDE DATA REGISTERS
|
| 582 |
|
|
A5 ;
|
| 583 |
|
|
A5 0F10 LOAD sF, DATA[10]
|
| 584 |
|
|
A6 8364 CALL read_ide_register[64]
|
| 585 |
|
|
A7 ;
|
| 586 |
|
|
A7 ; DATA ARE IN sB , sC
|
| 587 |
|
|
A7 ;
|
| 588 |
|
|
A7 ; DATA AVAILABLE SIGNAL IS STORED
|
| 589 |
|
|
A7 0F02 LOAD sF, TAG0_WORD_AVAILABLE[02]
|
| 590 |
|
|
A8 EF06 OUTPUT sF, CONTROL_WB_OUT[06]
|
| 591 |
|
|
A9 8080 RETURN
|
| 592 |
|
|
AA dummy_word_read:
|
| 593 |
|
|
AA 83A5 CALL read_word[A5]
|
| 594 |
|
|
AB 6601 SUB s6, 01
|
| 595 |
|
|
AC read_new_sector:
|
| 596 |
|
|
AC 83B8 CALL cf_status_check[B8]
|
| 597 |
|
|
AD CF50 LOAD sF, s5
|
| 598 |
|
|
AE 1F04 AND sF, DATA_TRANSFER_ALLOWED[04]
|
| 599 |
|
|
AF ;loops until previous non READ words are READ
|
| 600 |
|
|
AF 95AA JUMP NZ, dummy_word_read[AA]
|
| 601 |
|
|
B0 CF50 LOAD sF, s5
|
| 602 |
|
|
B1 1F08 AND sF, ERROR_MY_STATUS[08]
|
| 603 |
|
|
B2 9480 RETURN NZ
|
| 604 |
|
|
B3 CF50 LOAD sF, s5
|
| 605 |
|
|
B4 1F02 AND sF, COMMAND_ALLOWED[02]
|
| 606 |
|
|
B5 ; loops until commands are allowed
|
| 607 |
|
|
B5 06FF LOAD s6, FF
|
| 608 |
|
|
B6 91AC JUMP Z, read_new_sector[AC]
|
| 609 |
|
|
B7 8174 JUMP read_sector[74]
|
| 610 |
|
|
B8 cf_status_check:
|
| 611 |
|
|
B8 ;
|
| 612 |
|
|
B8 ; CF STATUS REGISTER READ
|
| 613 |
|
|
B8 ;
|
| 614 |
|
|
B8 0F17 LOAD sF, STATUS[17]
|
| 615 |
|
|
B9 8364 CALL read_ide_register[64]
|
| 616 |
|
|
BA ;
|
| 617 |
|
|
BA ; ERROR
|
| 618 |
|
|
BA ;
|
| 619 |
|
|
BA ; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR
|
| 620 |
|
|
BA ; MASK 0 0 0 0 0 0 0 1
|
| 621 |
|
|
BA ; ERR-ST X X X X X X X 1
|
| 622 |
|
|
BA ; AND 0 0 0 0 0 0 0 1
|
| 623 |
|
|
BA 0F01 LOAD sF, 01
|
| 624 |
|
|
BB CFB1 AND sF, sB
|
| 625 |
|
|
BC 95C6 JUMP NZ, put_error_code[C6]
|
| 626 |
|
|
BD ;
|
| 627 |
|
|
BD ; DATA REQUEST MASK (READY=1 : BUSY=0 : DRQ=1)
|
| 628 |
|
|
BD ;
|
| 629 |
|
|
BD ; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR
|
| 630 |
|
|
BD ; MASK 1 1 0 0 1 0 0 1
|
| 631 |
|
|
BD ; DRQ-ST 0 1 X X 1 X X 0
|
| 632 |
|
|
BD ; AND 0 1 0 0 1 0 0 0
|
| 633 |
|
|
BD 0FC9 LOAD sF, C9
|
| 634 |
|
|
BE CFB1 AND sF, sB
|
| 635 |
|
|
BF 6F48 SUB sF, 48
|
| 636 |
|
|
C0 91DA JUMP Z, put_data_request_allowed[DA]
|
| 637 |
|
|
C1
|
| 638 |
|
|
C1 ;
|
| 639 |
|
|
C1 ; COMMAND ALLOWED MASK (READY=1 : BUSY=0)
|
| 640 |
|
|
C1 ;
|
| 641 |
|
|
C1 ; BSY/DRDY/DWF/DSC/DRQ/CORR/0/ERR
|
| 642 |
|
|
C1 ; MASK 1 1 0 0 0 0 0 1
|
| 643 |
|
|
C1 ; CMD-ST 0 1 X X 0 X X 0
|
| 644 |
|
|
C1 ; AND 0 1 0 0 0 0 0 0
|
| 645 |
|
|
C1 0FC1 LOAD sF, C1
|
| 646 |
|
|
C2 CFB1 AND sF, sB
|
| 647 |
|
|
C3 6F40 SUB sF, 40
|
| 648 |
|
|
C4 91DE JUMP Z, put_command_allowed[DE]
|
| 649 |
|
|
C5 ;
|
| 650 |
|
|
C5 ; ELSE DATA_TRANSFER_ALLOWED & COMMAND_ALLOWED => 0
|
| 651 |
|
|
C5 ;
|
| 652 |
|
|
C5 ;JUMP put_error_code
|
| 653 |
|
|
C5 ; REVISAR ???
|
| 654 |
|
|
C5 ;AND s5,01
|
| 655 |
|
|
C5 8080 RETURN
|
| 656 |
|
|
C6 put_error_code:
|
| 657 |
|
|
C6 ;
|
| 658 |
|
|
C6 ; ERROR SIGNAL
|
| 659 |
|
|
C6 ;
|
| 660 |
|
|
C6 ; PUT ERROR CODE
|
| 661 |
|
|
C6 ;
|
| 662 |
|
|
C6 0F04 LOAD sF, 04
|
| 663 |
|
|
C7 EF07 OUTPUT sF, CONTROL_OUT[07]
|
| 664 |
|
|
C8 83CB CALL soft_reset[CB]
|
| 665 |
|
|
C9 0508 LOAD s5, ERROR_MY_STATUS[08]
|
| 666 |
|
|
CA 8080 RETURN
|
| 667 |
|
|
CB ;JUMP inicialization (STACK OVERFLOW???)
|
| 668 |
|
|
CB soft_reset:
|
| 669 |
|
|
CB 0D04 LOAD sD, SOFT_RESET[04]
|
| 670 |
|
|
CC 0F0E LOAD sF, CONTROL[0E]
|
| 671 |
|
|
CD 834E CALL write_ide_register[4E]
|
| 672 |
|
|
CE 0FFF LOAD sF, FF
|
| 673 |
|
|
CF 8347 CALL wait_loop[47]
|
| 674 |
|
|
D0 0FFF LOAD sF, FF
|
| 675 |
|
|
D1 8347 CALL wait_loop[47]
|
| 676 |
|
|
D2 0FFF LOAD sF, FF
|
| 677 |
|
|
D3 8347 CALL wait_loop[47]
|
| 678 |
|
|
D4 0FFF LOAD sF, FF
|
| 679 |
|
|
D5 8347 CALL wait_loop[47]
|
| 680 |
|
|
D6 0D00 LOAD sD, 00
|
| 681 |
|
|
D7 0F0E LOAD sF, CONTROL[0E]
|
| 682 |
|
|
D8 834E CALL write_ide_register[4E]
|
| 683 |
|
|
D9 8080 RETURN
|
| 684 |
|
|
DA put_data_request_allowed:
|
| 685 |
|
|
DA ;
|
| 686 |
|
|
DA ; DRQ ALLOW -> MY STATUS REGISTER
|
| 687 |
|
|
DA ;
|
| 688 |
|
|
DA 15FD AND s5, FD
|
| 689 |
|
|
DB 0F04 LOAD sF, DATA_TRANSFER_ALLOWED[04]
|
| 690 |
|
|
DC C5F2 OR s5, sF
|
| 691 |
|
|
DD 8080 RETURN
|
| 692 |
|
|
DE put_command_allowed:
|
| 693 |
|
|
DE ;
|
| 694 |
|
|
DE ; DRQ ALLOW -> MY STATUS REGISTER
|
| 695 |
|
|
DE ;
|
| 696 |
|
|
DE 15FB AND s5, FB
|
| 697 |
|
|
DF 0F02 LOAD sF, COMMAND_ALLOWED[02]
|
| 698 |
|
|
E0 C5F2 OR s5, sF
|
| 699 |
|
|
E1 8080 RETURN
|
| 700 |
|
|
FF ADDRESS FF
|
| 701 |
|
|
FF interrupt:
|
| 702 |
|
|
FF 80F0 RETURNI ENABLE
|
