URL https://opencores.org/ocsvn/fft2_size/fft2_size/trunk

Subversion Repositories fft2_size

[/] [fft2_size/] [fft_int_size/] [cascade_n.sv] - Blame information for rev 7

Details | Compare with Previous | View Log


`ifndef _cascade_n_
`define _cascade_n_
`include "butterfly.sv"
`include "yx_addr.sv"
`include "delay_line.sv"
 
module cascade_n #(parameter
        ADDR_WIDTH = 9,
        DATA_WIDTH = 32,
//      RES_WIDTH = DATA_WIDTH + 1,
        POW = 3, // 1...ADDR_WIDTH/2
        POW_WIDTH = (2**$clog2(ADDR_WIDTH) > ADDR_WIDTH - 1) ? $clog2(ADDR_WIDTH) : $clog2(ADDR_WIDTH) + 1
)(
        input aclr, clk, sink_ready,
        output [ADDR_WIDTH-1:0] sink_rdaddr,
        input signed [DATA_WIDTH-1:0] sink_Re, sink_Im,
        output reg sink_rdack,
        input [POW_WIDTH-1:0] pow, // 4..ADDR_WIDTH
        input [ADDR_WIDTH-1:0] addr_max,
 
        input [ADDR_WIDTH-1:0] source_rdaddr,
        input source_rdack,
        output reg signed [DATA_WIDTH:0] source_Re, source_Im,
        output reg source_ready
);
        localparam DELAY = (POW == 1 || POW == 2) ? 3 : 4;
 
        reg wr_buf = 1'b0, rd_buf = 1'b0;
        reg signed [DATA_WIDTH:0] mem_Re[2][2**ADDR_WIDTH];
        reg signed [DATA_WIDTH:0] mem_Im[2][2**ADDR_WIDTH];
 
        reg [ADDR_WIDTH-1:0] cnt, cnt_dly;
        reg sop = 1'b0;
        wire [ADDR_WIDTH-1:0] wraddr;
        wire wrvalid;
        wire [DATA_WIDTH:0] bf_Re, bf_Im;
 
        always @(posedge clk, posedge aclr)
                if (aclr)
                        cnt <= '0;
                else if (!sink_ready || sink_rdack || cnt == addr_max)
                        cnt <= '0;
                else
                        cnt <= cnt + 1'b1;
 
        yx_addr #(.WIDTH(ADDR_WIDTH), .POW(POW)) yx0(.cnt, .yx_cnt(sink_rdaddr));
 
        always_ff @(posedge clk) begin
                sink_rdack <= cnt == addr_max - 1'b1; // at last addr
                sop <= cnt == 'h0;
        end
 
        butterfly #(.DATA_WIDTH(DATA_WIDTH), .POW(POW)) bf( // 3,4 clocks delay
                .clk, .sync(sop), .sink_Re, .sink_Im, // y, x
                .source_Re(bf_Re), .source_Im(bf_Im) // y, x
        );
 
        // Delay line. Butterfly (3 or 4) + memory read (1)
        delay_lines_reg #(.DELAY(DELAY + 1), .WIDTH(ADDR_WIDTH)) dly0(
                .aclr(1'b0), .sclr(1'b0), .clock(clk), .clock_ena(1'b1),
                .sig_in(cnt), .sig_out(cnt_dly)
        );
 
        delay_line_reg #(.DELAY(DELAY + 1)) dly1(
                .aclr, .sclr(1'b0), .clock(clk), .clock_ena(1'b1),
                .sig_in(sink_ready), .sig_out(wrvalid)
        );
 
        yx_addr #(.WIDTH(ADDR_WIDTH), .POW(POW)) yx1(.cnt(cnt_dly), .yx_cnt(wraddr));
 
        always_ff @(posedge clk)
                if (wrvalid)
                        begin
                                mem_Re[wr_buf][wraddr] <= bf_Re;
                                mem_Im[wr_buf][wraddr] <= bf_Im;
                        end
 
        always_ff @(posedge clk) begin
                source_Re <= mem_Re[rd_buf][source_rdaddr];
                source_Im <= mem_Im[rd_buf][source_rdaddr];
        end
 
        generate
                if (POW == ADDR_WIDTH)
                        begin
                                always_ff @(posedge clk, posedge aclr)
                                        if (aclr)
                                                source_ready <= 1'b0;
                                        else if (wrvalid && cnt_dly == 2**(POW-1)) // last cascade, ready to line read
                                                source_ready <= 1'b1;
                                        else if (source_rdack) // end
                                                source_ready <= 1'b0;
                        end
                else
                        begin
                                always_ff @(posedge clk, posedge aclr)
                                        if (aclr)
                                                source_ready <= 1'b0;
                                        else if (pow == POW && wrvalid && cnt_dly == 2**(POW-1)) // last cascade, ready to line read
                                                source_ready <= 1'b1;
                                        else if (wrvalid && wraddr == 2**POW)
                                                source_ready <= 1'b1;
                                        else if (source_rdack) // end
                                                source_ready <= 1'b0;
                        end
        endgenerate
 
        always_ff @(posedge clk, posedge aclr)
                if (aclr)
                        wr_buf <= 1'b0;
                else if (wrvalid && cnt_dly == addr_max)
                        wr_buf <= !wr_buf;
 
        always_ff @(posedge clk, posedge aclr)
                if (aclr)
                        rd_buf <= 1'b0;
                else if (source_ready && source_rdack)
                        rd_buf <= !rd_buf;
 
endmodule :cascade_n
 
`endif

Line No.	Rev	Author	Line
1	7	Papayaved	`ifndef _cascade_n_
2			`define _cascade_n_
3			`include "butterfly.sv"
4			`include "yx_addr.sv"
5			`include "delay_line.sv"
6
7			`module cascade_n #(parameter`
8			`ADDR_WIDTH = 9,`
9			`DATA_WIDTH = 32,`
10			`// RES_WIDTH = DATA_WIDTH + 1,`
11			`POW = 3, // 1...ADDR_WIDTH/2`
12			`POW_WIDTH = (2**$clog2(ADDR_WIDTH) > ADDR_WIDTH - 1) ? $clog2(ADDR_WIDTH) : $clog2(ADDR_WIDTH) + 1`
13			`)(`
14			`input aclr, clk, sink_ready,`
15			`output [ADDR_WIDTH-1:0] sink_rdaddr,`
16			`input signed [DATA_WIDTH-1:0] sink_Re, sink_Im,`
17			`output reg sink_rdack,`
18			`input [POW_WIDTH-1:0] pow, // 4..ADDR_WIDTH`
19			`input [ADDR_WIDTH-1:0] addr_max,`
20
21			`input [ADDR_WIDTH-1:0] source_rdaddr,`
22			`input source_rdack,`
23			`output reg signed [DATA_WIDTH:0] source_Re, source_Im,`
24			`output reg source_ready`
25			`);`
26			`localparam DELAY = (POW == 1 \|\| POW == 2) ? 3 : 4;`
27
28			`reg wr_buf = 1'b0, rd_buf = 1'b0;`
29			`reg signed [DATA_WIDTH:0] mem_Re[2][2**ADDR_WIDTH];`
30			`reg signed [DATA_WIDTH:0] mem_Im[2][2**ADDR_WIDTH];`
31
32			`reg [ADDR_WIDTH-1:0] cnt, cnt_dly;`
33			`reg sop = 1'b0;`
34			`wire [ADDR_WIDTH-1:0] wraddr;`
35			`wire wrvalid;`
36			`wire [DATA_WIDTH:0] bf_Re, bf_Im;`
37
38			`always @(posedge clk, posedge aclr)`
39			`if (aclr)`
40			`cnt <= '0;`
41			`else if (!sink_ready \|\| sink_rdack \|\| cnt == addr_max)`
42			`cnt <= '0;`
43			`else`
44			`cnt <= cnt + 1'b1;`
45
46			`yx_addr #(.WIDTH(ADDR_WIDTH), .POW(POW)) yx0(.cnt, .yx_cnt(sink_rdaddr));`
47
48			`always_ff @(posedge clk) begin`
49			`sink_rdack <= cnt == addr_max - 1'b1; // at last addr`
50			`sop <= cnt == 'h0;`
51			`end`
52
53			`butterfly #(.DATA_WIDTH(DATA_WIDTH), .POW(POW)) bf( // 3,4 clocks delay`
54			`.clk, .sync(sop), .sink_Re, .sink_Im, // y, x`
55			`.source_Re(bf_Re), .source_Im(bf_Im) // y, x`
56			`);`
57
58			`// Delay line. Butterfly (3 or 4) + memory read (1)`
59			`delay_lines_reg #(.DELAY(DELAY + 1), .WIDTH(ADDR_WIDTH)) dly0(`
60			`.aclr(1'b0), .sclr(1'b0), .clock(clk), .clock_ena(1'b1),`
61			`.sig_in(cnt), .sig_out(cnt_dly)`
62			`);`
63
64			`delay_line_reg #(.DELAY(DELAY + 1)) dly1(`
65			`.aclr, .sclr(1'b0), .clock(clk), .clock_ena(1'b1),`
66			`.sig_in(sink_ready), .sig_out(wrvalid)`
67			`);`
68
69			`yx_addr #(.WIDTH(ADDR_WIDTH), .POW(POW)) yx1(.cnt(cnt_dly), .yx_cnt(wraddr));`
70
71			`always_ff @(posedge clk)`
72			`if (wrvalid)`
73			`begin`
74			`mem_Re[wr_buf][wraddr] <= bf_Re;`
75			`mem_Im[wr_buf][wraddr] <= bf_Im;`
76			`end`
77
78			`always_ff @(posedge clk) begin`
79			`source_Re <= mem_Re[rd_buf][source_rdaddr];`
80			`source_Im <= mem_Im[rd_buf][source_rdaddr];`
81			`end`
82
83			`generate`
84			`if (POW == ADDR_WIDTH)`
85			`begin`
86			`always_ff @(posedge clk, posedge aclr)`
87			`if (aclr)`
88			`source_ready <= 1'b0;`
89			`else if (wrvalid && cnt_dly == 2**(POW-1)) // last cascade, ready to line read`
90			`source_ready <= 1'b1;`
91			`else if (source_rdack) // end`
92			`source_ready <= 1'b0;`
93			`end`
94			`else`
95			`begin`
96			`always_ff @(posedge clk, posedge aclr)`
97			`if (aclr)`
98			`source_ready <= 1'b0;`
99			`else if (pow == POW && wrvalid && cnt_dly == 2**(POW-1)) // last cascade, ready to line read`
100			`source_ready <= 1'b1;`
101			`else if (wrvalid && wraddr == 2**POW)`
102			`source_ready <= 1'b1;`
103			`else if (source_rdack) // end`
104			`source_ready <= 1'b0;`
105			`end`
106			`endgenerate`
107
108			`always_ff @(posedge clk, posedge aclr)`
109			`if (aclr)`
110			`wr_buf <= 1'b0;`
111			`else if (wrvalid && cnt_dly == addr_max)`
112			`wr_buf <= !wr_buf;`
113
114			`always_ff @(posedge clk, posedge aclr)`
115			`if (aclr)`
116			`rd_buf <= 1'b0;`
117			`else if (source_ready && source_rdack)`
118			`rd_buf <= !rd_buf;`
119
120			`endmodule :cascade_n`
121
122			`endif

Browse

Tools

Subversion Repositories fft2_size

[/] [fft2_size/] [fft_int_size/] [cascade_n.sv] - Blame information for rev 7