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[/] [fft2_size/] [fft_int_size/] [size_ctrl.sv] - Blame information for rev 7

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`ifndef _size_ctrl_
`define _size_ctrl_
 
// FFT controller
module size_ctrl #(parameter
        POW = 14, // up to 2**POW FFT length
        DATA_WIDTH = 32,
        POW_WIDTH = (2**$clog2(POW) > POW - 1) ? $clog2(POW) : $clog2(POW) + 1
)(
        input clk, aclr,
        input [POW_WIDTH-1:0] pow, // 4..POW - FFT size is 2**pow
        input source_eop, // end of FFT
        output reg [POW_WIDTH-1:0] pow_reg, // current FFT pow
        output reg [POW-1:0] addr_max, // current last FFT data number
        output reg pow_ready, // pow ready to change
        output reg error, // error of parameter pow
 
        // input data stream
        input sink_sop, sink_eop, sink_valid,
        input signed [DATA_WIDTH-1:0] sink_Re, sink_Im,
        // output data stream
        output reg sop_reg, eop_reg, valid_reg,
        output reg signed [DATA_WIDTH-1:0] re_reg, im_reg
);
        reg [1:0] tsk_cnt = '0; // fft tasks counter
 
        always_ff @(posedge clk, posedge aclr)
                if (aclr)
                        begin
                                pow_reg <= POW_WIDTH'(POW);
                                addr_max <= {POW{1'b1}};
                        end
                else if (pow > POW)
                        begin
                                pow_reg <= POW_WIDTH'(POW);
                                addr_max <= {POW{1'b1}};
                        end
                else if (pow_ready && sink_sop && sink_valid)
                        begin
                                pow_reg <= pow;
                                addr_max <= {POW{1'b1}}>>(POW - pow);
                        end
 
        always_ff @(posedge clk, posedge aclr)
                if (aclr)
                        tsk_cnt <= '0;
                else if (sink_sop && sink_valid && source_eop)
                        ;
                else if (sink_sop && sink_valid)
                        tsk_cnt <= tsk_cnt + 1'b1;
                else if (source_eop)
                        tsk_cnt <= tsk_cnt - 1'b1;
 
        always_ff @(posedge clk, posedge aclr)
                if (aclr)
                        pow_ready <= 1'b0;
                else if (sink_sop && sink_valid)
                        pow_ready <= 1'b0;
                else if (source_eop && tsk_cnt == 'd1)
                        pow_ready <= 1'b1;
                else
                        pow_ready <= tsk_cnt == '0;
 
        always_ff @(posedge clk, posedge aclr)
                if (aclr)
                        error <= 1'b0;
                else if (sink_sop && sink_valid && (pow != pow_reg && !pow_ready || pow < 4 || pow > POW))
                        error <= 1'b1;
 
        always_ff @(posedge clk, posedge aclr)
                valid_reg <= (aclr) ? 1'b0 : sink_valid;
 
        always_ff @(posedge clk) begin
                sop_reg <= sink_sop;
                eop_reg <= sink_eop;
                re_reg <= sink_Re;
                im_reg <= sink_Im;
        end
 
endmodule :size_ctrl
 
`endif

Line No.	Rev	Author	Line
1	7	Papayaved	`ifndef _size_ctrl_
2			`define _size_ctrl_
3
4			`// FFT controller`
5			`module size_ctrl #(parameter`
6			`POW = 14, // up to 2**POW FFT length`
7			`DATA_WIDTH = 32,`
8			`POW_WIDTH = (2**$clog2(POW) > POW - 1) ? $clog2(POW) : $clog2(POW) + 1`
9			`)(`
10			`input clk, aclr,`
11			`input [POW_WIDTH-1:0] pow, // 4..POW - FFT size is 2**pow`
12			`input source_eop, // end of FFT`
13			`output reg [POW_WIDTH-1:0] pow_reg, // current FFT pow`
14			`output reg [POW-1:0] addr_max, // current last FFT data number`
15			`output reg pow_ready, // pow ready to change`
16			`output reg error, // error of parameter pow`
17
18			`// input data stream`
19			`input sink_sop, sink_eop, sink_valid,`
20			`input signed [DATA_WIDTH-1:0] sink_Re, sink_Im,`
21			`// output data stream`
22			`output reg sop_reg, eop_reg, valid_reg,`
23			`output reg signed [DATA_WIDTH-1:0] re_reg, im_reg`
24			`);`
25			`reg [1:0] tsk_cnt = '0; // fft tasks counter`
26
27			`always_ff @(posedge clk, posedge aclr)`
28			`if (aclr)`
29			`begin`
30			`pow_reg <= POW_WIDTH'(POW);`
31			`addr_max <= {POW{1'b1}};`
32			`end`
33			`else if (pow > POW)`
34			`begin`
35			`pow_reg <= POW_WIDTH'(POW);`
36			`addr_max <= {POW{1'b1}};`
37			`end`
38			`else if (pow_ready && sink_sop && sink_valid)`
39			`begin`
40			`pow_reg <= pow;`
41			`addr_max <= {POW{1'b1}}>>(POW - pow);`
42			`end`
43
44			`always_ff @(posedge clk, posedge aclr)`
45			`if (aclr)`
46			`tsk_cnt <= '0;`
47			`else if (sink_sop && sink_valid && source_eop)`
48			`;`
49			`else if (sink_sop && sink_valid)`
50			`tsk_cnt <= tsk_cnt + 1'b1;`
51			`else if (source_eop)`
52			`tsk_cnt <= tsk_cnt - 1'b1;`
53
54			`always_ff @(posedge clk, posedge aclr)`
55			`if (aclr)`
56			`pow_ready <= 1'b0;`
57			`else if (sink_sop && sink_valid)`
58			`pow_ready <= 1'b0;`
59			`else if (source_eop && tsk_cnt == 'd1)`
60			`pow_ready <= 1'b1;`
61			`else`
62			`pow_ready <= tsk_cnt == '0;`
63
64			`always_ff @(posedge clk, posedge aclr)`
65			`if (aclr)`
66			`error <= 1'b0;`
67			`else if (sink_sop && sink_valid && (pow != pow_reg && !pow_ready \|\| pow < 4 \|\| pow > POW))`
68			`error <= 1'b1;`
69
70			`always_ff @(posedge clk, posedge aclr)`
71			`valid_reg <= (aclr) ? 1'b0 : sink_valid;`
72
73			`always_ff @(posedge clk) begin`
74			`sop_reg <= sink_sop;`
75			`eop_reg <= sink_eop;`
76			`re_reg <= sink_Re;`
77			`im_reg <= sink_Im;`
78			`end`
79
80			`endmodule :size_ctrl`
81
82			`endif

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[/] [fft2_size/] [fft_int_size/] [size_ctrl.sv] - Blame information for rev 7