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---------------------------------------------------------------------
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---- ----
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---- FFT-based FIR Filter IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--
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-- File : fft_filter2_TB.vhd
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-- Generated : 08.08.05, 13:25
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.math_real.all;
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use IEEE.std_logic_arith.all;
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entity fft_filter2_tb is
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generic(
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iwidth : INTEGER := 16;
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owidth : INTEGER := 18;
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wwidth : INTEGER := 16;
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n : INTEGER := 10;
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v2 : INTEGER := 1;
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reall : INTEGER := 1;
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filtre:std_logic_vector(1 downto 0):="01");
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end fft_filter2_tb;
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architecture TB_ARCHITECTURE of fft_filter2_tb is
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constant tc:time:=12.5 ns; -- clock period =1/Fclk
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constant fs:real:=2500.0 ; --sampling frequency Fs in kHz
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constant nd:natural:=32; -- Fclk=nd*Fs, nd>29
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constant df:real:=5.0;--19.5*4.0; -- step of frequency in kHz to show the freq. characteristic
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constant f00:real:=00.0; -- init frequency in kHz
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constant magn:real:=30000.0; -- input signal magnitude
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constant Fl1:real:=100.0; -- low pass band
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constant Fh1:real:=200.0; -- high pass band
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constant Fl2:real:=100.0; -- low pass band
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constant Fh2:real:=200.0; -- high pass band
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component fft_filter2
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generic(
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iwidth : INTEGER := 8;
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owidth : INTEGER := 8;
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wwidth : INTEGER := 8;
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n : INTEGER := 7;
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v2 : INTEGER := 1;
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reall : INTEGER := 0 );
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port(
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CLK : in std_logic;
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RST : in std_logic;
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CE : in std_logic;
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START : in std_logic;
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DATAE : in std_logic;
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FILTER : in std_logic_vector(1 downto 0);
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L1 : in std_logic_vector((n-1) downto 0);
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H1 : in std_logic_vector((n-1) downto 0);
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L2 : in std_logic_vector((n-1) downto 0);
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H2 : in std_logic_vector((n-1) downto 0);
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DATAIRE : in std_logic_vector((iwidth-1) downto 0);
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DATAIIM : in std_logic_vector((iwidth-1) downto 0);
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READY : out std_logic;
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DATAORE : out std_logic_vector((owidth-1) downto 0);
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DATAOIM : out std_logic_vector((owidth-1) downto 0);
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SPRDY: out STD_LOGIC;
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WESP: out STD_LOGIC;
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SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
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SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
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FREQ:out STD_LOGIC_VECTOR (n-1 downto 0);
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SPEXP:out STD_LOGIC_VECTOR (3 downto 0) ) ;
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end component;
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signal CLK : std_logic:='1';
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signal RST : std_logic:='1';
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signal CE : std_logic;
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signal START : std_logic;
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signal DATAE,rdyd : std_logic;
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signal FILTER : std_logic_vector(1 downto 0);
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signal L1 : std_logic_vector((n-1) downto 0);
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signal H1 : std_logic_vector((n-1) downto 0);
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signal L2 : std_logic_vector((n-1) downto 0);
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signal H2 : std_logic_vector((n-1) downto 0);
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signal DATAIRE : std_logic_vector((iwidth-1) downto 0);
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signal DATAIIM : std_logic_vector((iwidth-1) downto 0);
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-- signal READY : std_logic;
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signal DATAORE : std_logic_vector((owidth-1) downto 0);
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signal DATAOIM : std_logic_vector((owidth-1) downto 0);
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signal clk_ce : std_logic := '1';
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signal DATA_IN,DATA_OUT,DATA_IN1,DATA_OUT1 : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
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signal rs,rc,f0,res,reslog,f1,frequ:real:=0.0;
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signal p,p1,p2,p3,p4,ENA,RDY : std_logic:='0';
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signal cnt,ct2:natural;
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signal ssc,scc,coun,freque:integer;
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constant a1:std_logic_vector((iwidth-1) downto 0):=
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CONV_STD_LOGIC_VECTOR(integer(0.99 * magn),iwidth);
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constant a0:std_logic_vector((iwidth-1) downto 0):=(others=>'0');
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constant nn:real:=real(2**n);
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begin
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FILTER<=filtre; --01 prosto filter, 10 filter+differenc-r
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CE<='1'; -- bez zamedlenija
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l1<=conv_std_logic_vector(integer(1.0*Fl1*nn/fs),n);
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h1<=conv_std_logic_vector(integer(1.0*Fh1*nn/fs),n);
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l2<=conv_std_logic_vector(integer(1.0*Fl2*nn/fs),n);
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h2<=conv_std_logic_vector(integer(1.0*Fh2*nn/fs),n);
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rst <= '1','0' after 103 ns;
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clk <= not clk after 0.5*tc; --Generator sinchroserii
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start<='0', '1' after 104 ns,'0' after 104 ns + 2*tc;
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QUANT:process(rst,CLK)
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begin
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if rst='1' then cnt<=0;
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elsif rising_edge(CLK) then
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if cnt= nd-1 then
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cnt<=0; ENA<='1' ;
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else
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cnt<=cnt+1;ENA<='0' ;
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end if;
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end if;
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end process;
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-- Unit Under Test port map
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UUT : fft_filter2
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generic map (
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iwidth => iwidth,
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owidth => owidth,
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wwidth => wwidth,
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n => n,
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v2 => v2,
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reall => reall
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)
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port map (CLK,RST,CE,
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START => START,
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DATAE => ENA,
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FILTER => FILTER,
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L1 => L1,
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H1 => H1,
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L2 => L2,
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H2 => H2,
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DATAIRE => DATA_In,
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DATAIIM => DATA_in1,
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READY => RDY,
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DATAORE =>DATAORE,
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DATAOIM =>DATAOIM
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);
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DATA_Out<=DATAORE(owidth-1 downto owidth-iwidth);
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DATA_Out1<=DATAOIM(owidth-1 downto owidth-iwidth);
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EPOCH:process begin
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--wait for 1500*tc*nd;
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loop
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p <= '0'; wait for (1024*nd-1)*tc;-- 0.25*1000 us; p <= '1'; wait for 4*12.5 ns;
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p<='1'; wait for tc;
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end loop;
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end process;
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SINE_GEN:process(clk,rst)
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variable i : real;
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variable j : integer;
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begin
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if rst = '1' then
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ct2<=0;
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rs <= 0.0;
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i := 0.0; j := 0;
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f0 <= f00;
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rdyd<='0';
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elsif clk = '1' and clk'event then
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rdyd<=rdy;
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if RDY='1' and rdyd='0' then
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if ct2=1 then
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ct2<=0;
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f0 <= f0 + df; f1 <= f0*2.5;
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else
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ct2<= ct2+1; -- counter of even/odd FFT
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end if;
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end if;
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-- if p = '1' then f0 <= f0 + df; f1 <= f0*2.5; end if;
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rc <= cos(f0 * 2.0 * math_pi * i/Fs); --0.0;----
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rs <= sin(f0 * 2.0 * math_pi * i/Fs);
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if ENA='1' then i:=i+1.0; end if;
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end if;
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end process;
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data_in1 <=(CONV_STD_LOGIC_VECTOR(integer(rs * magn),16));--others=>'0');-- ----
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data_in <= CONV_STD_LOGIC_VECTOR(integer(rc * magn),16); -- when p = '1' else x"0000";
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-- data_in <= CONV_STD_LOGIC_VECTOR(integer(0.9 * magn),16); -- when p = '1' else x"0000";
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-- data_in<=a0, a1 after 0.01 us, a0 after 14 us, a1 after 30 us,a0 after 35 us,
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-- a1 after 70 us, a0 after 74 us, a1 after 91 us,a0 after 105 us,
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-- a1 after 120 us, a0 after 123 us, a1 after 141 us,a0 after 155 us;
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-- p1 <= transport p after 10 us;
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process(clk,rst)
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variable couni : integer := 0;
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variable ss,sc,sm0,r,rsum : real;
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begin
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if rst = '1' then
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reslog <= -100.0;
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res<=0.0;
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elsif clk = '1' and clk'event then
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if RDY='1' and rdyd='0'and ct2=1 then
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coun <= 0;
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rsum:=0.0;
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end if;
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if coun /= 32 and ENA='1' then
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coun <= coun + 1;
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end if;
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if ENA='1' then
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if coun >= 0 and coun < 30 then
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ss := real(conv_integer(signed(data_out)))/magn;
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sc := real(conv_integer(signed(data_out1)))/magn;
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sm0 := ss*ss + sc*sc + 0.00000000000001; --; --
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r := 20.0 * log10(sqrt(sm0));
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rsum := rsum + sm0;
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end if;
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if coun = 31 then
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res<= sqrt(rsum/30.0) ;
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reslog <= 20.0 * log10(sqrt(rsum/30.0));
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freque<=integer(f0-df);
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end if;
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end if;
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end if;
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end process;
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ssc <= (conv_integer(signed(data_out)));
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scc <= (conv_integer(signed(data_out1)));
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end TB_ARCHITECTURE;
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