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unicore |
---------------------------------------------------------------------
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---- ----
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---- FFT Filter IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- DESCRIPTION:
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--
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-- FUNCTION FFT filter for FFT length of
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-- N= 64, 128, 256, 512, 1024, 2048 points,
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-- N= 2**n,
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-- ifft=0 forward FFT, =1 inverse FFT
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-- rams=1 - single data RAM, =2 dual data RAM
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-- input data width: iwidth = 8,...,16 bit signed
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-- output data width: owidth = 8,...,16 bit signed
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-- coefficient width : wwidth = 8,...,16 bit
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-- Synthesable for Virtex2, Spartan3 FPGAs.
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--
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-- FILES: FFT_Filtr2.VHD -- this file
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-- ALFFT_Core_slip.vhd - Slipping FFT with windowing
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-- FFTDPATH.vhd - data path of the FFT butterfly
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-- CONTROL.vhd - control unit of FFT processor
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-- ROM_COS.vhd - coefficient ROM
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-- RAM2X_2.vhd - dual data RAM block
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-- ALFFT_Core_sli.vhd - file of IFFT processor
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-- FFTDPATHi.vhd - data path of the IFFT butterfly
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-- CONTROL_i.vhd - control unit of IFFT processor
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-- ROM_COSi.vhd - coefficient ROM
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-- RAM1X_2.vhd - data RAM block
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-- DENORM.vhd -- denormalizer unit
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-- When redesign data RAM blocks
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-- the Core will fit another FPGA families
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--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
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library IEEE;
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use IEEE.std_logic_1164.all;
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Use IEEE.std_logic_arith.all;
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entity FFT_FILTER2 is
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generic (
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iwidth: INTEGER:=8 ; -- input data width =8...16
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owidth: INTEGER:=8 ; -- output data width =8...16
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wwidth: INTEGER:=8; -- coefficient width =8...16
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n:INTEGER:=7 ; -- 6,7,8,9,10,11 - transform length factor
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v2:INTEGER:=1 ; -- 1 - Virtex2
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reall:INTEGER:= 1 --wch. mass: 0 -complex 1 - 2 realnych
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);
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port (
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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CE: in STD_LOGIC; -- âûáîð êðèñòàëëà (ðàçðåøåíèå ÑLK)
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START: in STD_LOGIC; -- èìïóëüñ íà÷àëüíîãî ïóñêà
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DATAE: in STD_LOGIC; -- ñòðîá âõîäíûõ äàííûõ
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FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
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L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- ãðàíèöà ÔÍ×1
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H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- ãðàíèöà ÔÂ×1
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L2:in STD_LOGIC_VECTOR (n-1 downto 0); -- ãðàíèöà ÔÍ×2
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H2:in STD_LOGIC_VECTOR (n-1 downto 0); -- ãðàíèöà ÔÂ×2
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DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);--âõîä 1 ôèëüòðà
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DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);--âõîä 2 ôèëüòðà
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READY: out STD_LOGIC; --èìïóëüñ íà÷àëà âûâîäà ìàññèâà ðåçóëüòàòà
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DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);--âûõîä 1 ôèëüòðà
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DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);--âûõîä 2 ôèëüòðà
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SPRDY: out STD_LOGIC; --èìïóëüñ íà÷àëà âûâîäà ñïåêòðà
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WESP: out STD_LOGIC; -- ñòðîá îòñ÷åòîâ ñïåêòðà
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SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);--ðåàëüíàÿ ÷àñòü ñïåêòðîâ
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SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);--ìíèìàÿ ÷àñòü ñïåêòðîâ
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FREQ:out STD_LOGIC_VECTOR (n-1 downto 0); --íîìåð áèíà
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SPEXP:out STD_LOGIC_VECTOR (3 downto 0) --ïîðÿäîê ìàññèâà ñïåêòðîâ
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);
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end FFT_FILTER2;
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architecture ALFFT_CoreS of FFT_Filter2 is
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component ALFFT_Core is
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generic ( ifft: INTEGER:=0; -- 0- forward FFT
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rams:INTEGER:=2; -- 1,2
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iwidth: INTEGER:=8 ; -- input data width =8...16
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owidth: INTEGER:=8 ; -- output data width =8...16
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wwidth: INTEGER:=8; -- coefficient width =8...16
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n:INTEGER:=7 ;
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v2:INTEGER:=1 ; -- 1 - Virtex2
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slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2
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wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija
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reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
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); --4,5, 6,7,8,9,10,11 - transform length factor
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port (
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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CE: in STD_LOGIC;
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START: in STD_LOGIC;
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DATAE: in STD_LOGIC;
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DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
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DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
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FFTRDY: out STD_LOGIC;
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READY: out STD_LOGIC;
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WERES: out STD_LOGIC;
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ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);
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DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
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DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
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EXP: out STD_LOGIC_VECTOR (3 downto 0)
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);
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end component;
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component ALFFT_Corei is
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generic (width: INTEGER:=8 ; -- output data width =8...16
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wwidth: INTEGER:=8; -- coefficient width =8...16
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n:INTEGER:=7 ;
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v2:INTEGER:=1 ; -- 1 - Virtex2
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reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
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); --4,5, 6,7,8,9,10,11 - transform length factor
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port (
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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CE: in STD_LOGIC;
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START: in STD_LOGIC;
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FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
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L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
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H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
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L2:in STD_LOGIC_VECTOR (n-1 downto 0);
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H2:in STD_LOGIC_VECTOR (n-1 downto 0);
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DATAE: in STD_LOGIC;
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DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
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DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
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FFTRDY: out STD_LOGIC;
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READY: out STD_LOGIC;
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WERES: out STD_LOGIC;
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ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);
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DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);
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DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);
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EXP: out STD_LOGIC_VECTOR (3 downto 0)
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);
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end component ;
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component DENORM is
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generic (width: integer :=8 ; -- word width =8...24
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n:INTEGER:=7 ;
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reall:INTEGER:= 0 ;
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v2:INTEGER:=1 );-- 1 - Virtex2
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port (
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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CE: in STD_LOGIC;
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DATAE: in STD_LOGIC;
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START: in STD_LOGIC; --
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INIT: in STD_LOGIC; --
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WERES: in STD_LOGIC;
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SPRDY: in STD_LOGIC;
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ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);
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EXPI: in STD_LOGIC_VECTOR (3 downto 0);
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EXPF: in STD_LOGIC_VECTOR (3 downto 0);
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REDI: in STD_LOGIC_VECTOR (width-1 downto 0);
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IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);
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RDY: out STD_LOGIC;
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REDO: out STD_LOGIC_VECTOR (width-1 downto 0);
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IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)
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);
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end component;
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signal REDI: STD_LOGIC_VECTOR (owidth-1 downto 0);
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signal IMDI: STD_LOGIC_VECTOR (owidth-1 downto 0);
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signal REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
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signal IMDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
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signal INITOVERF: STD_LOGIC;
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signal WEspi: STD_LOGIC;
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signal sprdyi: STD_LOGIC;
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signal WEres: STD_LOGIC;
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signal fftrdy,ifftrdy: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
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signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
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signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
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signal MODE: STD_LOGIC_VECTOR (1 downto 0);
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signal SPREi,SPIMi,DRE,DIM:STD_LOGIC_VECTOR (owidth-1 downto 0);
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signal EXPF,EXPI:STD_LOGIC_VECTOR (3 downto 0);
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signal addrres,address: STD_LOGIC_VECTOR (n-1 downto 0);
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signal DIRE,DIIM: STD_LOGIC_VECTOR (iwidth-1 downto 0);
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constant vcc:STD_LOGIC:='1';
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signal sno1,sno2,sno3:integer;
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begin
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DIRE<=DATAIRE;-- & zeros;
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DIIM<=DATAIIM;-- & zeros;
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FFT_F: ALFFT_Core
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generic map (ifft=>0, -- 0- forward FFT
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rams=>2, -- 1,2
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iwidth=>iwidth, -- input data width =8...16
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owidth=>owidth, -- output data width =8...16
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wwidth=>wwidth, -- coefficient width =8...16
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n=>n,
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v2=>v2, -- 1 - Virtex2
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slip=> 2, -- 2 -- skolzassij s perekrytiem 2
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wnd=> 1, -- umnozaecca na okno 1 ,0 -bez umnozenija
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reall=>reall --wch. mass: 0 -complex 1 - 2 realnych
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) --4,5, 6,7,8,9,10,11 - transform length factor
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port map (CLK,RST,CE,
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START=>START,
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DATAE=>DATAE,
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DATAIRE=>DIRE,
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DATAIIM=>DIIM,
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FFTRDY=>fftrdy,
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READY=>sprdyi,
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WERES=>wespi,
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ADDRRES=>address,
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DATAORE=>SPREi,
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DATAOIM=>SPIMi,
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EXP=>expf
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);
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WESP<=wespi; -- spectr data output
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SPRDY<=sprdyi;
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SPRE<=SPREi;
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SPIM<=SPIMi;
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SPEXP<=expf;
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FREQ<=address;
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FFT_I: ALFFT_Corei
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generic map (width=>owidth, -- output data width =8...16
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wwidth=>wwidth, -- coefficient width =8...16
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n=>n,
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v2=>v2, -- 1 - Virtex2
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reall=>reall --wch. mass: 0 -complex 1 - 2 realnych
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) --4,5, 6,7,8,9,10,11 - transform length factor
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port map(CLK,RST,CE,
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START=>sprdyi,
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FILTER=>FILTER, --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
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L1=>L1, -- tsastoty filtrow
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H1=>H1, -- tsastoty filtrow
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L2=>L2,
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H2=>H2,
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DATAE=>wespi,
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DATAIRE=>SPREi,
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DATAIIM=>SPIMi,
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FFTRDY=>open,
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READY=>ifftrdy,
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WERES=>weres,
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ADDRRES=>addrres,
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DATAORE=>DRE,
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DATAOIM=>DIM,
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EXP=>EXPi
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);
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U_OUT: DENORM
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generic map(width=>owidth, -- word width =8...24
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n=>n,
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reall=>reall,
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v2=>v2)
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port map(CLK,RST,CE,
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DATAE=>DATAE,
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START=>start,
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INIT=> ifftrdy,
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WERES=>weres,
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ADDRRES=>addrres,
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SPRDY=>SPRDYi,
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EXPI=>expi,
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EXPF=>expf,
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REDI=>DRE,
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IMDI=>DIM,
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RDY=>READY,
|
296 |
|
|
REDO=>REDO,
|
297 |
|
|
IMDO=>IMDO
|
298 |
|
|
);
|
299 |
|
|
|
300 |
|
|
DATAORE<=REDO ;
|
301 |
|
|
DATAOIM<=IMDO ;
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
end ALFFT_CoreS;
|